A/D, D/C Converters for Image Signal Processing MN6577F, MN6577H Low Power 10-Bit 3-Volt CMOS A/D Converters for Image Processing Features Maximum conversion rate: 15 MSPS (min.) Linearity error: ±1.3 LSB (typ.) Differential linearity error: ±0.5 LSB (typ.) Power supply voltage: 3.0 V Power consumption: 40 mW (typ.) (fCLK=15 MHz) Applications Pin Assignment TQFP048-P-0707 QFH048-P-0707 N.C. VRBS VRB VR3 VR2 VR1 VRT VRTS N.C. AVSS AVDD AVDD MN6577F MN6577H 36 35 34 33 32 31 30 29 28 27 26 25 The MN6577F and MN6577H are high-speed 10-bit CMOS analog-to-digital converters for image processing applications. They use a half flash structure based on chopper comparators to achieve both high speed and low power consumption, and operate on a single 3 volt power supply. N.C. AVDD VIN N.C. N.C. N.C. AVSS DVSS DVDD LINDF OVF N.C. 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 Overview POWD NOE CLK MINV LINV N.C. DVDD DVSS DVSS DVDD TEST1 TEST2 Digital video equipment Digital image processing equipment D0 D1 D2 D3 D4 DVSS DVDDL D5 D6 D7 D8 D9 Digital television (TOP VIEW) 1 2 3 2 1 47 46 10 11 9 8 Upper comparator (5 bits) Encoder (5 bits) 12 D9 13 TEST2 14 TEST1 15 DVDD 16 DVSS 17 DVSS 18 DVDD 22 CLK NOE 23 24 POWD D8 D7 D6 D5 DDL D3 4 5 D4 6 DVSS 7 DV D2 D1 D0(LSB) OVF UNDF 29 Clock generator 31 5 Lower comparator (5 bits) 57 Lower encoder (5 bits) RTS VRB VRBS 20 21 DD LINV MINV AVSS 26 AV DD 25 AV 27 VR3 32 V R2 31 VR1 30 VRT 29 V 33 34 35 DD SS 39 V IN 38 AV DVDD 44 DV SS 43 AV 45 MN6577F, MN6577H A/D, D/C Converters for Image Signal Processing Block Diagram ( Pins 19, 28, 36, 37, 40, 41, 42, and 48 are no connention pins. ) 31 5 Error correction and data latch A/D, D/C Converters for Image Signal Processing MN6577F, MN6577H Pin Descriptions Pin No. 1 Symbol D0 Function Description Digital code output (LSB) 2 D1 Digital code output 3 D2 Digital code output 4 D3 Digital code output 5 D4 Digital code output 6 DVSS Ground for digital circuits 7 DVDD Power supply for digital circuits 8 D5 Digital code output 9 D6 Digital code output 10 D7 Digital code output 11 D8 Digital code output 12 D9 13 TEST2 Digital code output (MSB) 14 TEST1 Test mode selection pin 15 DVDD Power supply for digital circuits 16 DVSS Ground for digital circuits 17 DVSS Ground for digital circuits 18 DVDD Power supply for digital circuits 19 N.C. No connection 20 LINV Output inversion pin 21 MINV Output inversion pin Test mode selection pin 22 CLK Sampling clock 23 NOE Digital output enable pin 24 POWD Power down mode selection pin 25 AVDD Power supply for analog circuits 26 AVDD Power supply for analog circuits 27 AVSS Ground for analog circuits 28 N.C. No connection 29 VRTS Reference voltage power supply (TOP) 30 VRT Reference voltage input (TOP) 31 VR1 Intermediate reference voltage 32 VR2 Intermediate reference voltage 33 VR3 Intermediate reference voltage 34 VRB Reference voltage input (BOTTOM) 35 VRBS Reference voltage power supply (BOTTOM) 36 N.C. No connection 37 N.C. No connection 38 AVDD Power supply for analog circuits 39 VIN Analog signal input 40 N.C. No connection 3 MN6577F, MN6577H A/D, D/C Converters for Image Signal Processing Pin Description (continued) Pin No. 41 Symbol N.C. Function Description No connection 42 N.C. No connection 43 AVSS Ground for analog circuits 44 DVSS Ground for digital circuits 45 DVDD Power supply for digital circuits 46 UNDF Underflow output 47 OVF Overflow output 48 N.C. No connection Absolute Maximum Ratings Ta=25˚C Parameter Power supply voltage Symbol VDD Rating – 0.3 to +7.0 Unit V VI – 0.3 to VDD +0.3 V Output voltage VO – 0.3 to VDD +0.3 V Operating ambient temperature Topr –20 to +70 ˚C Storage temperature Tstg –55 to +125 ˚C Input voltage Recommended Operating Conditions Parameter Power supply voltage VDD=AVDD=DVDD=3.0V, VSS=AVSS=DVSS=0V, Ta=25˚C Symbol VDD min 2.85 typ 3.00 Unit V Digital input "H" level VIH 2.4 VDD V voltage "L" level VIL VSS 0.8 V Reference "H" level VRT 2.0 VDD V voltage "L" level VRB VSS 1.0 V Clock "H" level pulse width tWH 30 ns "L" level pulse width tWL 30 ns VAIN VSS Analog input voltage Electrical Characteristics Parameter Power consumption VDD Resolution V VDD=AVDD=DVDD=3.0V, AVSS=DVSS=0V, Ta=25˚C Symbol Conditions PC FC=15MSPS min (not including reference current) RES typ max Unit 39 72 mW 10 bit Linearity error EL fCLK=15MSPS ±1.3 ±2.5 LSB Differential linearity error ED VRT=3.0V ±0.5 ±1.0 LSB VBB=1.0V Maximum conversion rate Clock frequency 4 max 3.30 FC(max.) 15 fCLK 1 15 2 VRT – VRB V –1.5 mA Analog input dynamic range DR Output "H" level IOH VOH=VDD – 0.8V current "L" level MSPS MHz IOL VOL=0.4V 1.5 Output delay time td CL=20pF 10 mA Analog input capacitance CI 18 pF Sampling delay tsd 7 ns 20 40 ns A/D, D/C Converters for Image Signal Processing MN6577F, MN6577H Timing Chart The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital output 2.5 clock cycles later at the rising edge of the clock signal. tWH tWL Clock Analog input N N+1 tsd(7ns) Data output N–3 N–2 N+2 N+3 N–1 N N+4 N+1 td(20ns) Note: The circles indicate analog signal sampling points. 5 MN6577F, MN6577H A/D, D/C Converters for Image Signal Processing Package Dimensions (Unit:mm) MN6577F TQFP048-P-0707 9.00±0.20 7.00±0.10 36 25 24 0.10 6 SEATING PLANE (1.00) 0 to 10° +0.10 12 +0.10 0.20 -0.05 0.125 -0.05 0.50 1.20max. 1 (0.75) (1.00) 13 0.10±0.10 48 9.00±0.20 7.00±0.10 (0.75) 37 0.50±0.10 A/D, D/C Converters for Image Signal Processing MN6577F, MN6577H Package Dimensions (Unit:mm)(continued) MN6577H QFH048-P-0707 9.0±0.2 7.0±0.2 36 25 24 9.0±0.2 7.0±0.2 (0.75) 37 13 48 1 0.5 (0.75) 12 0.2±0.1 0.1 SEATING PLANE 0.1±0.1 0.15 +0.10 -0.05 2.9 max. 2.5±0.2 (1.0) 0.5±0.2 0 to 10° 7