Board User's Manual "CPU Board XMC4500 SDRAM"

He xa gon Applic atio n Ki t
For XMC4000 Family
CP U_ 45 B - V1
CPU Board XMC4500 SDRAM
Boa rd Us er‘s Ma nu al
Revision 1.0, 2013-02-20
Mic rocon t rolle r
Edition 2013-02-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all
warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual
property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life
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sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
CPU_45B-V1
CPU Board XMC4500 SDRAM
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 1.0
2013-02-20
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™,
EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™,
PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™,
SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc.
MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE
OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd.
Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company
Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments
Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2011-02-24
Template: IFX_Template_2011-02-24.dot
CPU_45B-V1
CPU Board XMC4500 SDRAM
Table of Contents
Table of Contents
Introduction ............................................................................................................................................................ 7
1
1.1
1.2
Overview ............................................................................................................................................. 7
Key Features ........................................................................................................................................ 7
Block Diagram ...................................................................................................................................... 8
2
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.12.1
2.12.2
2.12.3
Hardware Description ........................................................................................................................ 9
Power Supply ....................................................................................................................................... 9
Reset .................................................................................................................................................. 12
Clock Generation................................................................................................................................ 13
Boot Option ........................................................................................................................................ 13
Debug Interface .................................................................................................................................. 14
On-board USB Debugger ................................................................................................................... 15
Cortex Debug Connector (10-pin) ...................................................................................................... 16
Cortex Debug+ETM Connector (20-pin) ............................................................................................ 17
Serial Flash Memory .......................................................................................................................... 19
SDRAM .............................................................................................................................................. 20
USB .................................................................................................................................................... 20
RTC .................................................................................................................................................... 22
User LEDs and User Button ............................................................................................................... 23
Potentiometer ..................................................................................................................................... 23
Satellite Connectors ........................................................................................................................... 24
COM Connector ................................................................................................................................. 25
HMI Connector ................................................................................................................................... 26
ACT Satellite Connector ..................................................................................................................... 27
3
3.1
3.2
3.3
Production Data................................................................................................................................ 27
Schematics ......................................................................................................................................... 27
Component Placement and Geometry ............................................................................................... 32
Bill of Material (BOM) ......................................................................................................................... 33
Board User's Manual
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CPU_45B-V1
CPU Board XMC4500 SDRAM
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
CPU_45B-V1 Board Block Diagram..................................................................................................... 8
CPU Board XMC4500 SDRAM (CPU_45B-V1) ................................................................................... 9
Powering option.................................................................................................................................. 10
Block Diagram Of Power Supply ........................................................................................................ 10
Reset Circuit ....................................................................................................................................... 12
Reset LED and Reset Button ............................................................................................................. 12
Clock Generation Circuit .................................................................................................................... 13
Boot Options Switch ........................................................................................................................... 13
Installation of Serial Port Driver .......................................................................................................... 15
On-Board USB Debugger .................................................................................................................. 15
Cortex Debug Connector (10-pin) ...................................................................................................... 16
Cortex Debug Connector (10-pin) Layout .......................................................................................... 17
Cortex Debug+ETM Connector (20-pin) ............................................................................................ 17
Cortex Debug+ETM Connector (20-pin) Layout ................................................................................ 18
Quad SPI Flash Interface ................................................................................................................... 19
SDRAM Interface ............................................................................................................................... 20
USB Connector .................................................................................................................................. 20
USB power generation - Host/OTG mode ......................................................................................... 21
Battery Holder for Coin Cells .............................................................................................................. 22
XMC4500 Power Domains and Real Time Clock .............................................................................. 22
User LEDs and User Buttons ............................................................................................................. 23
Satellite Connectors ........................................................................................................................... 24
Satellite Connector Type COM .......................................................................................................... 25
Satellite Connector Type HMI ............................................................................................................ 26
Satellite Connector Type ACT ............................................................................................................ 27
Satellite Connectors, USB-OTG......................................................................................................... 28
XMC4500 ........................................................................................................................................... 29
Power, Debug Connector, Reset, SDRAM ........................................................................................ 30
On-board Debugger ........................................................................................................................... 31
Component Placement and Geometry ............................................................................................... 32
Board User's Manual
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Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
List of Figures
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Power status LEDs ............................................................................................................................. 10
Power Measurement .......................................................................................................................... 11
Boot Options Settings ........................................................................................................................ 13
Cortex Debug Connector (10 Pin) ...................................................................................................... 16
Cortex Debug+ETM Connector (20 Pin) ............................................................................................ 18
Quad SPI Signals ............................................................................................................................... 19
USB micro AB connector Pinout ........................................................................................................ 21
User LEDs .......................................................................................................................................... 23
User Buttons ....................................................................................................................................... 23
Potentiometer ..................................................................................................................................... 23
BOM of CPU_45B-V1 Board .............................................................................................................. 33
Board User's Manual
6
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Overview
Introduction
This document describes the features and hardware details of the CPU board “CPU Board XMC4500 SDRAM”
(CPU_45B-V1) designed to work with Infineon’s XMC4500 Microcontroller. This board is part of Infineon’s
Hexagon Application Kits. Please visit www.infineon.com/xmc-dev for more information about the Hexagon
Application Kit family.
1
Overview
The CPU board CPU_45B-V1 houses the XMC4500 Microcontroller and three satellite connectors (HMI, COM,
ACT) for application expansion. The board along with satellite cards (e.g. HMI_OLED-V1, COM_ETH-V1,
AUT_ISO-V1 boards) demonstrates the capabilities of XMC4500.
The main use case of this board is to demonstrate the external bus unit (EBU) of the XMC4500 device including
the tool chain. For this purpose a 64 Mbit SDRAM is connected to the XMC4500 and for external bus extension
an asynchronous 16-bit wide bus interface is available at the COM satellite connector.
Attention: This board (CPU_45B) has not been designed to work with the “General Purpose Motor Drive
Card” (MOT_GPDLV). For this purpose please use the CPU boards CPU_45A, CPU_44A or
CPU_42A.
The focus is safe operation under evaluation conditions. The board is neither cost nor size optimized and does
not serve as a reference design.
1.1
Key Features
The CPU_45B-V1 board is equipped with the following features













®
XMC4500 (ARM Cortex™-M4-based) Microcontroller, 1 MByte Flash, 160 kByte SRAM, LFBGA-144
8 MByte On-board SDRAM, 1 Mbit x 16 bits x 4 banks
Connection to satellite cards via satellite connectors COM, HMI and ACT
USB OTG Host/Device support via micro USB connector
Debug options
− On-board Debugger via the Debug USB connector
− Cortex Debug connector 10-pin (0.05”)
− Cortex Debug+ETM connector 20-pin (0.05”)
Reset push button
32 MBit quad SPI flash memory
Boot option switch
PowerScale Connector: Ready for power consumption analysis
Two User Buttons connected to P5.10 and P0.10
7 LED’s
3 Power indicating LED’s
2 User LEDs (P5.2 and P1.1)
1 RESET LED
1 Debug LED
Potentiometer, connected to analog input P14.1
Power supply
− Via Debug USB connector
− Via Micro-USB connector in USB device mode
− Via satellite connector pins (COM/ACT satellites cards can supply power to CPU board)
− RTC backup battery
Board User's Manual
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Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Overview
1.2
Block Diagram
Figure 1 shows the functional block diagram of the CPU_45B-V1 board. For more information about the power
supply please refer to chapter 2.1.
The CPU board has got the following building blocks:
- 3 Satellite Connectors (COM, HMI ACT)
- 2 User LEDs connected to GPIOs P5.2 and P1.1
- 2 User Buttons connected to GPIOs P5.10 and P0.10.
- Quad SPI flash memory (32 Mbit)
- Synchronous Dynamic RAM (SDRAM, 64Mbit)
- 2 Cortex Debug Connectors
- Variable resistor (POTI) connected to GPIO P14.1
- USB On-The-Go Connector (Micro-USB)
- On-board Debugger via USB connector (Micro-USB)
On-board
Debugger
XMC4200
SWV
SWD
RS485
Debug+ETM
20pin
SWV
SWD
UART
CAN
Debug
10pin
CAN1
JTAG
USB
GPIO
ETH
RMII
ETH
CAN
CAN1
XMC4500
LFBGA144
EE
U1C1
2xCS
QSPI
U2C0
2xCS
U2C1
EE
CCU
4/8
CAPCOM
POSIF
ENCODER
DSD
DSMOD
DAC
OPAMP
ADC
SENSOR
ACT
EBU
COM
EBU
QSPI
CPU Board XMC4500
SDRAM
2xButton
CPU_45B-V1
U0C0
EXTBUS
CAN
USB
OTG
2xLED
BSL
CAN
Debug
USB
POTI
SDRAM
SPI
SPI
2xISOFACE
GPIO
GPIO
GPIO
GPIO
I2C
I2S
SPI
GPIO
I2C_IOEX
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I2C
I2C
I2C_IOEX
HMI
I2C_IOEX
reset
OLED
HEADSET
cmd
SDCARD
TOUCH
Block_Diag.emf
Figure 1
CPU_45B-V1 Board Block Diagram
Board User's Manual
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Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2
Hardware Description
The following sections give a detailed description of the hardware and how it can be used.
Debug USB
Connector
USB OTG
Connector
ACT
Satellite
Connector
User LEDs
and User
Buttons
On-board
Debugger
COM
Satellite
ConnEctor
qSPI
Flash
SDRAM
Boot
Option
Switch
Power
indicating
LEDs
Debug
Connectors
Reset
Circuit
Debug
Connectors
Battery
Holder
Potentiometer
HMI Satellite
Connector
Figure 2
2.1
Board_Interfaces.emf
CPU Board XMC4500 SDRAM (CPU_45B-V1)
Power Supply
The CPU_45B-V1 board can be powered via either of the USB plugs (5 V); however, there is a current limit that
can be drawn from the host PC through USB. If the CPU_45B-V1 board is used to drive other satellite cards
(e.g. AUT_ISO-V1 or MOT_GPDLV-V2) and the total current required exceeds 500 mA, then the board needs to
be powered by a satellite card, which supports external power supply like e.g. AUT_ISO-V1, MOT_GPDLV-V2,
COM_ETH-V1.
The typical current drawn by the CPU board without any satellite cards connected is about 220 mA (@5V).
For powering the board through an USB interface, connect the USB cable provided with the kit to either of the
Micro-USB connector on board as shown in Figure 3.
Board User's Manual
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Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
USB OTG
Debug USB
IFX1763
3.3V Linear
Voltage
Regulator
PowerScale
Probe
Power
indicating
LEDs
Power.emf
Figure 3
Powering option
To indicate the power status of CPU_45B-V1 board three power indicating LED’s are provided on board (see
Figure 3). The LED will be “ON” when the corresponding power rail is powered.
Table 1
Power status LEDs
LED Reference
Power Rail
Voltage
Note
V401
VDD5
5V
Must always be “ON”
V402
VDD5USB
5V
V403
VDD3.3
3.3 V
“ON” if powered by USB OTG connector X203
“OFF” in all other supply cases
Must always be “ON”
USB
OTG
Power
LED
Debug
USB
Power
LED
VDD5USB +5V
Power
LED
VDD5 +5V
CPU Board XMC4500 SDRAM
CPU_45B-V1
VDD3.3 +3.3V
VDD3.3
U401
U200
VDD5USB
U300
Lin. Voltage
Regulator
IFX1763
JP300
VDD3.3
VDDP
HIB_IO_1
EN
P0.1
VDD5
On Board Devices
VDD5
XMC4400
LFBGA144
VBAT
BATTERY
HMI Sat.
Connector
Figure 4
COM Sat.
Connector
ACT Sat.
Connector
Power_Block.emf
Block Diagram Of Power Supply
Board User's Manual
10
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Hitex PowerScale probe is provided on the CPU_45B-V1 board to measure the power consumption of the
XMC4500 device.
Table 2
Power Measurement
Jumper
Function
Description
JP300
PowerScale
A Hitex PowerScale probe can be connected for current sensing the
VDD3.3 (CPU power source). Default: pos. 1-2 (closed)
Note: On the PCB there is a shorting trace between pin 1-2. This trace has
to be cut first, before using PowerScale. Pin 3 is GND.
Board User's Manual
11
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CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.2
Reset
A reset signal connected to the low-active PORST# pin of the target CPU (U300) can be issued by
 an on-board Reset Button (SW400, RESET)
 an on-board debug device (U500)
 an external debugger connected to either Cortex Debug connector X400 or X401
The RESET signal is routed to all satellite connectors. The reset circuit includes a red LED (V407) to indicate
the reset status: The Reset LED (V407) will be “ON” during active reset state and will be “OFF” if reset is not
active.
Be aware that PORST# is a bidirectional reset pin of the XMC4000 family which can also be pulled low by the
XMC4000 device itself.
Figure 5
Reset Circuit
Reset
LED
Reset
Button
RST.emf
Figure 6
Reset LED and Reset Button
Board User's Manual
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CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.3
Clock Generation
An external 12 MHz crystal provides the clock signal to the XMC4500 microcontroller. The drive strength of the
oscillator is set to maximum by software, in order to ensure a safe start-up of the oscillator even under worst
case conditions. A serial 510 Ohm resistor will attenuate the oscillations during operations.
For the RTC clock a separate external 32.768 kHz crystal is used on board.
Figure 7
Clock Generation Circuit
2.4
Boot Option
During power-on-reset the XMC4500 latches the dip switch SW300 settings via the TCK and the TMS pin.
Based on the values latched different boot options are possible.
Table 3
Boot Options Settings
BSL (TMS)
CAN/UART (TCK)
Boot Option
OFF (1)
UART (0)
Normal Mode (Boot from flash)
ON (0)
UART (0)
ASC BSL Enabled (Boot from UART)
OFF (1)
CAN (1)
BMI Customized Boot Enabled
ON (0)
CAN (1)
CAN BSL Enabled (Boot from CAN)
Boot
Option
Switch
Boot_Switch.emf
Figure 8
Boot Options Switch
Board User's Manual
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CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.5
Debug Interface
The CPU_45B-V1 board supports debugging via 3 different channels:

On-board Debugger

Cortex Debug Connector (10-pin)
 Cortex Debug+ETM Connector (20-pin)
The Hexagon Application Boards are designed to use “Serial Wire Debug” as debug interface. JTAG debug is
not supported by default because the GPIO P0.7, where the required TDI function is mapped to also, is used by
the on-board SDRAM device and various Actuator boards connected to the ACT satellite connector.
Attention: It is strongly recommended not to use JTAG debug mode, especially if satellites boards are
connected, which uses the GPIO 0.7. For the same reason also do not use the on-board
debugger in JTAG mode.
If you want to use the JTAG debug mode through the cortex debug connectors (X400, X401) anyway, enable
the JTAG interface of the XMC device by assembling the pull-up resistor R427 (4k7 Ohm) and the resistor R410
(0 - 33 Ohm).
Board User's Manual
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Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.5.1
On-board USB Debugger
The on-board debugger [1] supports
 Serial Wire Debug

Serial Wire Viewer [2]

Full Duplex UART communication via a USB Virtual COM
[1]
Newer firmware versions of the on-board debugger require the latest J-Link driver (V4.62 or higher) and a
Serial Port Driver (CDC driver) installed on your computer. Please check “Install J-Link Serial Port Driver”
when installing the latest J-Link driver (see Figure 9)
[2]
Serial Wire Viewer operation does not work during use of the on-board SDRAM.
Figure 9
Installation of Serial Port Driver
The on-board debugger can be accessed through the Debug USB connector shown in Figure 10. The Debug
LED V502 shows the status during debugging.
Debug USB
Debug LED
On-board
Debugger
Debug.emf
Figure 10
On-Board USB Debugger
When using an external debugger connected to the 10pin/20pin Cortex Debug Connector, the on-board
debugger is switched off.
When using the USB virtual COM port function of the on-board debugger (connected to P1.4 and P1.5 of the
XMC4500) the UART interface to the COM satellite is disabled through the switches U301 and U306.
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Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.5.2
Cortex Debug Connector (10-pin)
The CPU_45B-V1 board supports Serial Wire Debug operation through the 10-pin Cortex Debug Connector.
By default the board does not support Serial Wire Viewer operation through the 10-pin Cortex Debug
Connector, because the required SWO pin mapped to P2.1 is used for the connection to the on-board SDRAM.
If Serial Wire Viewer operation is required anyway the resistor R404 needs to be assembled.
JTAG operation additionally would require the TDI (P0.7) signal. By default the TDI signal is disconnected from
the Cortex Debug Connectors by a not assembled resistor R410, because the pin P0.7 can be used by the onboard SDRAM, by Actuator boards connected to the ACT satellite connector and by boards connected to the
COM satellite connector.
Cortex Debug
Connector (10-pin)
VCC
1
2
SWDIO / TMS
GND
3
4
SWDCLK / TCK
GND
5
6
SWO / TDO
KEY
7
8
NC / TDI
GNDDetect
9
10 nRESET
cortex-10pin.emf
Figure 11
Cortex Debug Connector (10-pin)
Table 4
Cortex Debug Connector (10 Pin)
Pin No.
Signal Name
Serial Wire Debug
JTAG Debug
1
VCC
+3.3 V
+3.3 V
2
SWDIO / TMS
Serial Wire Data I/O
Test Mode Select
3
GND
Ground
Ground
4
SWDCLK / TCK
Serial Wire Clock
Test Clock
5
GND
Ground
Ground
6
SWO / TDO
Trace Data OUT
Test Data OUT
7
KEY
KEY
KEY
8
NC / TDI
Not connected
Test Data IN
9
GNDDetect
Ground Detect
Ground Detect
10
nRESET
Reset (Active Low)
Reset (Active Low)
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Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Cortex Debug
Connector (10 Pin)
10Pin_Conn.emf
Figure 12
2.5.3
Cortex Debug Connector (10-pin) Layout
Cortex Debug+ETM Connector (20-pin)
The CPU_45B-V1 board supports Serial Wire Debug operation and Instruction Trace operation through the 20pin Cortex Debug+ETM Connector.
The board does not support Serial Wire Viewer operation through the Cortex Debug Connectors by default,
because the required SWO pin mapped to P2.1 is used for the connection to the on-board SDRAM. If Serial
Wire Viewer operation is required anyway the resistor R404 needs to be assembled.
JTAG operation additionally would require the TDI (P0.7) signal. By default the TDI signal is disconnected from
the Cortex Debug Connectors by a not assembled resistor R410, because the pin P0.7 can be used by the onboard SDRAM, by Actuator boards connected to the ACT satellite connector and by boards connected to the
COM satellite connector.
Cortex Debug+ETM
Connector (20-pin)
VCC 1
2
SWDIO / TMS
GND 3
4
SWDCLK / TCK
GND 5
6
SWO / TDO / EXTa / TRACECTL (NC)
KEY 7
8
NC/EXTb/TDI (NC)
GNDDetect 9
10
nRESET
GND/TgtPwr+Cap 11
12
TRACECLK
GND/TgtPwr+Cap 13
14
TRACEDATA[0]
GND 15
16
TRACEDATA[1]
GND 17
18
TRACEDATA[2]
GND 19
20 TRACEDATA[3]
cortex-20pin.emf
Figure 13
Cortex Debug+ETM Connector (20-pin)
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Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Table 5
Cortex Debug+ETM Connector (20 Pin)
Pin No.
Signal Name
Serial Wire Debug
JTAG Debug
1
VCC
+3.3 V
+3.3 V
2
SWDIO / TMS
Serial Wire Data I/O
Test Mode Select
3
GND
Ground
Ground
4
SWDCLK / TCK
Serial Wire Clock
Test Clock
5
GND
Ground
Ground
6
SWO / TDO
Trace Data OUT
Test Data OUT
7
KEY
KEY
KEY
8
NC / TDI
Not connected
Test Data IN
9
GNDDetect
Ground Detect
Ground Detect
10
nRESET
Reset (Active Low)
Reset (Active Low)
11
GND/TgtPwr+Cap
Ground
Ground
12
TRACECLK
Trace Clock
Trace Clock
13
GND/TgtPwr+Cap
Ground
Ground
14
TRACEDATA[0]
Trace Data 0
Trace Data 0
15
GND
Ground
Ground
16
TRACEDATA[1]
Trace Data 1
Trace Data 1
17
GND
Ground
Ground
18
TRACEDATA[2]
Trace Data 2
Trace Data 2
19
GND
Ground
Ground
20
TRACEDATA[3]
Trace Data 3
Trace Data 3
Cortex Debug+ETM
Connector (20 Pin)
20 Pin_Conn.emf
Figure 14
Cortex Debug+ETM Connector (20-pin) Layout
Board User's Manual
18
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.6
Serial Flash Memory
The CPU_45B-V1 board has 32Mbit serial flash memory interfaced to XMC4500 through a SPI interface. The
SPI interface can be configured as single, dual or quad SPI.
Table 6
Quad SPI Signals
Pin No.
Signal Name
Signal Description
P0.13
CLK
Clock
P3.3
CS#
Active Low Chip Select
P3.15
DI
Data Input of Flash (MTSR)
P3.14
DO
Data Output of Flash (MRST)
P0.14
Data I/O
Data Input/Output
P0.15
Data I/O
Data Input/Output
Figure 15
Quad SPI Flash Interface
Board User's Manual
19
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.7
SDRAM
The CPU_45B-V1 board has a 64 Mbit SDRAM interfaced to the XMC4500. The SDRAM interface is shown in
Figure 16.
Figure 16
2.8
SDRAM Interface
USB
The XMC4500 supports USB interface in host only mode, device only mode or as an OTG Dual Role Device
(DRD). In USB device mode, power is expected through VBUS (pin 1 of X203) from an external host (e.g. PC).
When the current consumption of the application running on the Hexagon Application system is higher than
500 mA, power from an external source through satellite cards shall be used.
Note: Some PCs, notebooks or hubs have a weak USB supply which is not sufficient for proper supply. In this
case use an external 5 Volt power supply or a powered USB hub.
Figure 17
USB Connector
The USB ID pin of the USB connector is connected to the port pin P15.2 of the XMC4500. This pin must be
polled by software, because this pin does not support USB_ID detection.
An OTG device will detect whether a USB 3.0 Micro-A or Micro-B plug is inserted by checking the ID pin. When
the ID = FALSE, Micro-A connector is plugged and when ID = TRUE a Micro-B connector is plugged in. When
ID is true the XMC4500 acts as USB host else as USB device.
Board User's Manual
20
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Table 7
USB micro AB connector Pinout
Pin No.
Pin Name
Pin Description
1
VBUS
5V
2
D-
Data Minus
3
D+
Data Plus
4
ID
Identification
5
GND
Ground
Figure 18
USB power generation - Host/OTG mode
In the host only mode and OTG mode the CPU_45B-V1 board is capable of supplying power to the connected
device (e.g. USB mouse). The board has a power-switch which is controlled by the USB.BUSDRIVE signal of
XMC4500. USB.BUSDRIVE is mapped to Port P0.1 (active high).
In the Host/OTG mode a low active FAULT signal indicates to XMC4500 via HIB_IO_0 signal, if more than 500
mA current is drawn by the external device. HIB_IO_0 signal is used as general purpose input pin for this
implementation.
Diode V200 will allow powering the board through USB in all USB modes via e.g. a PC.
Board User's Manual
21
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.9
RTC
The XMC4500 CPU has two power domains, the Core Domain and Hibernate Domain.
The Core Domain (VDDP pins) is connected to the VDD3.3 rail. An on-board LDO voltage regulator generates
VDD3.3 (3.3 V) from VDD5 (5 V).
The Hibernate Domain is powered via the auxiliary supply pin VBAT, which is supplied by either a 3 V coin cell
(size 1216, 1220, 1225) plugged into the battery holder or 3.3 V (VDD3.3) generated by the on-board voltage
regulator.
Battery
Holder
Batt.emf
Figure 19
Battery Holder for Coin Cells
The Real Time Clock (RTC) is located in the hibernate domain. The XMC4500 uses the HIB_IO_1 signal (active
low) to shutdown the external LDO voltage regulator which generates VDD3.3 (core domain). Even if the Core
Domain is not powered the Hibernate Domain will operate if VBAT is available. The RTC keeps running as long
as the Hibernate Domain is powered via the auxiliary supply VBAT. The RTC is capable to wake-up the whole
system from Hibernate mode by setting HIB_IO_1 to high.
XMC4500
VDD3.3
CPU
VDDP
Core Domain
EN
Hibernate Domain
HIBIO_1
Hibernate
Control
SPI
IFX1763
LDO
Voltage Reg.
12 MHz
RTC
VBAT
32.768 kHz
Internal OSC
Battery
External OSC
+
RTC.emf
Figure 20
XMC4500 Power Domains and Real Time Clock
Board User's Manual
22
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.10
User LEDs and User Button
The port pins P5.2 and P1.1 of XMC4500 on the CPU_45B-V1 board are connected to the LEDs V300 and
V301 respectively. More User LED’s are available through the I2C GPIO expander on most of the satellite
cards.
Table 8
User LEDs
LED
Connected to Port Pin
LED1 / V300
GPIO P5.2
LED2 / V301
GPIO P1.1
Two User Buttons, SW401 and SW402 are connected to P5.10 and P0.10 of XMC4500
Table 9
User Buttons
Button
Connected to Port Pin
Button1 / SW401
GPIO P5.10
Button2 / SW402
GPIO P0.10
User
LED2
User
LED1
2 User
Buttons
Button_LED.emf
Figure 21
2.11
User LEDs and User Buttons
Potentiometer
The CPU_45B-V1 board provides a potentiometer for ease of use and testing of the on-chip analog to digital
converter. The potentiometer is connected to the analog input G0_CH1 (P14.1). The analog output of the
potentiometer ranges from 0 V to 3.3 V.
Table 10
Potentiometer
Potentiometer
Connected to Port Pin
R300
P14.1/ G0_CH1 (Group 0, channel 1)
Board User's Manual
23
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
2.12
Satellite Connectors
The CPU_45B-V1 board provides three satellite connectors for application expansion by satellite cards:

COM satellite connector (Communication)

HMI satellite connector (Human Machine Interface)
 ACT satellite connector (Actuator)
Note: Satellite cards shall be connected to their matching connectors only. (For e.g. COM satellite cards shall be
connected to COM satellite connector only)
COM Satellite
Connector
ACT Satellite
Connector
HMI Satellite
Connector
Satt_Conn.emf
Figure 22
Satellite Connectors
Board User's Manual
24
Revision 1.0, 2013-02-20
Figure 23
Board User's Manual
25
EBU_RD/EBU_nWR
EBU_RD
EBU_nBC1
EBU_nBC0
nc
EBU_nCS1
P3.1
P3.0
P2.15
P2.14
nc
P0.9
GND
EBU.nADV
P0.6
VSS
P0.0
P0.0
EBU_A16
P14.13
P14.13
P6.0
U2C1_DOUT0/DX0D
P3.11/P3.12
EBU_A17
nc
nc
P6.1
nc
nc
EBU_A18
nc
nc
P6.2
U0C0_DOUT0
P1.5 **
EBU_A19
U0C0_DX0B
P1.4 **
P6.4
nc
nc
nc
nc
nc
nc
ETH0_TX_EN
P5.9
nc
ETH0_MDC
P1.10
nc
ETH0_MDO
GND
EBU_A
EBU_A
EBU_A
EBU_A
EBU_A
EBU_A
EBU_A
EBU_A
GND
EBU_CS
EBU_CS
EBU_BC
EBU_BC
EBU_RD
EBU_WR
EBU_ADV
VDD5
VDD5
COM_GPIO0
COM_GPIO1
SPI_CSC1
SPI_CSC0
ASC_TXD
ASC_RXD
ASC_DIR
RSVD
ETH_RMII
ETH_RMII
ETH_RMII
46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
COM
nc
nc
P3.13
P6.3
nc
CAN_N1_TXD
CAN_N1_RXDA
nc
nc
nc
U2C1_SCLKOUT
P6.3
RESET#
RSVD
CAN_TXD
CAN_RXD
SPI_MTSR
SPI_MRST
SPI_SCLK
I2C_SCL
GPIO
RESET
VDD5
GND
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
EBU_AD
GND
EBU_AD15
EBU_AD14
EBU_AD13
EBU_AD12
EBU_AD11
EBU_AD10
EBU_AD9
EBU_AD8
EBU_AD7
EBU_AD6
EBU_AD5
EBU_AD4
EBU_AD3
EBU_AD2
EBU_AD1
EBU_AD0
P2.6
GND
GND
VDD5
P2.7
ETH0_CLK_RMIIC
ETH_RMII
VSS
P1.3
P1.2
P1.9
P1.8
P1.7
P1.6
P4.1
P4.0
P0.8
P0.7
P3.6
P3.5
P0.5
P0.4
P0.3
P0.2
PORST
nc
nc
nc
VSS
P15.8
P0.11
P15.9
ETH0_RXERB
ETH_RMII
P2.12
P2.13
ETH0_TXD0
ETH0_TXD1
ETH_RMII
P0.14
ETH0_CRS_DVC
nc
RSVD
P0.15
ETH_RMII
U1C1_DOUT3
qSPI_D3
P3.14
P3.15
VSS
XMC Pin
ETH_RMII
U1C1_DOUT2
qSPI_D2
COM
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
nc
ETH0_RXD0D
P5.0
P1.11
U1C1_DOUT1
qSPI_D1
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
nc
I2C_SDA
ETH0_RXD1D
P5.1
7
RSVD
GND
U1C1_DOUT0
GND
qSPI_D0
6
nc
SPI_CSC2
nc
nc
5
RSVD
3
nc
ETH_RMII
nc
nc
1
GND
ETH_RMII
U1C1_SELO1
XMC Function
Function
4
COM
2
VSS
qSPI_CS
U1C1_SELO0
P0.12
P3.3 *
qSPI_CS
GND
qSPI_SCLK
GND
U1C1_SCLKOUT
VSS
CPU_45B-V1
(SDRAM)
P0.13
Satellite
Connector
Pin
CPU_45B-V1
(SDRAM)
Function
2.12.1
XMC Function
XMC Pin
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
COM Connector
The COM satellite connector on the CPU_45B-V1 board allows interface expansion through COM satellite cards
(e.g. COM_ETH-V1)
Satellite Connector Type COM
Attention: * This pin is used as chip select signal for the on-board EEPROM and therefore disconnected
by solder jumper SJ1
Attention: ** This pin is connected with the satellite connector via an analog switch
Revision 1.0, 2013-02-20
Figure 24
Board User's Manual
26
nc
nc
nc
nc
nc
nc
nc
GND
nc
nc
nc
nc
nc
nc
nc
VSS
nc
nc
nc
VADC_G3CH4
P15.12
nc
VADC_G3CH5
P15.13
nc
VADC_G1CH4
P14.12
nc
nc
nc
GND
COLA
COL0
COL1
COL2
COL3
TPx0
TPx1
RSVD
RSVD
RSVD
ADC19
ADC17
ADC15
ADC3/ORC0
DAC0/ADC1
nc
nc
nc
nc
nc
nc
nc
P5.11
U1C1.DOUT0
U1C1.DX0B
U1C1.SCLKOUT
U2C0.DOUT0
U2C0.DX0C
U2C0.SCLKOUT
U2C1.SCLKOUT
P6.3
RESET#
MMC_DATA4
MMC_DATA6
MMC_CMD
MMC_LED
MMC_SDWC
RSVD
RSVD
OLED_CMD
I2S_MTSR
I2S_MRST
I2S_SCLK
SPI_MTSR
SPI_MRST
SPI_SCLK
I2C_SCL
GPIO
RESET
46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
HMI
GND
TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
RSVD
RSVD
ADC18
ADC16
ADC14
ADC2/DACREF
DAC1/ADC0
AREF
VDD5
GND
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
VADC_G2CH3
VADC_G0CH3
VADC_G0CH4
VADC_G1CH0
VAREF
nc
MMC_DATA2
HMI
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
AGND
P6.3
nc
MMC_DATA0
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
VDD5
P3.13
nc
6
VSS
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
P15.3
P14.3
P14.4
P14.8
VAREF
POSRT
P3.9
P3.7
P3.8
P0.13
P3.14
P3.15
P5.11
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
VSS
GND
GND
MMC_nRST
4
VDD5
VDD5
HMI_GPIO0
DAC.OUT1
SPI_CSH1
SPI_CSH0
P14.9
U2C0.SELO0
P3.10
I2S_SYNCLK
AGND
nc
nc
I2S_WA
I2S_MCLK
VAGND
nc
nc
HMI_GPIO1
U1C1.SELO2
P3.4
AudioRST
P5.7
P4.2
P4.2
RSVD
P15.5 Input
nc
nc
RSVD
P5.7
nc
nc
RSVD
P15.5
nc
nc
MMC_nSDCD
I2C_SDA
nc
nc
MMC_BUSPOW
U2C1_DOUT0/DX0D
nc
nc
MMC_DATA7
P3.11/P3.12
nc
nc
MMC_DATA5
SPI_CSH2
nc
nc
MMC_DATA3
7
nc
nc
nc
MMC_DATA1
5
nc
nc
nc
GND
MMC_CLK
3
U2C0.SELO3
nc
XMC Pin
XMC Function
Function
2
HMI
1
P5.6
GND
nc
CPU_45B-V1
(SDRAM)
Pin
Satellite
Connector
VSS
Function
CPU_45B-V1
(SDRAM)
XMC Function
2.12.2
XMC Pin
CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
HMI Connector
The HMI satellite connector on the CPU_45B-V1 board allows interface expansion through HMI satellite cards.
Satellite Connector Type HMI
Revision 1.0, 2013-02-20
Figure 25
Board User's Manual
(1)
P0.7 can also be used for JTAG Debugging (TDI)
(2)
P0.8 is used as TRST in order to enable JTAG Debug
(3)
This pin is connected with the satellite connector via an analog switch
(4)
This ADC input does not support “Out of Range Detection”
(5)
This pin is disconnected by a solder jumper
(6)
Support High Resolution PWM
3
Production Data
3.1
Schematics
27
AGND
VADC_G1CH1
nc
nc
VADC_G0CH0
nc
VADC_G3CH6
VAGND
P14.9
nc
nc
P14.0
nc
P15.14
GND
P4.7
P4.7
CCU43OUT1
P15.4 Input
P15.4
VSS
U2C1_DOUT0/DX0D
P3.11/P3.12
P4.5
nc
nc
CCU43OUT0
U2C0.SELO0
P3.10 (5)
P4.6
U2C0.SELO3
P5.6 (5)
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
DSD_MCLK3
P6.6 (3)
GND
PWMX3
PWMX2
PWMB2_L
PWMB2_H
PWMB1_L
PWMB1_H
PWMB0_L
PWMB0_H
ADC13
ADC11
ADC9
ADC7
ADC5/ORC2
ADC3/ORC0
DAC0/ADC1
AGND
VDD5
VDD5
ACT_GPIO0
SPI_CSA1
SPI_CSA0
TRAP_X
TRAP_B
TRAP_A
CC_IN5
CC_IN4
CC_IN3
RSVD
DSDCLK1
DSDCLK0
P6.5 (3)
nc
PIF0_IN2B
nc
nc
nc
DSD_DIN3A
nc
nc
nc
nc
nc
nc
nc
U2C0.DOUT0
PIF0IN3
DSDIN0
DSDIN1
DSDIN2
DSDIN3
RSVD
CC_IN0
CC_IN1
CC_IN2
ENA_A
ENA_B
ENA_X
SPI_MTSR
ACT
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
nc
nc
nc
PWMP
7
nc
DSD_PWMP
P1.1
5
PWMN
PIF0_IN1B
PIF0IN2
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
ACT
GPIO
RESET
GND
PWMX1
PWMX0
PWMA2_L
PWMA2_H
PWMA1_L
PWMA1_H
PWMA0_L
PWMA0_H
ADC12
ADC10
ADC8
ADC6/ORC3
ADC4/ORC1
ADC2/DACREF
DAC1/ADC0
AREF
VDD5
GND
CCU43OUT3
CCU43OUT2
nc
nc
nc
nc
nc
nc
VADC_G2CH7
VADC_G2CH6
VADC_G0CH2
VADC_G1CH7
VADC_G1CH6
VADC_G0CH4
VADC_G1CH0
VAREF
P6.3
RESET#
I2C_SCL
VDD5
P6.3
U2C1.SCLKOUT
SPI_SCLK
VSS
P4.3
P4.4
nc
nc
nc
nc
nc
nc
P15.7
P15.6
P14.2
P14.15
P14.14
P14.4
P14.8
VAREF
PORTS
P3.9
P3.13
U2C0.DX0C
U2C0.SCLKOUT
SPI_MRST
P3.7
P3.8
nc
nc
nc
nc
nc
nc
nc
nc
nc
P14.5
P4.16
P14.7
VSS
GND
PIF0_IN0B
GND
PIF0IN1
6
nc
DSD_PWMN
P1.0
PIF1IN2
PIF1IN1
3
nc
ACT_GPIO1
nc
nc
1
VADC_G3CH7
I2C_SDA
nc
nc
PIF1IN0
XMC Pin
XMC Function
Function
4
ACT
2
P15.15
SPI_CSA2
nc
GND
GND
nc
CPU_45B-V1
(SDRAM)
Pin
Satellite
Connector
VSS
Function
CPU_45B-V1
(SDRAM)
XMC Function
2.12.3
XMC Pin
CPU_45B-V1
CPU Board XMC4500 SDRAM
Production Data
ACT Satellite Connector
The ACT satellite connector on the CPU_45B-V1 board allows interface expansion through ACT satellite cards.
Satellite Connector Type ACT
This chapter contains the schematics for the CPU board:
 Satellite Connectors, USB-OTG
 XMC4500
 Power, Debug Connector, Reset
 On-board Debugger
The board has been designed with Eagle. The full PCB design data of this board can also be downloaded from
www.infineon.com/xmc-dev.
Revision 1.0, 2013-02-20
E
R200
L201
BLM18PG600
1
GND GND GND
100nF/0402
C200
1
2
3
4
5
1M/0402
X203C
USB-OTG Connector
ZX62-AB-5PA
X203S
VDD5
GND
VDD5USB
VDD5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
2
V201
ESD8V0L2B-03L
OTG_FS_DM
OTG_FS_DP
P15.2
R202 33R/0402
R203 33R/0402
GND
100nF/0402
C204 VDD5
GND
C202
VDD3.3
R204
D
GND
COM
GND
HSEC8_MATING-CARD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
X200
VDD5
EBU_AD0
EBU_AD1
EBU_AD2
EBU_AD3
EBU_AD4
EBU_AD5
EBU_AD6
EBU_AD7
EBU_AD8
EBU_AD9
EBU_AD10
EBU_AD11
EBU_AD12
EBU_AD13
EBU_AD14
EBU_AD15
P0.2
P0.3
P0.4
P0.5
P3.5
P3.6
P0.7
P0.8
P4.0
P4.1
P1.6
P1.7
P1.8
P1.9
P1.2
P1.3
P3.13
P6.3
RESET#
P2.7
P2.6
P2.13
P2.12
P15.9
P0.11
P15.8
P3.15
P3.14
P0.15
P0.14
USB-OTG Supply
P0.[0..15],P1.[0..15],P2.[0..15],P3.[0..15],P4.[0..7],P5.[0..11],P6.[0..6],P14.[0..15],P15.[2..15]
2
10k/0402
100nF/0402
C
P6.4
P6.2
P6.1
P6.0
P0.9
P0.6
P3.1
P3.0
P2.15
P2.14
P3.12
P14.13
P0.0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
3
GND
P0.1
R205
R206
B
2
SJ1
COM_RXD
COM_TXD
P5.1
P5.0
P1.11
P1.10
P5.9
P0.13
P0.12
P3.3 1
1
D1
GND
100uF/T/10V/C
C213
P4.6
P4.5
P15.14
P15.15
P14.0
P14.9
P3.12
P15.4
P4.7
P5.6
P3.10 1
C
2
A
V200
SJ2
4
5
4
VIN
EN
4
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
1
3
GND
VOUT
FAULT#
U200
TPS2051BDBV
BAS3010A-03W
SJ3
1
2
DSD_MCLK3A
P1.0
P1.1
VDD5
3
+
A
3 D2
VDD3.3
no ass./10k/0402
10k/0402
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
VDD5
HIB_IO_0
GND
GND
4u7F/0805
C212
GND
5
P14.7
P14.6
P14.5
P14.12
P15.13
P15.12
P14.9
P3.12
P15.5
P5.7
P3.10
P5.6 1
P4.2
P3.4
6
2
1
SJ5
2
SJ4
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
5
6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
VDD5
HMI
GND
7
GND
GND
HSEC8_MATING-CARD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
X202
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
P4.4
P4.3
VAREF
P14.8
P14.4
P14.14
P14.15
P14.2
P15.6
P15.7
P3.8
P3.7
P3.9
P3.13
P6.3
RESET#
DSD_DIN3A
Legal Disclaimer
GND
HSEC8_MATING-CARD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
X201
VDD5
C205
VDD5USB
VDD5
AGND
GND
2
ACT
100nF/0402
C208 VDD5
VDD3.3
R207
100nF/0402
VDD5
AGND
2
10k/0402
VDD5
28
C210
Board User's Manual
100nF/0402
C211 VDD5
Figure 26
100nF/0402
1
V1 / 04.04.2012 / Ma
Sheet: 2/5
8
18.10.2012 14:43:12
CPU_45B-V1
Satellite Conn., USB-OTG
VAREF
P14.8
P14.4
P14.3
P15.3
P5.11
P3.15
P3.14
P0.13
P3.8
P3.7
P3.9
P3.13
P6.3
RESET#
8
E
D
C
B
A
CPU_45B-V1
CPU Board XMC4500 SDRAM
Production Data
Satellite Connectors, USB-OTG
Revision 1.0, 2013-02-20
E
D
P0.15
VDD3.3
Jumper closed with a cutable trace on bottom layer
C
VDD3.3
R306
VDD3.3
R310
GND
PS
+ -
CS#
CLK
DI
DO
HOLD#
(IO3)
(IO0)
(IO1)
WP#
(IO2)
U302
VCC
S25FL032P0XMFI01
3
GND
1
GND
GND
GND
GND
100nF/0402
P3.3
P0.13
P3.15
P3.14
1
6
5
2
C321
P0.14
7
8
P3.13
P3.12
P1.1
P5.2
GND
F3
F4
G1
HIB_IO_1
HIB_IO_0
VDDC
GND
2
GND
M11
B12
A2
L12
A11
B1
D1
E1
E2
H2
H3
H4
J1
L5
M5
J2
J3
K2
K1
J4
K3
L2
L3
P14.15
P14.14
P14.13
P14.12
P14.9
P14.8
P14.7
P14.6
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
OTG_FS_DM
OTG_FS_DP
F12
F11
F10
G9
H10
F9
G10
C9
C8
D8
C7
F8
E8
A9
B8
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
G12
E10
E12
E11
D11
D12
B11
A10
B10
B9
D10
C10
C12
C11
E9
D9
P1.15
P1.14
P1.13
P1.12
P1.11
P1.10
P1.9
P1.8
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
3
VDDC3
VDDC2
VDDC1
VDDP3
VDDP2
VDDP1
Analog
Digital
VSSO
VSS1
VSS2
VSS3
/PORST
TCK
TMS
XTAL1
XTAL2
RTC_XTAL_1
RTC_XTAL_2
VAREF
VAGND
VDDA
VSSA
P15.15
P15.14
P15.13
P15.12
P15.9
P15.8
P15.7
P15.6
P15.5
P15.4
P15.3
P15.2
P5.11
P5.10
P5.9
P5.8
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
P2.8
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.15
P3.14
P3.13
P3.12
P3.11
P3.10
P3.9
P3.8
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
4
XMC4500_LFBGA144
Supply
Hibernate/RTC
USB_DUSB
USB_D+
VBUS
HIB_IO_1
HIB_IO_0
VBAT
P14.15
P14.14
P14.13
P14.12
P14.9
P14.8
P14.7
P14.6
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
P1.15
P1.14
P1.13
P1.12
P1.11
P1.10
P1.9
P1.8
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P0.15
P0.14
P0.13
P0.12
P0.11
P0.10
P0.9
P0.8
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
J12
A1
A12
M12
G11
G8
G7
H11
H12
F2
F1
M3
M2
L1
M1
K4
L4
M4
K5
L6
M6
G6
G5
G3
G4
G2
H1
J5
H5
K6
H6
J7
K8
J8
K10
J10
H7
H8
H9
J6
K7
M7
L7
M8
L8
M9
L9
K9
J9
M10
L10
L11
K11
K12
J11
D7
D6
C2
D2
D3
F6
F5
E3
E4
A7
B6
E7
F7
B3
B2
C1
GND
R313
P15.15
P15.14
P15.13
P15.12
P15.9
P15.8
P15.7
P15.6
P15.5
P15.4
P15.3
P15.2
P5.11
P5.10
P5.9
P5.8
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
P2.8
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.15
P3.14
P3.13
P3.12
P3.12
P3.10
P3.9
P3.8
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
I2C_DX
I2C_DOUT
L300
RESET#
TCK
TMS
P0.[0..15],P1.[0..15],P2.[0..15],P3.[0..15],P4.[0..7],P5.[0..11],P6.[0..6],P14.[0..15],P15.[2..15]
Boot Options
C311
C309
GND
100nF/0402
100nF/0402
4
3
USIC_TxD
P1.5
2
A
VCC
GND
A
VCC
GND
A
VCC
GND
A
VCC
GND
74LVC1G66DCK
B
EN
U304
74LVC1G66DCK
B
EN
U303
74LVC1G66DCK
B
EN
U306
74LVC1G66DCK
B
EN
U301
1
5
3
1
5
3
1
5
3
1
5
3
GND
GND
GND
COM_TXD
COM_RXD
GND
8
5
6
100nF/0402
V1 / 04.04.2012 / Ma
DSD_MCLK3A
DSD_DIN3A
GND
Sheet: 3/5
8
18.10.2012 14:43:12
CPU_45B-V1
P6.6
2
P6.5
4
4
DBGPRES#
2
4
2
4
CAN_TxD
CAN_RxD
CAN
Node1
7
Trace Signal / ACT Board Switch
P1.5
P1.4
COMDIS#
USIC_RxD
P1.4
UART
USIC0CH0
COM Board Switch
7
CPU
AGND
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
GND
TMS
TCK
6
100nF/0402
C322
Legal Disclaimer
GND
219-02
Q301
32.768KHZ
1
2
BSL
OFF ON
SW300
GND GND
Q302
510R/0603
12MHZ/S/3.2X2.5
VAREF
5
R304
4
R302
U300
VDD3.3
BLM18PG600
VDD3.3
Hitex
PowerScale
10k/0402
VDDP
1 JP300
2
2k2/0603
LED1
LED-GE/D/0603
V300 R301
4
10uF/10V/0805
2k2/0603
R307
3
P14.1
100nF/0402
C300
qSPI FLASH
10uF/10V/0805
VDD3.3
R300
POTI/10K/VERT
AGND
E
A
R309
C325
C6
E6
C5
D5
E5
B4
D4
A8
B7
A6
A5
B5
A4
A3
C3
C4
100nF/0402
C301
B
10uF/10V/0805
P0.15
P0.14
P0.13
P0.12
P0.11
P0.10
P0.9
P0.8
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
100nF/0402
C302
680R/0603
R305
C323
10k/0402
R303
100nF/0402
C305
V301 680R/0603
LED-GE/D/0603
LED2
C324
10k/0402
VDD3.3
S
VBAT
100nF/0402
C306
A
P0.[0..15],P1.[0..15],P2.[0..15],P3.[0..15],P4.[0..7],P5.[0..11],P6.[0..6],P14.[0..15],P15.[2..15]
100nF/0402
C307
VDD5USB
CPU
C308
1
Potentiometer, GPIO LED, I2C Pullups
10uF/10V/0805
VDDP
BLM18PG600
L301
4k7/0402
C315
15pF/0402
3
AGND
4k7/0402
C312
15pF/0402
ON
CAN
2
AGND
2
UART
C316
15pF/0402
29
C317
15pF/0402
VDD3.3
VDD3.3
C310
C318
Board User's Manual
100nF/0402
C319
Figure 27
100nF/0402
1
E
D
C
B
A
CPU_45B-V1
CPU Board XMC4500 SDRAM
Production Data
XMC4500
Revision 1.0, 2013-02-20
E
D
C
VDD3.3
CS0 pullup
R431
B
COMDIS#
P3.2
SDRAM
1
F2
F3
G9
F8
F7
F9
H7
H8
J8
J7
J3
J2
H3
H2
H1
G3
H9
G2
P3.2
P5.4
P5.5
P3.1
P1.12
P1.13
P1.14
P1.15
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.8
P2.9
R432
22R/0402
P5.8
P5.3
P6.4
GNDGND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQM
LDQM
NC
NC
BA0
BA1
2
IS42S16400F-7BL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
CS#
RAS#
CAS#
WE#
CLK
CKE
U430A
Ext. device pulls signal to GND
and disconnects UART/CAN signals
from COM connector
VDD3.3
GND
A8
B9
B8
C9
C8
D9
D8
E9
E1
D2
D1
C2
C1
B2
B1
A2
F1
E8
E2
G1
G7
G8
C1
C3
C5
C7
C9
X401
S2*10/1.27SO
C2
C4
C6
C8
C10
D2
D4
D6
P0.2
P0.3
P0.4
P0.5
P3.5
P3.6
P0.7
P0.8
P4.0
P4.1
P1.6
P1.7
P1.8
P1.9
P1.2
P1.3
P2.15
P2.14
P2.10
P2.11
XE3K_DM2+CTX
FLE-103-01-G-DV
D1
D3
D5
FTSH-105-01-L-DV-K
GND
100nF/0402
VDD3.3
R408
P1.4
P1.5
3
GND
VDD3.3
A9
E7
J9
A7
B3
C7
D3
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
IS42S16400F-7BL
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
U430P
A1
E3
J1
A3
B7
C3
D7
USIC_TxD
P1.5
4
GND
USIC_RxD
P1.4
UART
USIC0CH0
RESET#
P6.0
P6.6
P6.5
P6.2
P6.1
33R/0402
33R/0402
33R/0402
33R/0402
33R/0402
R421
R423
R424
R425
R426
P5.10
Push Buttons
CAN_TxD
CAN_RxD
CAN
Node1
TRACECLK
TRACED[0]
TRACED[1]
TRACED[2]
TRACED[3]
TDO/SWO
TDI
P0.10
GND
P
P1
GND
S
S1
BYP
EXP
RESET#
GND
GND
GND
Q404
BC858C
GND
GND
V1 / 04.04.2012 / Ma
5
6
Sheet: 4/5
8
18.10.2012 14:43:12
CPU_45B-V1
7
S
S1
10nF/0402
GND
10K/0402
GND GND
Power, Debug, Reset, SDRAM
GND
P
P1
C415
GND
R422
0R/0603
R416
SW400
TMPS2-SMD
GND
4
9
2
1
8
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
GND
OUT
SENSE/ADJ
IFX1763_PADNOP
GND
GND
GND
EN
IN
Power LED and Testpoints
Reset
GND GND
3
6
7
5
8
U401
7
R417
Legal Disclaimer
GND
GND
BUTTON 2
SW402
TMPS2-SMD
X402
BK-885
Battery Holder
100nF/0402
GND
10k/0402
R414
C417
10k/0402
100nF/0402
S
S1
BUTTON 1
SW401
TMPS2-SMD
3
C416
P
P1
GND
100uF/T/10V/C
C414
RTC Battery
HIB_IO_1
R415
R413
TRST
BAV70
VDD5
270k/0402
no ass./10k/0402
VDD3.3
R400
VDD3.3
10k/0402
R401
P0.8
TMS
TCK
P2.1
P0.7
+
10k/0402
C401
VDD5
no ass./4k7/0402
33R/0402
33R/0402
no ass./33R/0402
no ass./33R/0402
VDD3.3
DBGPRES#
Debugger pulls signal to GND
and keeps the on-board
wiggler in reset state
DBG2PRES#
10k/0402
VDD3.3
10k/0402
C
A
1
2
Debugger pulls signal to GND,
disconnects trace signals
C400
from ACT connector
and keeps the on-board
100nF/0402
wiggler in reset state
VDD3.3
V408
V404
V405
BAT54-02V
BAT54-02V
C431
100nF/0402
2
1
C430
100nF/0402
R427
R402
R403
R404
R410
C435
100nF/0402
2
4
6
8
10
12
14
16
18
20
C436
100nF/0402
1
3
5
7
9
11
13
15
17
19
C432
100nF/0402
VBAT
2
2+
1+
-
VDD5
C405
10uF/10V/0805
X400
C433
100nF/0402
VDD3.3
R429
1
VDD3.3
R430
A
1
VDD3.3 Supply
TP404
6
TP405
10K/0402
C406
Debug Connectors
C434
100nF/0402
5
no ass.
4
1
V406
10k/0402
VDD3.3
R419
VDD3.3
no ass.
R407
3
1
10nF/0402
C407
10uF/10V/0805
2
680R/0603
V403
LED-GN/D/0603
TP406
VDD3.3
R420
1
no ass./0R/0603
VDD5
no ass.
R405
C413
100nF/0402
2K2/0603
VDD3.3
V407
LED-RT/D/0603
1k5/0603
V401
LED-GN/D/0603
TP407
30
VDD5USB
Board User's Manual
no ass.
R406
Figure 28
1k5/0603
V402
LED-GN/D/0603
1
E
D
C
B
A
CPU_45B-V1
CPU Board XMC4500 SDRAM
Production Data
Power, Debug Connector, Reset, SDRAM
Revision 1.0, 2013-02-20
BAS3010A-03W
E
D
C
B
1
2Y
GND
GND
2
GND
no ass./10nF/0402
4
6
100nF/0402
NC7WZ07P6X
2A
1Y
C503
3
DBG2PRES#
1A
2
GND
GND
C502
VDD3.3
3
WPORST#
WTCK
WTMS
32
34
33
29
30
8
9
18
17
21
22
23
24
25
26
GND
VSS
EPAD
PORST#
TCK
TMS
XTAL1
XTAL2
RTC_XTAL_1
RTC_XTAL_2
VAREF
VAGND
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
Analog
Digital
4
Supply
HIB_IO_0
VBAT
P14.9
P14.8
P14.7
P14.6
P14.5
P14.4
P14.3
P14.0
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P0.8
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
VDDC1
VDDC
VDDP2
VDDP1
VDDP
USB_DUSB USB_D+
Hibernate/RTC
XMC4200_QFN48
no ass.
1
2
3
4
X501
27
EPAD
GND
510R/0603
100nF/0402
P0.7
TCK
CS
P2.1
Q500
R500
12MHZ/S/3.2X2.5
TDO
TDI
C511
1
DBGPRES#
VCC
GND
RESET#
GPIO-P0.3
DEBUG_LED# GPIO-P0.2
RESET#
DEBUG_LED#
U501
U1C0
DX0A-P0.4
DOUT0-P0.5
GPIO-P0.6
RXD
TXD
EN#
5
U1C1
DX0D-P0.0
UART2 (DM2)
RXD
TXD
TXACTIVE#
SWV
U0C1
DX2A-P2.3
DX1A-P2.4
DOUT0-P2.5
DX0A-P2.2
SPI Slave
CS_IN
CLK_IN
MISO
MOSI
UART
RXD
TDI
TDO
VDD3.3
U500
31
6
41
28
5
3
4
7
10
19
20
11
12
13
14
15
16
35
36
37
38
39
40
42
43
44
45
46
47
48
1
2
R501
R502
TCK
TMS
SWV
EN#
TXD
RXD
GND
VDD3.3
R504
GND
6
5
6
7
8
X500S
100nF/0402
C512
GND GND GND
1
2
3
4
5
X500C
7
Sheet: 5/5
8
18.10.2012 14:43:12
CPU_45B-V1
On-board Debugger
V1 / 04.04.2012 / Ma
Configure COMDIS# as open-drain output
Configure Debugger-P0.5 as USIC_Tx but only active while X-spy function is selected
Configure Debugger-P0.4 as USIC_Rx but only active while X-spy function is selected
Configure Debugger-P0.3 as RESET# detect input but with additional open-drain output capabilities
L500
BLM18PG600
GND
1
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Legal Disclaimer
GND
33R/0402
33R/0402
TCK
CS
TMS
P2.1
COMDIS#
P1.4
P1.5
RESET#
DEBUG_LED#
C505 100nF/0402
U0C0
DX0B-P1.4
DOUT0-P1.5
SCLKOUT-P1.1
SELO0-P1.0
C507 100nF/0402
SPI Master
MISO
MOSI
CLK_OUT
CS_OUT
C508 100nF/0402
TMS
TCK
C506 10uF/10V/0805
VDD3.3
C510 10uF/10V/0805
A
C509 100nF/0402
C
A
VDD5
V501
R506
R507
BAS3010A-03W
4k7/0402
10k/0402
On-board Debugger
C500 15pF/0402
V502 680R/0603
LED-GN/D/0603
V500
5
2
D2
4
3 D1
3
ESD8V0L2B-03L
On-board Debugger Concept
2
C501 15pF/0402
VDD3.3
R503
31
10k/0402
R505
Board User's Manual
1M/0402
Figure 29
ZX62-AB-5PA
1
E
D
C
B
A
CPU_45B-V1
CPU Board XMC4500 SDRAM
Production Data
On-board Debugger
Revision 1.0, 2013-02-20
C504 100nF/0402
CPU_45B-V1
CPU Board XMC4500 SDRAM
Production Data
1
2
3
4
U501
U304
A
U303
-
30
2
C
SJ3
X501
C509
C506
C502
+
JP300
32
5
43
2
R
C
V4
03 R
40
V4
7
01 R
40
V4
5
02 R
40
6
Q404
R306
3
32
C
C
30
0
7
31
C414
R420
V407
TP
4
TP 04
40
5
TP
40
6
TP
40
7
ADJ_3
X4
R307
02
C
5
30
Q
C
17.82
2.4
C211
V406
C210
26
R4425
R 424
R 423
R 421
R 04
V4 410
R
03
R4
02
R4
ADJ_1
01
C4400
C 400
R
30
1
C
1
30
31
6 L
30
0
C
SW400
30
9
C
7
42
R422
C
C
C415
R419
1
31
C
01
L3
30
6
C511
V301 C504 R502
C510
R305
SW402
C416
31
5
7
30
C
C 43
C 4 0
C 43 34
43 5
2
L500
R504
R505
C512
R430
R206
C417
L201
R203
C407 U401
C405
R417
R301
R416
V300 SW401
C200
R200
R415 R413
46
44
X2
00
2
80
C
U300
U306
C322
00
X4
20.99
8
30
4
32
R
37.50
C500
8
C501 C20 5
0
SJ2 C2
C319 R503
PS
3
31
75.00
Q500
R
81.03
R507
C505
C503
R500
46
C318
C
01
X4
04
R3
02
R3
2
04
R4
05
V4
U500
C
2
31
2
30
C
Q
10
R3
1
SJ
09
R3
1
14.70
6
43 31
4
C
U430
SH
FT 408
R
E
FL
U301
01
R4
C310
C507
C
1
43
C413
R506
C508
R429
93.57
02
U3
21
C3
ON
0
30
SW
C433
R
03
R3
C406
V501
44
C2
04
R414
R207
R202
R205
U200
V200
01
X2
C213
V201
ADJ_2
X500
V500
V502
R501
2
X203
R204
V408
C2
02
C212
Component Placement and Geometry
80
3.2
21.03
R300
SJ5
SJ4
X202
25.08
80
46
44
2
86.60
Alle Angaben in [mm] +/-0.1
Figure 30
Component Placement and Geometry
Board User's Manual
32
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Production Data
3.3
Bill of Material (BOM)
Table 11
BOM of CPU_45B-V1 Board
Pos
No.
Qty Value
Device
Reference Des.
1
1
0R/0603
Resistor
R416
2
2
1M/0402
Resistor
R200, R505
3
2
1k5/0603
Resistor
R405, R406
4
3
2k2/0603
Resistor
R306, R307, R420
5
3
4k7/0402
Resistor
R302, R304, R506
6
1
4u7F/0805
Capacitor, ceramic
C212
7
17
10k/0402
Resistor
8
2
10nF/0402
Capacitor
R204, R206, R207, R303, R309, R310,
R400, R401, R408, R414, R419, R422,
R429, R430, R431, R503, R507
C406, C415
9
8
10uF/10V/0805
Capacitor, ceramic
10
2
12MHZ/S/3.2X2.5
Crystal, NX3225GD, NDK
C308, C323, C324, C325, C405, C407,
C506, C510
Q302, Q500
11
6
15pF/0402
Capacitor
C312, C315, C316, C317,C500, C501
12
1
22R/0402
Resistor
R432
13
1
32.768KHZ
Crystal, NX3215SA, NDK
Q301
14
11
33R/0402
Resistor
15
4
74LVC1G66DCK
IC, Single Analog Switch
R202, R203, R402, R403, R421, R423,
R424, R425, R426, R501, R502
U301, U303, U304, U306
16
40
100nF/0402
Capacitor
17
2
100uF/T/10V/C
Capacitor, bipolar
C200, C202, C204, C205, C208, C210,
C211, C300, C301, C302, C305, C306,
C307, C309, C310, C311, C318, C319,
C321, C322, C413, C416, C417, C430,
C431, C432, C433, C434, C435, C436,
C400, C401, C502, C504, C505, C507,
C508, C509, C511, C512
C213, C414
18
1
219-02
Dual DIP-Switch, 0.1" SMD
SW300
19
1
270k/0402
Resistor
R415
20
2
510R/0603
Resistor
R313, R500
21
4
680R/0603
Resistor
R301, R305, R407, R504
22
3
BAS3010A-03W
Diode, SOD323, Infineon
V200, V408, V501
23
2
BAT54-02V
Diode, SC79, Infineon
V404, V405
24
1
BAV70
Diode, SOT23-3, Infineon
V406
25
1
BC858C
Transistor, SOT23-3, Infineon
Q404
Board User's Manual
33
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM
Production Data
26
1
BK-885
X402
BLM18PG600
Battery Holder, 12mm Coin
Cell
Ferrite Bead, 0603, Murata
27
4
28
2
ESD8V0L2B-03L
Diode, TSLP-3-1, Infineon
V201, V500
29
3
HSEC8_MATING-CARD Connector, Edgecard, Samtec X200, X201, X202
30
1
IFX1763_PADNOP
31
2
LED-GE/D/0603
Voltage Regulator, 3.3V LDO, U401
Infineon
LED, yellow
V300, V301
32
4
LED-GN/D/0603
LED, green
V401, V402, V403, V502
33
1
LED-RT/D/0603
LED, red
V407
34
1
IS42S16400F-7BL
Synchronous Dynamic RAM,
ISSI
U430
35
1
NC7WZ07P6X
IC, Dual Buffer OD, SC70-6
U501
36
1
POTI/10K/VERT
Potentiometer, K09K1130A8G, R300
ALPS
37
1
S2*10/1.27SO
X400
38
1
S25FL032P0XMFI01
39
3
TMPS2-SMD
Connector, FTSH-110-01-LDV-K-P, Samtec
IC, qSPI Flash Memory,
SPANSION
Switch, tactile
40
1
TPS2051BDBV
IC, Power Switch, SOT23-5
U200
41
1
XE3K_DM2+CTX
42
1
XMC4200_QFN48
Connector, FTSH-105-01-LM- X401
DV-K, w/o pin 7, Samtec
Connector, FLE-103-01-G-DV,
Samtec
IC, XMC4200, QFN48,
U500
Infineon
43
1
XMC4500_LFBGA144
IC, XMC4500, LFBGA144,
Infineon
44
2
ZX62-AB-5PA
Connector, Micro-USB, Hirose X203, X500
45
1
no ass.
Pinheader, 4-pin, 0.1" TH
X501
46
4
no ass.
Pinheader, 1-pin, 0.1" TH
TP404, TP405, TP406, TP407
47
1
no ass./0R/0603
Resistor
R417
48
1
no ass./4k7/0402
Resistor
R427
49
2
no ass./10k/0402
Resistor
R205, R413
50
1
no ass./10nF/0402
Capacitor
C503
51
2
no ass./33R/0402
Resistor
R404, R410
52
1
no ass.
Pinheader, 3-pin, 0.1" TH,
Hitex PowerScale
JP300
53
3
no ass.
Solder Bridge (open)
SJ1, SJ2, SJ3
54
2
0R/0402
Solder Bridge (closed by
resistor)
SJ4, SJ5
Board User's Manual
34
L201, L300, L301, L500
U302
SW400, SW401, SW402
U300
Revision 1.0, 2013-02-20
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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