XMC4000
32-bit Microcontroller Series for Industrial Applications
General Pu rp oses Direct Memory Access
(GPDMA )
AP32290
Application Note
About this document
Scope and purpose
This Application Note describes the usage of the General Purpose Direct Memory Access (GPDMA) in the
XMC4000 microcontroller series.
Various transfer modes of the GPDMA are described, showing how to use the GPDMA to transfer data to and
from several peripherals.
Applicable Products
XMC4000 Microcontrollers Family
References
Infineon: Example code: http://www.infineon.com/XMC4000 Tab: Documents
Infineon: XMC Lib, http://www.infineon.com/DAVE
Infineon: DAVE™, http://www.infineon.com/DAVE
Infineon: XMC Reference Manual, http://www.infineon.com/XMC4000 Tab: Documents
Infineon: XMC Data Sheet, http://www.infineon.com/XMC4000 Tab: Documents
V1.0
1
2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Table of Contents
Table of Contents
Table of Contents ..........................................................................................................................2
1
1.1
1.2
GPDMA Overview ..........................................................................................................3
Block diagram of GPDMA .................................................................................................................... 3
GPDMA Terminology ........................................................................................................................... 4
2
2.1
2.1.1
2.1.2
2.2
Flow control and Handshaking Interface .........................................................................5
Hardware handshaking ....................................................................................................................... 5
Enable of Hardware handshake ................................................................................................... 6
Routing service request signal to DMA channel ........................................................................... 6
Software handshaking ........................................................................................................................ 7
3
DMA transfer block size .................................................................................................8
4
4.1
4.2
4.3
Source and Destination addressing ................................................................................9
Address increment or decrement ....................................................................................................... 9
Gather transfer (Source) ................................................................................................................... 10
Scatter transfer (Destination) ........................................................................................................... 11
5
5.1
5.2
5.3
Block transfer types .................................................................................................... 12
Auto reloading of channel register ................................................................................................... 12
Contiguous address between blocks................................................................................................ 12
Block chaining using linked lists ....................................................................................................... 13
6
Service Request Generation ......................................................................................... 14
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
Multi block transfer of VADC result registers to RAM for motor control ............................ 15
PWM period match interrupt to trigger ADC conversion ................................................................. 16
GPDMA configuration for multiple block transfer ............................................................................ 18
Setting the transfer flow and priority ......................................................................................... 18
Enable the Hardware handshaking ............................................................................................ 18
Selecting the service request via the DMA Line Router ............................................................. 19
Source configuration .................................................................................................................. 19
Destination configuration ........................................................................................................... 20
Configure the block transfer type ............................................................................................... 20
Block transfer complete Interrupt .............................................................................................. 20
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
Single block transfer CRC checking ............................................................................... 21
Setting up FCE for CRC checking ...................................................................................................... 22
GPDMA configuration for Single block transfer ............................................................................... 22
Setting the transfer flow and priority ......................................................................................... 23
Source configuration .................................................................................................................. 23
Destination configuration ........................................................................................................... 23
Configure the block transfer type ............................................................................................... 23
Block transfer complete Interrupt .............................................................................................. 23
9
Revision History.......................................................................................................... 25
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GPDMA Overview
1
GPDMA Overview
The General Purposes Direct Memory Access (GPDMA) is a module within the XMC4000 series to transfer data
without any CPU interference. When a DMA transfer request is generated, the GPDMA transfers data stored
at the source address to the destination address.
1.1
Block diagram of GPDMA
GPDMA0
GPDMA1
GPDMA Channels
GPDMA Channels
Channel 7
Channel ….
Channel 1
Channel 0
Channel 3
Channel ….
Channel 1
Channel 0
Arbiter
DLR Line to Channel Selection
DLR Line to Channel Selection
For Hardware trigger
DMA Line Router
(DLR)
Figure 1
Arbiter
Source & Destination transfer
Peripherals
SRAM
GPDMA Block Diagram
Note: Please note that the number of DMA channels is different for XCM4500, XMC4400, XMC4200 and
XMC4100.
Figure 1 shows the block diagram of the GPDMA as implemented in XMC4000 series:
GPDMA channels: up to 12
Arbiter
Single AHB master interface for data transfer
Single AHB slave interface for register configuration
DMA Line Router (DLR)
One channel of the GPDMA is required for each source/destination pair. The master interface reads the data
from a source peripheral and writes it to a destination peripheral. Two physical transfers which consist of
Source to FIFO and FIFO to Destination are therefore required for each DMA transaction.
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GPDMA Overview
1.2
GPDMA Terminology
Service partners terms
The Source peripheral is the device from which the GPDMA reads data and stores the data in the
channel FIFO. The source peripheral teams up with a destination peripheral to form a channel.
The Destination peripheral is the device to which the GPDMA writes the stored data from the FIFO
(previously read from the source peripheral).
The GPDMA0 channels 0 and 1 provide a FIFO size of 32 Bytes. These channels can be used to execute burst
transfers up to a fixed length burst size of 8. The remaining channels FIFO size is 8 Bytes.
GPDMA
FIFO
Source
Figure 2
Destination
Source and Destination definition
Transfer terms
A Single transaction is made up of a data width size of 8/16/32 bit.
A Burst transaction can be composed of 1, 4 or 8 transaction.
A Block transfer shall transfer the number of transaction specified by the block transfer size.
Data width
(8/16/32 bit)
Data 19
Data 18
Data 17
Data 16
Burst Transaction
size (1/4/8)
Transaction 20
Transaction 19
Transaction 18
Transaction 17
Burst 5
Block Transfer
Data 03
Data 02
Data 01
Data 00
Figure 3
Transaction 4
Transaction 3
Transaction 2
Transaction 1
Burst 1
GPDMA transfer definition
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Flow control and Handshaking Interface
2
Flow control and Handshaking Interface
The device that controls the length of a block is known as the flow controller. The GPDMA, the source
peripheral, or the destination peripheral can be assigned as the flow controller depends on the selection of
the transfer flow in register CTLL.TT_FC. Typically if the block size is known, then the GPDMA must be
assigned as the flow controller.
Lastly the operation of the handshaking interface depends on whether the peripheral or the GPDMA is the
flow controller. The peripheral uses the handshaking interface to indicate to the GPDMA that it is ready to
transfer data over the AHB bus. A peripheral can request a DMA transaction through the GPDMA using the
Hardware or Software handshaking interface.
Table 1
Transfer flow, Flow Control and Handshake combination
Transfer flow
Flow controller
Handshaking
Memory to Memory
Memory to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Peripheral to Peripheral
GPDMA
GPDMA
GPDMA
GPDMA
Peripheral
Source peripheral
Peripheral
Destination peripheral
Not required
Hardware or Software
Hardware or Software
Hardware or Software
Software
Software
Software
Software
2.1
Hardware handshaking
Hardware handshaking means to use the peripheral service request signal (eg. VADC.G0SR0, ERU0.SR0,
CCU40.SR0 etc) to request for a DMA transfer via a DMA Line Router (DLR). Before the transfer can begin the
GPDMA and DLR units must be set up according to the application requirements.
GPDMA0
Source
FIFO
Source hardware
handshaking
Channel 0
CFGL.HS_SEL_SRC = 0
CFGH.SRC_PER
Destination
Destination hardware
handshaking
CFGL.HS_SEL_DST = 0
CFGH.DEST_PER
DMA
trigger
signal
DLR
DLR_SRSEL0/1
DLR_LNEN
Figure 4
Peripheral
Service
Request
Hardware handshaking interface
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AP32290
Flow control and Handshaking Interface
2.1.1
Enable of Hardware handshake
The hardware handshake are available for both source and destination of a particular channel which can be
enabled by setting the register CFGL.HS_SEL_SRC = 0 and CFGL.HS_SEL_DST = 0 respectively. And the
accepted polarity of the service request signal by the GPDMA is by default active high. However the polarity
of the signal can be change if necessary by setting CFGL.SRC_HS_POL or CFGL.DST_HS_POL.
2.1.2
Routing service request signal to DMA channel
The DMA Line Router (DLR) is used to route a required service request signal from a peripheral to a
particular GPDMA channel. There are a total of 12 DMA lines (RS0 to RS11) and each DMA line offers selection
to certain service request source which can be configured using register DLR_SRSEL0/1. (See table 4-5 of
reference manual for DMA request source selection)
Then the DLR_LNEN register is used to enable selected DLR line and to reset a previously stored and
pending service request. Finally individual GPDMA channel configuration register CFGH.SRC_PER or
CFGH.DEST_PER can select the assigned DLR line.
DMA Line Router
Table 4-5
DLR_SRSEL0
DLR_LNEN
GPDMA
GPDMA0_CHx_CFGH.
SRC_PER
GPDMA0_CHx_CFGH.
DEST_PER
RS0
LN0
DLR0
RS1
LN1
DLR1
RS2
LN2
DLR2
RS3
LN3
DRL3
RS4
LN4
DLR4
RS5
LN5
DLR5
RS6
LN6
DRL6
RS7
LN7
DLR7
RS8
LN8
DRL8
RS9
LN9
DLR9
RS10
LN10
DLR10
RS11
LN11
DLR11
Channel
x
DLR_SRSEL1
Figure 5
DLR Line to channel selection
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Flow control and Handshaking Interface
2.2
Software handshaking
Additionally the user can trigger a DMA channel using a software trigger. Usually this is done in the ISR
responding to a peripheral service request, for example the peripheral being ready to accept new data.
Before the transfer can begin the GPDMA and NVIC units must be set up according to the application
requirements. Once the peripheral (source or destination) is ready for a transaction it sends a service
request to the CPU. The interrupt service routine then uses the GPDMA software registers, to initiate and
control a DMA transaction.
Table 2
Software handshake configuration
Software handshake request
Enable software handshake
Register setting
Source Software Transaction Request
CFGL.HS_SEL_SRC = 1
REQSRCREG.CHx = 1
REQSRCREG.CHx = 1
Destination Software Transaction Request
CFGL.HS_SEL_DST = 1
REQDSTREG.CHx = 1
REQDSTREG.CHx = 1
By setting the software register CFGL.HS_SEL_SRC = 1 and/or CFGL.HS_SEL_DST = 1 enables software
handshaking on the source and/or destination of channel x.
To start software handshaking to perform a block transfer from source to FIFO on channel 0 simply set
REQSRCREG.CH0 = 1 and REQSRCREG.WE_CH0 = 1.
The same process can be done for software handshaking from FIFO to destination by setting
REQDSTREG.CH0 = 1 and REQDSTREG.WE_CH0 = 1.
GPDMA0
Source
FIFO
Source software
handshaking
CFGL.HS_SEL_SRC = 1
Channel 0
Destination
Destination software
handshaking
CFGL.HS_SEL_DST = 1
Software
Source request
REQSRCREG.CHx = 1
REQSRCREG.WE_CHx = 1
Figure 6
Destination request
REQDSTREG.CHx = 1
REQDSTREG.WE_CHx =1
Software handshaking interface
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DMA transfer block size
3
DMA transfer block size
Both the source and destination are required to configure the width (8/16/32 bit) of the data by
programming the source transfer width CTLL.SRC_TR_WIDTH and destination transfer width
CTLL.DST_TR_WIDTH of the CTLL register respectively. And the total number of data required for a transfer
block can be configured in the register CTLH.BLOCK_TS.
Source
SAR+2
SAR+1
SAR+0
Data 02
Data 01
Data 00
Block size
Data 9
Block size
SAR+9
Destination
CTLH.BLOCK_TS
= 10
8bit
Data Width
Data 9
DAR+2
DAR+1
DAR+0
Data 02
Data 01
Data 00
8bit
Data Width
CTLL.SRC_TR_WIDTH
= 00 (8bit)
Figure 7
DAR+9
CTLL.DST_TR_WIDTH
= 00 (8bit)
Block size configuration
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Source and Destination addressing
4
Source and Destination addressing
The GPDMA module needs to know the start address of the source and destination before it can begin any
transfer. Therefore the source and destination base address have to be programmed into the Source
Address register SAR and the Destination Address register DAR respectively.
4.1
Address increment or decrement
For every next DMA transaction, the source and destination address can be increment or decrement by
setting the Source Address Increment CTLL.SINC or Destination Address Increment CTLL.DINC. However by
default the SINC and DINC is set to incremental mode.
Source
CTLL.SINC =
Increment
OR
CTLL.SINC =
Decrement
SAR+2
SAR+1
SAR+0
SAR-1
SAR-2
Destination
CTLL.DINC =
Increment
OR
CTLL.DINC =
Decrement
Base address for source
Eg. SAR = 0x08040000
Figure 8
DAR+2
DAR+1
DAR+0
DAR-1
DAR-2
Base address for
Destination
Eg. DAR = 0x20000400
Source and Destination address configuration
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Source and Destination addressing
4.2
Gather transfer (Source)
Note: Only for GPDMA0 channel 0 to 1.
Gather transfer is relevant to source transfers within a block; we can program the GPDMA to have an interval
within a sequential address increment or decrement. This is known as the Gather transfer.
The Gather transfer works by incrementing or decrementing the source address by a programmed amount
specified in the Source Gather Count (SGRx.SGC) of the SGR register, which is also know as the “Gather
boundary “. When the Gather boundary is reached, the source address is then offset by the value stored in
the source gather interval (SGRx.SGI) field.
Source
SAR+15
SAR+14
SAR+13
SAR+12
SAR+11
SAR+10
SAR+9
SAR+8
SAR+7
SAR+6
SAR+5
SAR+4
SAR+3
SAR+2
SAR+1
SAR+0
Figure 9
GPDMA0_CHx_CTLL (x=0-1)
.SRC_GATHER_EN = 1
Data 15
Data 14
Data 13
CTL.BLOCK_TS
= 10
Data 12
Data 11
Data 13
Data 10
Data 09
Data 08
Data 07
Data 06
Data 12
Gather Interval
CHx_SGR.SGI = 1
Data 10
Gather count / Boundary
CHx_SGR.SGC = 2
Data 07
Data 09
Data 06
Data 05
Data 04
Data 04
Data 03
Data 03
Data 01
Data 02
Data 00
Block
transfer #1
Data 01
Data 00
Example of Gather transfer
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Source and Destination addressing
4.3
Note:
Scatter transfer (Destination)
Only for GPDMA0 channel 0 to 1.
Scatter transfer is relevant to destination transfers within a block; we can program the GPDMA to have an
interval within a sequential address increment or decrement. This is known as the Scatter transfer.
The Scatter transfer works by incrementing or decrementing the source address by a programmed amount
specified in the Destination Scatter Count (DSRx.DSC) of the DSR register, which is also know as the “Scatter
boundary “. When the Scatter boundary is reached, the destination address is then offset by the value stored
in the destination scatter interval (DSRx.DSI) field.
Destination
GPDMA0_CHx_CTLL (x=0-1)
.DST_SCATTER_EN = 1
CTL.BLOCK_TS
= 10
Data 13
Data 12
Data 10
Data 09
Data 07
Data 06
Block
transfer #1
Data 04
Data 03
Data 01
Data 00
Figure 10
DAR+21
DAR+20
DAR+19
DAR+18
DAR+17
DAR+16
DAR+15
DAR+14
DAR+13
DAR+12
DAR+11
DAR+10
DAR+9
DAR+8
DAR+7
DAR+6
DAR+5
DAR+4
DAR+3
DAR+2
DAR+1
DAR+0
Data 13
Data 12
Data 10
Data 09
Data 07
Data 06
Scatter Interval
CHx_DSR.DSI = 3
Data 04
Data 03
Scatter count / Boundary
CHx_DSR.DSC = 2
Data 01
Data 00
Example of Scatter transfer
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Block transfer types
5
Block transfer types
The types of DMA block transfer from source to destination are achievable by using the combinations of
Auto Reload method, Contiguous method or Linked List method.
Single block transfer
0. Single block transfer
Source
Destination
1
Multiple Block Reload/Contiguous transfer
1. Source Contiguous and Destination reload
Source
Destination
Multiple Block Reload/Contiguous and Linked List transfer
4. Source Contiguous and Destination Linked List
Source
Destination
1
1
1
Interval
2
2. Source Reload and Destination Contiguous
Source
Destination
6. Source Linked List and Destination Contiguous
Source
Destination
Interval
2
2
3
3
5. Source Reload and Destination Linked List
Source
Destination
7. Source Linked List and Destination Reload
Source
Destination
1
Interval
1
2
Interval
1
2
2
3
3
3. Source Reload and Destination Reload
Source
Destination
8. Source Linked List and Destination Linked List
Source
Destination
1
2
1
Interval
Interval
2
3
Figure 11
Types of block transfer
5.1
Auto reloading of channel register
For Auto reload method, means that the GPDMA channel registers SAR, DAR and CTL are reloaded with their
initial values at the completion of each block; hence there is no change in the source and destination
address. To configure for auto reload mode set CFGL.RELOAD_SRC = 1 and/or CFGL.RELOAD_DST = 1
5.2
Contiguous address between blocks
In this case the address between successive blocks is selected as a continuation from the end of the previous
block. To configure for contiguous method set CFGL.RELOAD_SRC = 0 or CFGL.RELOAD_DST = 0. Please
note that either the source or destination can be contiguous. However if register is set as
CFGL.RELOAD_SRC = 0 and CFGL.RELOAD_DST = 0 will result to a single block transfer method.
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Block transfer types
5.3
Block chaining using linked lists
To extend the flexibility of multi block transfer, we can reuse the concept of reloading the SAR, DAR, CTLH
and CTLL registers through the use of linked list. A chain of linked lists is pre programmed into the XMC flash
memory before the start of DMA transfer and each linked list contains the configuration of the CTLH, CTLL,
LLP, DAR and SAR. During the process of multi block transfer, the GPDMA will reprogram the channel
registers (CTLH, CTLL, LLP, DAR and SAR) according to the value stated in the linked list for that block prior
to the start of each block transfer. For the next block transfer, the GPDMA will reference the LLP register
which points to the next linked list.
Hence linked list transfer offers a very flexible way of DMA block transfer from different locations of the
source and destination.
Note: Linked list are only available on channels 0 and 1 of GPDMA0
Channel register value is
reloaded from the Linked list
GPDMA0
Linked list
created for
Block 0
transfer
Linked list
created for
Block 1
transfer
Linked list
created for
Block 2
transfer
Flash Memory
Channel0 register
Linked List 0
Linked List 1
Linked List 3
Control Register High: CTLH
CTLH
CTLH
CTLH
Control Register Low: CTLL
CTLL
CTLL
CTLL
Link List Pointer: LLP
LLP
LLP
LLP =
0x0000
Destination Address: DAR
DAR = D0
DAR = D1
DAR = D2
Source Address: SAR
SAR = S0
SAR = S1
SAR =S2
Note:
S0, S1, S2 are the base address for source
D0, D1, D2 are the base address for destination
Source
Block 1
Point to the next
Linked list
Point to the next
Linked list
Destination
Block 0
S1
D0
3
Block 2
1
S2
Block 1
2
D1
Block 0
Block 2
S0
Figure 12
D2
Multi block transfer using Linked List method
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Service Request Generation
6
Service Request Generation
The following DMA Events can be generated for each channel due to DMA activity Block Transfer Complete
Interrupt
DMA Transfer Complete Interrupt
Destination Transaction Complete Interrupt
Source Transaction Complete Interrupt.
Error Interrupt.
Each DMA Event for each channel is directly stored in the according “RAW Status” bit.The user software can
control the processing by writing to the according “Mask” and “Clear” bits. Once the event is forwarded to
the “Status” bit its occurrence is registered in the Combined Interrupt Status Register and a service request
is triggered to the NVIC which is linked to the interrupt nodes of GPDMA0.SR0 or GPDMA1.SR0.
Figure 13
DMA Event to Service Request Flow
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Multi block transfer of VADC result registers to RAM for motor control
7
Multi block transfer of VADC result registers to RAM for
motor control
The CCU8 is used to generate the center align PWM for IGBT switching. [1] Hence during CCU8 period match
interrupt, CCU80.SR2 signal will be used to trigger VADC queue source conversion to measure the line
current and back EMF. [2] After completion of the ADC conversion, the result interrupt VADC.G0SR2 is
generated to trigger the GPDMA channel 0 via the DLR. [3] Once the assigned channel received the hardware
handshaking signal, the GPDMA shall then transfer the values from the VADC result register (Source) to a
designated RAM array (Destination). [4] Finally a block transfer complete interrupt will be generated by the
GPDMA to indicate an update of the ADC result value in the RAM array has been done and ready for futher
processing.
Software
XMC4500
GPDMA0
GPDMA_VADC_Res_Update
DLR Line to
Channel
Selection
GPDMA
Channel 0
Block transfer
interrupt
4
3
DMA Line Router
(DLR)
Hardware signals
For Hardware
handshake
VADC.
2
Source to Destination
DMA transfer
G0SR2
Current_U
Current_V
Current_W
BEMF_U
BEMF_V
BEMF_W
Period
Match
interrupt
VADC_G0
SRAM
Result
Interrupt
VADC_G0_RES0
VADC_G0_RES1
DMA_RES0
DMA_RES1
Queue
Source
VADC_G0_RES7
DMA_RES7
1
CCU80.SR2
CCU8
Period match
interrupt
Figure 14
PWM center
aligned
Block diagram for fast VADC result update
Therefore for this use case, we shall make the following configuration for GPDMA channel 0.
Hardware handshake interface: VADC result interrupt signal
Block transfer size = 8 and Width = 16bit
Source: VADC result registers [0-7] VADC_G0_RES0 and Destination: RAM
Gather transfer is used as we only want to extracted 16bit result from the 32bit VADC result register
Block Transfer type: Source reload and Destination reload
GPDMA interrupt: Block complete interrupt
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Multi block transfer of VADC result registers to RAM for motor control
7.1
PWM period match interrupt to trigger ADC conversion
Setting up for CCU8 PWM period match interrupt
From “Table 19-13 Digital Connections in the XMC4500” of the reference manual, we understand that the
VADC module can be triggered by CCU8 via signals from CCU80.SR2 or CCU80.SR3.
Figure 15
Table 19-13 Digital Connections in the XMC4500
Therefore for this case we shall configure the CCU8 period match event to be linked to service request node
CCU80.SR2 as the triggering signal for VADC conversion.
XMC_CCU8_SLICE_EnableEvent(PWM_SLICE_PTR, XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH);
XMC_CCU8_SLICE_SetInterruptNode(PWM_SLICE_PTR, XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH,
XMC_CCU8_SLICE_SR_ID_2);
NVIC_SetPriority(CCU80_2_IRQn, 3U);
NVIC_EnableIRQ(CCU80_2_IRQn);
Setting up for Queue source AD conversion upon external trigger request
This is to enable the ADC for external trigger of XMC_CCU_80_SR2 at the rising edge.
XMC_VADC_QUEUE_CONFIG_t g_queue_handle =
{
.req_src_priority = (uint8_t)3,
.conv_start_mode = XMC_VADC_STARTMODE_WFS,
.external_trigger = (bool) true,
.trigger_signal
= XMC_CCU_80_SR2,
.trigger_edge
= XMC_VADC_TRIGGER_EDGE_RISING,
.gate_signal
= XMC_VADC_REQ_GT_A,
.timer_mode
= (bool) false,
};
The below configuration for Queue entry 0, means that it will start AD conversion on channel number 0 upon
receiving an external trigger request.
XMC_VADC_QUEUE_ENTRY_t g_queue_entry[VADC_QUEUE_MAX] =
{
//Queue 0
{
.channel_num = 0,
.refill_needed = true,
.generate_interrupt = false,
.external_trigger = true
},
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Multi block transfer of VADC result registers to RAM for motor control
}
Setting up ADC result event to trigger GPDMA transfer
Next we need to enable the Result Event of the last AD conversion channel in the queue. This is to indicate
that the conversion has completed for all channels and the results are ready. Hence we can then route this
signal to trigger the GPDMA for transfer.
XMC_VADC_RESULT_CONFIG_t g_result_handle[VADC_RES_MAX] =
{
// Result register 7
{
.post_processing_mode
.data_reduction_control
.part_of_fifo
.wait_for_read_mode
.event_gen_enable
},
=
=
=
=
=
XMC_VADC_DMM_REDUCTION_MODE,
0,
false,/* No FIFO */
true, /* WFS */
true /* Result event */
}
For this ADC Result Event, we shall link it to service request node VADC.G0SR2.
XMC_VADC_GROUP_SetResultInterruptNode(VADC_G0, 7, XMC_VADC_SR_GROUP_SR2);
NVIC_SetPriority(VADC0_G0_2_IRQn, VADC0_G0_2_IRQn_10);
NVIC_EnableIRQ(VADC0_G0_2_IRQn);
Application Note
17
V1.0, 2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Multi block transfer of VADC result registers to RAM for motor control
7.2
GPDMA configuration for multiple block transfer
To begin the GPDMA configuration we had to create a channel configuration structure as shown below. After
that the initialization parameters of the DMA channel shall be configured within this structure.
XMC_DMA_CH_CONFIG_t GPDMA0_Ch0_config =
{
.enable_interrupt = true,
.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
.src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
.enable_src_gather = true,
.enable_dst_scatter = false,
.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
.src_addr = (uint32_t) &VADC_G0->RES[0],
.dst_addr = (uint32_t) &verify_ADC_Result[0],
.src_gather_interval = 1,
.src_gather_count = 1,
.dst_scatter_interval = 0,
.dst_scatter_count = 0,
.block_size = 8,
.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD,
.priority = XMC_DMA_CH_PRIORITY_7,
.src_handshaking = XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE,
.src_peripheral_request = DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_1,
};
7.2.1
Setting the transfer flow and priority
As hardware handshaking is required only from the source peripheral (VADC). Therefore we can select the
transfer flow from peripheral to memory (_P2M) with DMA _DMA) as the flow controller.
Since there is no other DMA channel is configured in this case, therefore the priority is not relevant.
.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
.priority = 7,
7.2.2
Enable the Hardware handshaking
When the VADC (Source) is ready, it shall instruct the GPDMA to transfer data from the result registers to the
GPDMA FIFO. For this case hardware handshaking is necessary for the source. Next to transfer data from the
GPDMA FIFO to memory (Destination), no handshaking is required for the destination as the memory is
always in ready state.
.src_handshaking = XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE,
Application Note
18
V1.0, 2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Multi block transfer of VADC result registers to RAM for motor control
7.2.3
Selecting the service request via the DMA Line Router
After the hardware handshake is enabled, the next thing is to route the service request signal VADC.G0SR2
(VADC result event) to GPDMA channel 0. This can be done by simply searching for VADC_G0SR2 in the file
xmc_dma_map.h and assigned the macro to the configuration structure as shown below:.src_peripheral_request = DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_1,
7.2.4
Source configuration
The source consists of 8 VADC result registers from VADC_G0RES0 to VADC_G0RES7 (block size = 8) with
individual 16 bit RESULT (transfer width = 16bit) within the 32bit register. From the assigned base address of
the VADC_G0_RES_ADDRESS, the GPDMA will increament according to the programmed transfer width to
the next address location.
Note: Block size configuration is the same for both the source and destination
.block_size = 8,
.src_addr = VADC_G0_RES_ADDRESS,
.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
Note: One word is equal to 16bit
As only the 16bit RESULT is required out of the 32bit result register, therefore we can program the GPDMA to
transfer one word (Gather count = 1) from the start of the base address followed by interval of one word
(Gather Interval =1) for the next word to be transferred.
.enable_src_gather = true,
.src_gather_count = 1,
.src_gather_interval = 1,
0x4000471C
0x40004708
0x40004704
0x40004700
G0RES7.XXXXXX
G0RES7.RESULT
G0RES2.XXXXXX
G0RES2.RESULT
G0RES1.XXXXXX
G0RES1.RESULT
G0RES0.XXXXXX
G0RES0.RESULT
Interval
Count
16bit
Figure 16
Gather transfer
Application Note
19
V1.0, 2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Multi block transfer of VADC result registers to RAM for motor control
7.2.5
Destination configuration
An array of 8 words (transfer width = 16bit) is created for the storage of the converstion result. Therefore the
destination is configured with the base address (&DMA_ADC_Result[0])of the array with incremental count.
.dst_addr = (uint32_t)&DMA_ADC_Result[0],
.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
7.2.6
Configure the block transfer type
The GPDMA is programmed for multiblock source reload and destination reload.
.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD,
7.2.7
Block transfer complete Interrupt
After a successful DMA block transfer of the VADC result registers to the designated RAM location, the user is
notified with a block transfer complete interrupt from the GPDMA.
.enable_interrupt = true
void GPDMA_Init(void)
{
XMC_DMA_CH_EnableEvent(XMC_DMA0, CH0, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
NVIC_SetPriority(GPDMA0_0_IRQn, 11); //Priority no.11
NVIC_EnableIRQ(GPDMA0_0_IRQn);
}
User can place their codes in the interrupt routine to process the value of the result registers.
#define GPDMA_BlockTransfer_ISR
void GPDMA_BlockTransfer_ISR(void)
{
uint32_t event;
GPDMA0_0_IRQHandler
event = XMC_DMA_CH_GetEventStatus(XMC_DMA0,CH0);
if(event == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
{
XMC_DMA_CH_ClearEventStatus(XMC_DMA0, CH0,
XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
}
/* Coding to process array verify_ADC_Result[0] */
}
Application Note
20
V1.0, 2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Single block transfer CRC checking
8
Single block transfer CRC checking
In this use case, [1] the GPDMA is used to feed the Flexible CRC Engine (FCE) to calculate the CRC-32 on a
fictitious frame of data. In this process the CRC-32 of a frame of 256 words is calculated. [2] When the block
transfer is completed an interrupt will be triggered. [3] And in the interrupt handler, the GPDMA shall
compare the values of the calculated CRC with a pre determined CRC value stored in the CRC check register.
If the calculated CRC matches the expected one, then the status of a variable will be updated as PASS.
XMC4500
Memory
FCE
GPDMA0
Channel 0
CRC_data
[256]
1
Source address Reg
= CRC_data[0]
Dest. Address
Reg = FCE_IR
2
Block transfer
interrupt
CRC Input register
CRC Result
register
=?
CRC Check
register
3
Software
GPDMA_BlockTransfer_ISR
Figure 17
FCE upload with DMA
Therefore for this use case, we shall make the following configuration for GPDMA channel 0.
Block transfer size = 256 and Width = 32bit
Source: CRC_Data (Memory) and Destination: CRC input register
Block Transfer type: Single block transfer
GPDMA interrupt: Block complete interrupt
Application Note
21
V1.0, 2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Single block transfer CRC checking
8.1
Setting up FCE for CRC checking
The FCE is configured to use CRC Kernel 0, which is a CRC32 with ethernet polynomial of 0x04C11DB7. And
the initial value (seedvalue) is configured as 0xffffffff.
XMC_FCE_t crc_engine =
{
.kernel_ptr = FCE_KE0,
.fce_cfg_update.config_xsel = true,
.fce_cfg_update.config_refin = true,
.fce_cfg_update.config_refout = true,
.seedvalue = 0xffffffffU
};
The check value is aslo input into the CRC Check register such that the FCE hardware can do a comparison
with the CRC Result register to determine if they are matching.
#define CRC_CHECK_VALUE
0x99f69cd9
/* Set expected CRC-32 */
XMC_FCE_UpdateCRCCheck(&crc_engine, CRC_CHECK_VALUE);
8.2
GPDMA configuration for Single block transfer
For this use case single block DMA transfer is being used with transfer flow from Memory to Memory as
handshaking is not required due to the reason that both the memory and FCE are in ready state.
XMC_DMA_CH_CONFIG_t GPDMA0_Ch0_config =
{
.enable_interrupt = true,
.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32,
.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
.src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
.enable_src_gather = false,
.enable_dst_scatter = false,
.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2M_DMA,
.src_addr = (uint32_t) &CRC_data,
.dst_addr = (uint32_t) &(FCE_KE0->IR),
.src_gather_interval = 0,
.src_gather_count = 0,
.dst_scatter_interval = 0,
.dst_scatter_count = 0,
.block_size = 256,
.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
.priority = XMC_DMA_CH_PRIORITY_0,
};
Application Note
22
V1.0, 2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Single block transfer CRC checking
8.2.1
Setting the transfer flow and priority
The FCE and memory does not require handshaking, as they are always ready to accept new data. Therefore
transfer flow memory to memory (_M2M) with DMA as the flow controller (_DMA) is chosen. For priority
setting, it is not relevant since there is no other DMA channel is configured in this case.
.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2M_DMA,
.priority = XMC_DMA_CH_PRIORITY_0,
8.2.2
Source configuration
The source refers to a 32bit array CRC_data with a size of 256 words (block size = 256) for CRC checking.
Therefore the base address and transfer width can be configured as shown below with address increment
after every single word.
.block_size = 256,
.src_addr = (uint32_t) &CRC_data,
.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32,
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
8.2.3
Destination configuration
And the destination refers to the FCE input register which has a data width of 32 bit. As we want to transfer
always to the input register of the FCE so there is no change to the address after every transaction.
.dst_addr = (uint32_t) &(FCE_KE0->IR),
.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
8.2.4
Configure the block transfer type
The single block transfer is used and after the transfer is completed the DMA channel will be disabled.
.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
8.2.5
Block transfer complete Interrupt
After a successful DMA block transfer of the CRC_data to the FCE input register, the user is notified with a
block transfer complete interrupt from the GPDMA.
.enable_interrupt = true
#define GPDMA0_0_IRQn_11
11
void GPDMA_Init(void)
{
XMC_DMA_CH_EnableEvent(XMC_DMA0, CH0, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
NVIC_SetPriority(GPDMA0_0_IRQn, GPDMA0_0_IRQn_11);
NVIC_EnableIRQ(GPDMA0_0_IRQn);
}
Application Note
23
V1.0, 2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Single block transfer CRC checking
With this interrupt, the user can instruct the GPDMA to compare the value of the CRC result register with the
CRC check register. If both values are the same the “verify_CRC_check” shall be updated with PASS.
#define GPDMA_BlockTransfer_ISR
GPDMA0_0_IRQHandler
void GPDMA_BlockTransfer_ISR(void)
{
if (XMC_FCE_GetEventStatus(&crc_engine, XMC_FCE_STS_MISMATCH_CRC) == false)
{
verify_CRC_check = PASS;
}
else
{
verify_CRC_check = FAIL;
}
}
Application Note
24
V1.0, 2015-07
General Purposes Direct Memory Access (GPDMA)
AP32290
Revision History
9
Revision History
Current Version is V1.0, 2015-07
Page or Reference
Description of change
V1.0, 2015-07
Initial Version
Application Note
25
V1.0, 2015-07
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