Peripheral - Universal Serial Interface Channel (USIC)

USIC
Universal Serial Interface Channel
XMC™ Microcontrollers
November 2014
USIC
Universal Serial Interface Channel
Interruption Generation
Highlights

Baud rate Generator
UART
Optional
Shared 64
Word FIFO
Buffer
Date
Handling and
More
SPI/Dual SPI/Quad SPI
LIN
Data Shifting
IO Stage
IIC
IIS
USIC channel 1

Baud rate Generator
UART
Optional
Shared 64
Word FIFO
Buffer
Date
Handling and
More
SPI/Dual SPI/Quad SPI
Data Shifting
LIN
IO Stage
Pins
Common Bus Interface
USIC channel 0
SRx
Each USIC module provides two
universal serial communication
channels to interface with external
devices. It is tailored for various serial
protocols like UART, SPI, IIC and IIS. A
shared 64 words FIFO buffer is
available in each USIC module.
IIC
IIS
Key Feature
Customer Benefits
› Flexible serial interface that
supports UART, SPI, IIC and IIS
protocol
› Support for Standard, Dual and
Quad SPI mode
› Shared FIFO buffer available in
every USIC channel
› Common serial communication
protocol are supported by one
peripheral
› Direct hardware control of all signals
needed for external memory device
› Offload CPU and CPU can perform
other critical task
Copyright © Infineon Technologies AG 2015. All rights reserved.
2
USIC
Flexible Serial Interface Protocol
› USIC support different serial communication protocols on every
channel
– UART, SSC/SPI, IIC, IIS
› This gives user the flexibility to select the desired serial interface
on each USIC channel
› This flexibility allows user to have the same or different protocol
on the each USIC channel
Copyright © Infineon Technologies AG 2015. All rights reserved.
3
USIC
Support Dual and Quad-SPI
› The transmit data can be shifted out one, two or four bits each
time depending on the selected mode
› Receive data also can be shifted in one, two or four bits each
time depending on the selected mode
› The data throughput on Quad-SPI is four times higher than the
standard SPI
Data output 3
Data output 2
Data output 1
Data input 3
Transmit Shift
Register
Data output 0
Data input 2
Data input 1
Data input 0
Transmit
Buffer
(TBUF)
Copyright © Infineon Technologies AG 2015. All rights reserved.
Receive
Shift
Register
Receive
Buffer
(RBUF)
4
USIC
FIFO Buffer Capability
› Total of 64 data words buffer entries shared between two
channel for transmit and receive.
› User configurable FIFO buffer size.
› Offload CPU to perform other tasks while the USIC is
transmitting.
Copyright © Infineon Technologies AG 2015. All rights reserved.
5
USIC
System Integration
NVIC
ERU
USIC
GPIO
CCU
XMC4500
XMC4400
XMC41/200
●
●
●
XMC1100
XMC1200
XMC1300
●
●
●
USIC is interconnected with several
modules in the MCU system.
NVIC – To generate interrupt
›
Target applications
– Connectivity/Communication
GPIO – Signal connection to the Input
and Output pins
ERU
– If the input to USIC does not
have direct connection to USIC,
the signal can be mapped to
ERU module and connected to
USIC
CCU4 – Input signal to CCU4 module
Copyright © Infineon Technologies AG 2015. All rights reserved.
6
Application Example
Interface with external flash via Quad SPI
Overview
SCLK
CS
IO0
MCU
IO1
IO2
IO3
MultiI/O
Flash
In Brief
USIC able to interface with external
flash that support multi I/O via quad
SPI communication where data
throughput can be dramatically
increased compared to the standard
SPI communication.
In today’s market, there are SPI flash memory
that support multiple I/O SPI capability. This
means the transferring of data is done with
multiple data lines using SPI protocols.
To support this feature, Dual and Quad SPI has
been implemented into USIC module. Using
quad SPI to interface with external flash, the
data throughput is increase by four times over
standard SPI.
This allows applications that require higher
data transfer rate to external memory to be
implemented using USIC. As the protocol is
taken care by the USIC module, software
implementation to transfer and receive data
becomes simple and easy.
Copyright © Infineon Technologies AG 2015. All rights reserved.
7
Table of contents
1
Flexible Data Word and Data Frame Length Control
2
Transmit Control Information
3
Flexible Routing
4
Transfer Trigger Capability
5
Interrupt Events
6
Baud Rate Generation
7
Debugger Support
Copyright © Infineon Technologies AG 2015. All rights reserved.
8
USIC - Highlight features
Flexible Data Word and Data Frame Length Control
› There are two options to handle data frame size
› Option 1: Known frame length
– Set to a fixed length
– Support up to 63-bit
Example: SPI in Master Mode
Data word = 8-bit; Data Frame = 32-bit
Data
word
Data
word
Data Frame
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9
USIC - Highlight features
Flexible Data Word and Data Frame Length Control
› Option 2:Flexible frame length
– Provide infinite frame length
– The frame length can be dynamically controlled by End of
frame bit
Example: SPI in Master Mode
Data word = 8-bit; Data Frame = 64 (infinite)
Set End of Frame Data frame is ended
bit before the last after transmitting
data byte
the last byte
Copyright © Infineon Technologies AG 2015. All rights reserved.
10
USIC - Highlight features
Transmit Control Information (1/3)
› Transmit control information (TCI) is a 5bit data generated automatically when
the data to be transmit is written to the
transmit buffer input location TBUFx or
FIFO transmit buffer - INx (x = 00 – 31).
›
TCI = 00000
TBUF00 / IN00
TCI = 00001
TBUF01 / IN01
…
TCI = 11111
…
TBUF31 / IN31
TCI can be used as an additional control parameter for various
function such as:
– Dynamic change of data word length or data frame length
– Automatic slave select for SPI
– Channel select control for IIS
Copyright © Infineon Technologies AG 2015. All rights reserved.
11
USIC - Highlight features
Transmit Control Information (2/3)
› Dynamic change of data word length
– With correct configuration, TCI can be use to adjust data word
length and to end the data frame.
– Bit 3 – 0 of TCI configures the data word length and bit 4 of
TCI indicates this is last data of the frame (End of Frame).
Example:
1) Writing data to TBUF07
TBUF07
TCI = 0 0111
End of Frame = 0
(not end of frame)
Data word length = 8 bit
2) Writing data to TBUF23
TBUF23
TCI = 1 0111
End of Frame = 1
(Is end of frame)
Data word length = 8 bit
Copyright © Infineon Technologies AG 2015. All rights reserved.
12
USIC - Highlight features
Transmit Control Information (3/3)
› Automatic Slave select
– TCI also can be used to trigger slave select signal
automatically when USIC is operated in SPI Master mode.
– Total of 8 slave select signal available in each USIC channel
and the generated 5-bit TCI value can control only Slave
select signal 0 – 4.
Example:
1) Writing data to TBUF01
TBUF01
TCI = 00001
Slave Select [7:0]= 0x01
Enable
Slave Select 0
2) Writing data to TBUF15
TBUF15
TCI = 01111
Slave Select [7:0]= 0x0F
Copyright © Infineon Technologies AG 2015. All rights reserved.
Enable
Slave Select 0,
1 ,2 & 3
13
USIC - Highlight features
Flexible Routing
› Each channel offers several possible input and output pins
› Pin reconfiguration without resetting the device
› Refer to USIC-Interconnect chapter in device Reference Manual
on the available pins for USIC transmit and receive pin
Input pin selection A
Input pin selection G
Data input
USIC
Data Output
Channel Shift Clock Output (SCLK)
Output pin selection A
Output pin selection G
SCLK pin selection A
SCLK pin selection E
Copyright © Infineon Technologies AG 2015. All rights reserved.
14
USIC - Highlight features
Transfer Trigger capability
› Data transfer can be gated and only transfer when trigger signal
is triggered.
› Events outside USIC module (i.e. CCU4 timer or input pin) can
trigger a data transfer.
Transfer
Trigger
PORTS
USIC
Control
Input
Valid
signal
Transmit
Buffer
Data Out
› Refer USIC-Interconnect chapter in device Reference Manual for
the available pins for USIC Control Input.
Copyright © Infineon Technologies AG 2015. All rights reserved.
15
USIC - Highlight features
Interrupt Events (1/2)
› Support various interrupt for every protocol
(e.g. UART data word)
– Transmit Shift interrupt (TSI)
– Transmit Buffer interrupt (TBF)
– Standard Receive interrupt (RI)
– Received Start interrupt (RSI)
– Alternative Receive interrupt
– Data Lost interrupt
TBF
RSI
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TSI
RI
16
USIC - Highlight features
Interrupt Events (2/2)
› Alternative Receive Interrupt
– UART – Parity error occurs
– SPI – Reception of first data word in a data frame
– IIC – First data word of new data frame
– IIS – Data for the right channel
› Support also protocol related interrupt
– Some examples:
– UART – Noise detection, Collision detection, Sync break detection..etc
– SPI – MSLS event, Slave Select input event, Parity Error Interrupt
– IIC – Start Condition, Stop Condition, ACK received, NACK received..etc
– IIS – WA rising/ falling edge, WA end event, Trigger signal activation
Copyright © Infineon Technologies AG 2015. All rights reserved.
17
USIC - Highlight features
Baud Rate Generation
› Dedicated baud rate generator available on each USIC channel
to provide independent baud rate generation
› USIC baud rate can be selected from internal system frequency
or external clock source
› Baud rate generator provides protocol specific signal generation
Internal
Clock
External
Clock
Master Clock (MCLK)
Baud rate
generator
Shift Clock (SCLK)
Copyright © Infineon Technologies AG 2015. All rights reserved.
18
USIC - Highlight features
Debugger Support
› When received data read from received buffer (RBUF), the read
status will change and new incoming data will be transferred to
RBUF
› To prevent read status change during debugging, USIC offers
receive buffer register for debugging (RBUFD)
›
RBUFD is a mirrored register
containing the same data as
RBUF
Receive Buffer
Register for Debugging
Read status
remains unchanged
after debugger
read from RBUFD
Copyright © Infineon Technologies AG 2015. All rights reserved.
19
General Information
› For latest updates, please refer to:
http://www.infineon.com/xmc1000
http://www.infineon.com/xmc4000
› For support:
http://www.infineonforums.com/forums/8-XMC-Forum
Copyright © Infineon Technologies AG 2015. All rights reserved.
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Disclaimer
The information given in this training materials is given as a hint for
the implementation of the Infineon Technologies component only and
shall not be regarded as any description or warranty of a certain
functionality, condition or quality of the Infineon Technologies
component.
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