XMC1000 System XMC™ Microcontrollers August 2015 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 2 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 3 XMC1000 Block Diagram System Master CPU System Slaves SCU PFU ARM® Cortex®-M0 RTC ERU0 ERU1 CCU40 CCU41 CCU80 CCU81 POSIF0 POSIF1 BCCU ADC PAU WDT Bus Matrix Flash AHB2APB Bridge ROM & RAM PORTS MATH LEDTS0 LEDTS1 LEDTS2 USIC0 USIC1 CAN 16-bit APB Bus PRNG 2015-08-28 TSE ACMPx XMC1000 is based on a Cortex® -M0 architecture with a rich peripheral set for sensor/actuator applications. Copyright © Infineon Technologies AG 2015. All rights reserved. 4 Architecture of Cortex-M0 Highlights Cortex®-M0 is a lean 32-bit processor core with 0.84 DMIPS/MHz. It allows modern programming style in C-language to reduce development time. Its optimised interrupt controller allows use in hard real-time applications. Widespread standard core offers a broad variety of software tools and components. Key Features Customer Benefits › Standard core › › Modern 32-bit instruction set › › Upwards compatible to Cortex® M3/M4 2015-08-28 › Availability of third party tools, software libraries and engineering force Using C language reduces development time and maintenance cost Offers high scalability with reusing software components Copyright © Infineon Technologies AG 2015. All rights reserved. 5 Architecture of Cortex®-M0 Standard Core (1/2) 4x Breakpoint Unit 2x Watchpoint Unit Cortex®-M0 Core 0.84 DMIPS/MHz Thumb-2 / Thumb ISA Integrated Nested Vectored Interrupt Controller and SYSTICK Timer Debug Access Port: Single Pin Debug (SPD) or Serial Wire Debug (SWD) 1x AMBA AHBLite Bus Source: http://www.arm.com 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 6 Architecture of Cortex®-M0 Standard Core (2/2) ARM Cortex®-M Thumb Thumb-2 ARM architecture Core architecture Cortex®-M0 Most Subset ARMv6-M Von Neumann Cortex®-M3 Entire Entire ARMv7-M Harvard Cortex®-M4 Entire Entire ARMv7E-M Harvard ARM Cortex®-M Hardware multiply Hardware divide Saturated math DSP exten sions Floatingpoint Cortex®-M0 1 or 32 cycle No No No No Cortex®-M3 1 cycle Yes Yes No No Cortex®-M4 1 cycle Yes Yes Yes Optional Source: Wikipedia 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 7 Architecture of Cortex®-M0 Modern 32-bit Instruction Set Cortex®-M0 is an ARMv6-M architecture. It has a subset of Thumb and Thumb-2 instruction sets. Cortex® M0 is fully upwards compatible to Cortex®-M4 Source: http://www.arm.com 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 8 Architecture of Cortex®-M0 CPU Performance Benchmark CoreMark CRC Routine (The higher the better) (The lower the better) 7759 400 clock cycles millisec 5681 3681 119 80 65 XMC4000 Flash cached XMC4 @120 MHz, 3 WS 2015-08-28 XMC4000 Flash uncached 3100 XMC1000 Flash prefetched XMC1 @48 MHz, 2.5 WS 31 178 97 XMC4000 XMC4000 XMC1000 XMC1000 Flash unFlash Flash RAM cached cached XMC4 @120 MHz, 3 WS Copyright © Infineon Technologies AG 2015. All rights reserved. XMC1 @32 MHz, 1.3 WS 9 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 10 Memories Highlights Memory Flash BootROM SRAM The memory map is based on standard ARM® Cortex®-M0 system memory map. The linear address space of the 32-bit architecture provides full access to all code, memory and peripheral addresses. Key Feature Customer Benefits › Parity protected RAM and ECC protected flash › Memory and IP protection › Excellent program/erase timing with high endurance › High code/data integrity due to hardware error detection and correction mechanism. › Protected against unauthorized readout of memory content › No need for external EEPROM, reduced system cost 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 11 Memories Parity Protected RAM and ECC protected Flash › RAM supports parity bit generation and error detection – Parity bit can be inverted to force an error for test purposes – Hardware support for ClassB Library saves CPU load for volatile memory test › Flash supports ECC with: – Single bit error correction – Partial double bit error detection › Flash supports automatic verification of programmed data › Flash supports configurable erase and write protection › Flash provides a low power sleep mode – Enabled/disabled through NVMCONF.NVM_ON bit › Zero-wait-state access to RAM @48 MHz – 8-bit, 16-bit and 32-bit write access – 32-bit read access 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 12 Memories Memory and IP Protection (1/2) › IP Protection – Unauthorized external access to Flash is blocked – Boot options to download and execute external code are blocked – Unauthorized read out of critical data and user IP from Flash is prevented – Only user code originating from the Flash can be executed – Blocking mechanism – After user code is programmed into Flash, the Boot Mode Index (BMI) is expected to be switched to “user productive mode” – Entry to other boot modes is blocked – User code can trigger a change in BMI but that will first erase the complete user Flash 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 13 Memories Memory and IP Protection (2/2) › Access protection during run-time – Flash Write and Erase Protection – A range of Flash sectors starting from sector 0 can be userconfigured to be erase- and write-protected – SFR Bit Protection Scheme – Specific system-critical SFR bits (e.g. CLKCR.PCLKSEL) require a special software write sequence – Privilege Access Control Scheme – Each memory address range (or sub-block) that supports this scheme has a disable bit – When the bit is set, the corresponding memory address range is rendered invalid – Any access to such an invalid address causes a bus error – The same bit can be cleared to enable access again 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 14 Memories Excellent timings with high endurance Parameter Min. Typical Max. Unit Voltage range 1.8 - 5.5 V Erase time per page 6.8 7.1 7.6 ms Page = 256 bytes Erase all - - 8 s At 200 Kbytes Write time per block 102 152 204 µs Block = 16 bytes Data retention 20 - - years Ta = 85°C, 100 cycles @ 200 Kbyte data 10 - - years Ta = 85°C, 10k cycles @ 16 Kbyte data 0 0 0 cycles fMCLK = 8 MHz 0 1 1 cycles fMCLK = 16 MHz 1 1.3 2 cycles fMCLK = 32 MHz 2 2.5 3 cycles fMCLK = 48 MHz Erase cycles per page - - 5*104 cycles Total erase cycles - - 2*106 cycles Flash Wait States › Note Note: When Flash is busy, any access to Flash memory or write access to Flash SFRs will be stalled 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 15 Memories Flash and SRAM Performance › Performance of Cortex-M0 @48 MHz › Based on XMC1400 120 100 Flash (prefetched) 80 Flash + SRAM 60 Note: SRAM is too small to run the entire benchmark codes 40 Note: Additional performance can be gathered using the MATH Co-processor 20 0 EEMBC CoreMark (IAR Compiler) Dhrystone (KEIL) Note: higher numbers are better 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 16 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 17 Bus System Peripheral Access Unit (PAU) CPU Cortex-M0 Debug PAU Peripheral Access Unit Flash & BROM SRAM Highlights Allows user application to enable/disable the access to programmable memory locations. Generates a Hard Fault exception when there is an access to a disabled or unassigned address location. Peripherals Key Features Customer Benefits › Protect against unintentional memory access › Safety mechanism for runaway code › Hard Fault exception for invalid access 2015-08-28 › Enter safe state in case of runaway code Copyright © Infineon Technologies AG 2015. All rights reserved. 18 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 19 Interrupt System Highlights System Tick Timer Peripheral Cortex®-M Processor Core NMI IRQs NVIC Peripheral System exceptions Configuration registers Bus Interface Internal bus interconnect The interrupt system consists of the Nested Vectored Interrupt Controller (NVIC) and the interrupt generation blocks in the individual modules. Events from peripherals can be routed via the connection matrix directly to other peripherals and can trigger interrupt requests. Key Features Customer Benefits › 4 programmable priority levels › Flexible priority control › Interrupt Tail-Chaining › Speed up interrupt servicing › Automatic State Saving and Restoring › Low latency exception handling 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 20 Interrupt System 4 Programmable Priority Levels › NVIC supports 32 interrupt nodes › Each interrupt node has an 8-bit priority field (only 2 MSBs are writable) in IPRn (Interrupt Priority Register) › A priority level is assigned to an interrupt node by writing to its corresponding priority field › The lower the value written to the priority field, the higher the priority › A higher priority interrupt can interrupt an existing lower priority interrupt, resulting in nested interrupts › When multiple interrupts have the same priority level, the pending interrupt with the lower node ID takes precedence 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 21 Interrupt System Interrupt Tail-Chaining › When a current ISR is completed and there is a pending interrupt, stack pop is skipped and control is transferred to the new ISR › Allows interrupt servicing to speed up Tail-chaining Source: http://www.arm.com 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 22 Interrupt System Automatic State Saving and Restoring › Automatic state saving and restoring are done without any instruction overhead: › State registers are pushed onto the stack before entering the ISR › Reading of vector table entry is done after the state saving › State registers are popped after exiting the ISR 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 23 Interrupt System Interrupt Latency › Defined as the time from detection of interrupt pulse and latching of interrupt by NVIC, to execution of first instruction in ISR › Typically 21 MCLK cycles › Note: Flash wait states are not considered 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 24 Interrupt System General Module Interrupt Structure › Generates interrupt pulses to NVIC › Independent of status flag level 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 25 Interrupt System Interrupt Node Source Extension › XMC1400 only › For additional flexibility › Each interrupt node can select out of 3 service request sources Selector INTSELx Source A 0 Source B 1 Source C 2 Node x 3 OR gate 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 26 Interrupt System Connection Matrix Connection Matrix CCU 4/8 ADC ADC CCU 4/8 ERU ORC Events GPIO In A In B 80% Logic & Storage Out Triggers GPIO ACMP USIC POSIF NVIC BCCU USIC BCCU › Peripheral outputs can trigger events which are routed to peripheral inputs or to the NVIC › Additional event routing is possible via the Event Request Unit ERU which can store events and logically combine two events › This allows very flexible and powerful system design 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 27 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 28 Clock 4-20M 64 or 96 MHz DCO1 Main Clock Generation 32.768 kHz DCO2 Oscillator Watchdog Clock Selection 32.768k Highlights Clock The main function of the clock system is to generate clock for the CPU and the on-chip peripherals. An oscillator watchdog monitors the frequencies of the two on-chip oscillators. Peripheral clock can run at twice the speed of CPU clock. Key Features Customer Benefits › Oscillator Watchdog › Safely shut down system during loss of clock › Individual Peripheral Clock Gating › Oscillator Frequency Calibration by Hardware/Software › Optimized overall current consumption › Improved clock accuracy 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 29 Clock Clock Generation › Up to 96 MHz peripheral clock › Up to 48 MHz CPU clock XMC1400 only Main onchip Oscillator (DC01) 8-96MHz 4-20M 32.768k TRIM High Freq Osc Pads Low Freq Osc Pads 32.768k *2 . Blank Fract Div PCLK :2 up to 96MHz - CCU POSIF BCCU MATH - CPU TRIM MCLK - rest of periph . up to 48MHz ACMPx ERU0 CAN . RTC Auxiliary on- chip Oscillator (DCO2) 2015-08-28 32. 768kHz WDT XMC1400 only Copyright © Infineon Technologies AG 2015. All rights reserved. 30 Clock Oscillator Frequency Calibration (1/3) › XMC1400 only › Accurate peripheral and main clock achieved by calibrating DCO1 with external crystal › This is an automatic process › Low-frequency pads (32.768 kHz) › RTC › Automatic DCO1 calibration › High-frequency pads (4-20 MHz) › Direct jitter-free clock for CAN › Automatic DCO1 calibration 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 31 Clock Oscillator Frequency Calibration (2/3) › Software adjustment based on die temperature (DCO1) › Runtime calibration with on-chip die temperature sensor (DTS) › The offset is calculated using formulae and values stored in the flash configuration sector › Improved clock accuracy 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 32 Clock Oscillator Frequency Calibration (3/3) › Fractional Divider adjustment based on external reference › External frequency captured by Capture Compare Unit 4 (CCU4) › Discrete oscillator circuit with on-chip comparator 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 33 Clock Clock Blanking (1/2) › XMC1000 microcontrollers don’t require a VDDC buffer capacitor › Stable core voltage during load changes is guaranteed by clock blanking › During clock blanking, main clock (MCLK) and peripheral clock (PCLK) freeze for a few clock cycles to guarantee system stability and avoid brown-out reset › Clock blanking may occur if there is a significant load increase (more than ~300 %) › Several peripherals are enabled at the same time (typically at startup) › Sudden significant increase in main and peripheral clock frequency (typically at startup) › Wakeup from deep sleep › Does not occur during normal runtime operation 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 34 Clock Clock Blanking (2/2) › Clock blanking can be avoided if › Peripherals are enabled one at a time › Clock frequency is increased in steps (e.g. 2 MHz 8 MHz 32 MHz) › Clock frequency is decreased to 125 kHz and all peripherals are disabled before entering sleep › If clock blanking happens › Wait 15 usec before increasing the load again to prevent further drop in the core voltage › Status bit CLKCR.VDDC2LOW indicates stabilized core voltage › Clock blanking can be monitored externally on P0.1 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 35 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 36 Reset Highlights Reset Master Reset System Reset Always ensure safe application state via on-chip reset generation. Full user control via reset event signals and software control. Key Features Customer Benefits › Master reset › Safe operating conditions and defined system state after poweron/brownout › Fail safe mechanisms › Reset brings the system into safe operation 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 37 Reset Reset Overview PADs Debug SFRs PAD control ensures defined pad state Core SFRs RAMs All RAM undefined after Poweron and unmodified with any Reset E.g. CPU, Clock, Timer, ADC, Comm, Flash, Port logic DAP & M 0 debug system EVR VDDP & VDDC supervisory Power- on or Brownout Debugger not connected Master Reset Software via setting bit RSTCON.MR STEN Software via setting bit AIRCR.SYSR ESETREQ 2015-08-28 Lockup CPU lockup mechanism System Reset Watchdog Timer via WDT overflow Copyright © Infineon Technologies AG 2015. All rights reserved. RAM Error via parity error in volatile memory Flash Error via doublebit ECC error in Flash memory 38 Reset Master Reset › Supply voltage (1.8-5.5 V) and core voltage monitoring PADs PAD control ensures defined pad state › Upon power-on › Upon VDDP/VDDC undervoltage (brownout) › Or triggered by software › Complete device reset EVR VDDP & VDDC supervisory Power- on or Brownout Software via setting bit RSTCON.MR STEN 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. Master Reset 39 Reset Fail safe mechanisms Watchdog Timer via WDT overflow › RAM parity error detection › Optional system reset in case of parity error › Flash ECC error detection › Optional system reset in case of double-bit ECC error Flash Error via ECC error in Flash memory › Lockup reset › Standard ARM CPU feature › Optional reset in case of unrecoverable CPU states RAM Error via parity error in volatile memory › Watchdog Timer reset › Watchdog reset generated if CPU is not responsive › Watchdog reset can be avoided with optional pre-warning EVR Lockup VDDP & VDDC supervisory CPU lockup mechanism Master Reset System Reset › VDDP or VDDC low pre-warning interrupts › Prepare system for clock blanking or imminent brownout reset 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 40 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 41 Power Highlights Power 1.8-5.5 V EVR Pads CPU clocks memories logic A power supply of 1.8 V to 5.5 V is needed via the power supply pin pair (VDD, VSS). The core supply for the CPU, memories and most of the peripherals is generated by the EVR. Key Features Customer Benefits › Different power saving modes › Scalable power consumption according to application use case › Fail safe functionality › Can be used in a wide range of designs with a wide range of components › Power monitoring and validation › Very wide supply voltage range of 1.8-5.5 V 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 42 Power Different power saving modes (1/2) › Simple transition scheme › Both power saving states entered from Active state › Active – Sleep › Active – Deep Sleep › Power saving states entered with a single request › Sleep and Deep Sleep entered via CPU instruction Mode 2015-08-28 Recovery Active - Clock scaling - Disable selected peripherals by clock gating - Flash on/off - Full SW control Sleep - CPU stopped - Wakeup via interrupt - Automatic restoration Deep Sleep - CPU stopped - Main oscillator (DCO1) stopped - Wakeup via interrupt - Automatic restoration › Flexible Wake-up trigger › One wake-up trigger source can serve different power saving modes Power Saving Copyright © Infineon Technologies AG 2015. All rights reserved. 43 Power Different power saving modes (2/2) Typical current consumption [mA] XMC1300 › Low active current › Current consumption depends on clock frequency and enabled peripherals XMC Family Typical [mA] Worst case [mA] XMC1100 8.4 11 XMC1200 8.8 11.5 XMC1300 9.2 12 XMC1400 23 25 9.2 10 6.6 4 1.2 0 All on @ 64/32 MHz CPU off @ 64/32 MHz All on @ 1/1 MHz All off @ 1/1 MHz Deep Sleep Major current contributors [mA] XMC1300 6 5.04 3.4 4 2 0 2015-08-28 0.24 Base Load Copyright © Infineon Technologies AG 2015. All rights reserved. ADC 0.87 0.94 USIC CCU4 44 Power Power Monitoring and Validation › Pad domain power monitoring › Core domain power validation › Supply voltage VDDP › Core voltage VDDC › Pre-warning when VDDP < VDDPPW › Warning when VDDC > VCLIP › Brownout reset when VDDP < VDDPBO › Warning & clock blanking when VDDC < VDROP › Brownout reset when VDDC < VDDCBO Safe power up and down with automatic internal reset handling (release & issue) VDDP brownout reset pre-warning VDDP warning VDDC VCLIP VDROP VDDCBO VDDPPW VDDPBO EVR VDDC brownout reset clock blanking clock t 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. t 45 Power Voltage Detectors › Supply Voltage (VDDP) Monitoring › External Voltage Detector, VDEL › External Brownout Detector, BDE › Core voltage (VDDC) Monitoring › VDDC Brownout Detector › VDROP Detector › Monitor lower limits of the core voltage › VCLIP Detector › Monitor upper limits of the core voltage 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 46 Power, Reset and Clock Start-Up Sequence Hardware Controlled Startup Phase Power-Up System Reset Release Startup Software ( SSW) Execution Configuration of System Functions Configuration of Clock System and Miscellaneous Functions Initialization Completed Start of Application Software Controlled Startup Phase 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 47 Agenda 1 XMC1000 and ARM® Cortex®-M0 2 Memories 3 Bus System 4 Interrupt System 5 Clock 6 Reset 7 Power 8 Ports 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 48 Ports Highlights PORT slice Control interface The Ports module provides a generic and flexible interface to the microcontroller. Pad Control PU Signal interface PIN PD Key Features Customer Benefits › Flexible function mapping › High-current pins › Very wide supply voltage range of 1.8-5.5 V › 2015-08-28 › › Up to 13 input / 11 output functions per pin, special functions (e.g. DAC) Driverless MOSFET switching, signaling LED control without external transistor Can be used in a wide range of designs with a wide range of components Copyright © Infineon Technologies AG 2015. All rights reserved. 49 Ports Flexible Function Mapping › Up to 12 input / 9 output functions per pin › Adjustable pad properties › Input / output › Push-pull / open drain › Pull-up / pull-down / tristate › Power save › Adjustable pad hysteresis › Direct control by peripherals › Analog reference generation by › pull-up/pull-down control › using a switching signal XMC1000 + ACMP - 2015-08-28 measured analog signal Px.z adjustable analog reference VDDP Port/Pad R › Quad SPI functionality without › software overhead › LED matrix control without › software overhead Px.y R C BCCU channel or CCU 4 slice Copyright © Infineon Technologies AG 2015. All rights reserved. 50 Ports High-Current Pins › Certain P1.x pins only › Sink up to 50 mA › Direct drive multiple LEDs in a common cathode configuration › Fast MOSFET turn-off without external driver XMC1000 Px.x Px.x XMC1000 Px.x P1.x P1.x 2015-08-28 Copyright © Infineon Technologies AG 2015. All rights reserved. 51 Support material: Collaterals and Brochures › › › › › Product Briefs Selection Guides Application Brochures Presentations Press Releases, Ads › www.infineon.com/XMC Technical Material › › › › › Application Notes Technical Articles Simulation Models Datasheets, MCDS Files PCB Design Data › › › › www.infineon.com/XMC Kits and Boards DAVETM Software and Tool Ecosystem Videos › Technical Videos › Product Information Videos › Infineon Media Center › XMC Mediathek Contact › Forums › Product Support › Infineon Forums › Technical Assistance Center (TAC) Copyright © Infineon Technologies AG 2016. All rights reserved. 52 Disclaimer The information given in this training materials is given as a hint for the implementation of the Infineon Technologies component only and shall not be regarded as any description or warranty of a certain functionality, condition or quality of the Infineon Technologies component. Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind (including without limitation warranties of noninfringement of intellectual property rights of any third party) with respect to any and all information given in this training material. All the images used in the trainings are free for commercial use or free for use with attribution and were designed by Freepik.