A8286 Datasheet

A8286
Dual LNB Supply and Control Voltage Regulator
Features and Benefits
Description
▪ 2-wire serial I2C™ -compatible interface: control (write)
and status (read)
▪ LNB voltages (16 programmable levels) compatible with
all common standards
▪ Tracking switch-mode power converter for lowest dissipation
▪ Integrated converter switches and current sensing
▪ Output current limit of 900 mA typical, with 48 ms timer
▪ Static current limit circuit allows full current at startup and
13→18 V output transition; reliably starts wide load range
▪ Push-pull output stage minimizes 13→18 V and 18→13 V
output transition times for highly capacitive loads
▪ Adjustable rise/fall time via external timing capacitor
▪ Built-in tone oscillator, factory-trimmed to 22 kHz
facilitates DiSEqC™ tone encoding, even at no-load
▪ Four methods of 22 kHz tone generation, via I2C™ data
bits and/or external pin
▪ 22 kHz tone detector facilitates DiSEqC™ 2.0 decoding
▪ Diagnostics for output voltage level, input supply UVLO,
and DiSEqC™ tone output
▪ Cable disconnect diagnostic
▪ Auxiliary modulation input
▪ LNB overcurrent with timer
Intended for analog and digital satellite receivers, this dual
low-noise block converter regulator (LNBR) is a monolithic
linear and switching voltage regulator, specifically designed to
provide the power and the interface signals to two LNB down
converters via coaxial cables. The A8286 requires few external
components, with the boost switches and compensation circuitry
integrated inside of the device. A high switching frequency is
chosen to minimize the size of the passive filtering components,
further assisting in cost reduction. The high level of component
integration ensures extremely low noise and ripple figures.
The A8286 has been designed for high efficiency, utilizing
the Allegro™ advanced BCD process. The integrated boost
switches have been optimized to minimize both switching and
static losses. To further enhance efficiency, the voltage drop
across the tracking regulators has been minimized.
The A8286 has integrated tone detection capability, to support
full two-way DiSEqC™ communications. Several schemes
are available for generating tone signals, all the way down
to no-load, and using either the internal clock or an external
time source.
Package: 28-pin QFN (suffix ET)
Continued on the next page…
5 mm × 5 mm
(Not to scale)
Functional Block Diagram
VS
A
C2
100 MF
Channel 1
L1
33 MH
VDD
B
R8-C11 network is needed only when high
inductive load is applied, such as ProBrand LNB.
C
D3 and D4 are used for surge protection.
D
Either C12 or C9 should be used, but not both.
LX1
GNDLX1
BOOST1
VCP1
D3
C
A8286
Charge
Pump
VIN
C1
100 nF
VREG
TMode1
EXTM1
Regulator
Fsw
DAC
R2
R3
LNB
Voltage
Control
Wave
Shape
I2 C
Compatible
Interface
Fault Monitor
OCP1
OCP2
PNG1
PNG2
TSD
VUV
C8
D2 220 nF
L2
220 MH
R8
30 7
Fsw
TCAP1
Clock
Divider 22 kHz
C7
22 nF
Oscillator
C11
0.68 MF
B
TDO1
Tone
Detect
IRQ
PAD
VOUT1
LNB1
Linear
Stage
TGate1
SDA
GND
D
R6
157
VPump
TCAP1
R1
SCL
C12
Boost
Converter
C3
220 nF
8286-DS, Rev. 17
C4
100 nF
R5
TDO1 EXTM1
Channel 1 of 2 channels shown.
C6
1 MF
C5
100 MF
R4
A
L3
1 MH
D1
TDI1
R7
100 7
C10
10 nF
C9
220 nF
D
C13
10 nF
D4
C
A8286
Dual LNB Supply and Control Voltage Regulator
Description (continued)
A comprehensive set of fault registers are provided which, comply
with all the common standards, including: overcurrent, thermal
shutdown, undervoltage, cable disconnect, power not good, and
tone detect.
The device uses a 2-wire bidirectional serial interface, compatible
with the I2C™ standard, that operates up to 400 kHz.
The A8286 is supplied in a lead (Pb) free 28-lead
MLP/QFN with 100% matte tin leadframe.
Absolute Maximum Ratings
Rating
Units
Load Supply Voltage, VIN pin
Characteristic
Symbol
VIN
Conditions
30
V
Output Current1
IOUT
Internally
Limited
A
–0.3 to 33
V
–1 to 33
V
–0.3 to 30
V
–0.3 to 41
V
Logic Input Voltage, EXTM pin
–0.3 to 5
V
Logic Input Voltage, other pins
–0.3 to 7
V
Logic Output Voltage
–0.3 to 7
V
Output Voltage, BOOST pin
Surge2
Output Voltage, LNB pin
Output Voltage, LX pin
Output Voltage, VCP pin
VCP
Operating Ambient Temperature
TA
–20 to 85
°C
Junction Temperature
TJ(max)
150
°C
Storage Temperature
Tstg
–55 to 150
°C
1Output
current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150°C.
2Use Allegro recommended Application circuit.
Package Thermal Characteristics*
Package
RθJA
(°C/W)
PCB
ET
32
4-layer
* Additional information is available on the Allegro website.
Ordering Information
Use the following complete part numbers when ordering:
Part Number
Packinga
Description
A8286SETTR-Tb
7-in. reel, 1500 pieces/reel
12 mm carrier tape
ET package, MLP surface mount
aContact Allegro
bLeadframe
for additional packing options.
plating 100% matte tin.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A8286
Dual LNB Supply and Control Voltage Regulator
22 LNB2
23 GNDLX2
24 LX2
25 VIN
26 LX1
27 GNDLX1
28 LNB1
Device Pin-out Diagram
BOOST1
1
21 BOOST2
VCP1
2
20 VCP2
TCAP1
3
NC
4
TDO1
5
17 TDO2
EXTM1
6
16 EXTM2
TDI1
7
15 TDI2
19 TCAP2
18 NC
IRQ 14
NC 13
12
SCL
ADD 11
9
SDA 10
8
GND
VREG
PAD
(Top View)
Terminal List Table
Name
Number
Function
GND
–
Fused internally; connect to ground plane for thermal dissipation
ADD
11
Address select
BOOST1
1
Tracking supply voltage to linear regulator (channel 1)
BOOST2
21
Tracking supply voltage to linear regulator (channel 2)
EXTM1
6
External modulation input (channel 1)
EXTM2
16
External modulation input (channel 2)
GND
8
PAD
Pad
Signal ground
GNDLX1
27
Boost switch ground (channel 1)
GNDLX2
23
Boost switch ground (channel 2)
IRQ
14
Interrupt request
LNB1
28
Output voltage to LNB (channel 1)
LNB2
22
Output voltage to LNB (channel 2)
LX1
26
Inductor drive point (channel 1)
LX2
24
Inductor drive point (channel 2)
NC
4, 13, 18
SCL
12
I2C™-compatible clock input
SDA
10
I2C™-compatible data input/output
Exposed thermal pad; connect to ground plane
No connection
TCAP1
3
Capacitor for setting the rise and fall time of the LNB output (channel 1)
TCAP2
19
Capacitor for setting the rise and fall time of the LNB output (channel 2)
TDI1
7
Tone detect input (channel 1)
TDI2
15
Tone detect input (channel 2)
TDO1
5
Tone detect output (channel 1)
TDO2
17
Tone detect output (channel 2)
VCP1
2
Gate supply voltage (channel 1)
VCP2
20
Gate supply voltage (channel 2)
VIN
25
Supply input voltage
VREG
9
Analog supply
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A8286
Dual LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Relative to selected VLNB target level,
ILOAD = 0 to 500 mA
–3
–
3
%
IIN(Off)
ENB bit = 0, LNB output disabled, VIN = 12 V
–
–
12.0
mA
IIN(On)
ENB bit = 1, LNB output enabled, ILOAD = 0
mA, VIN = 12 V
–
–
20.0
mA
General
Set-Point Accuracy, Load and Line Regulation
Supply Current
Boost Switch On Resistance
Err
RDS(on)BOOST ILOAD = 500 mA
Switching Frequency
fSW
Switch Current Limit
ILIMSW
VIN = 10 V, VOUT = 20.3 V
∆VREG
VBOOST – VLNB, no tone signal,
ILOAD = 500 mA
ICHG
TCAP capacitor (C7) charging
Linear Regulator Voltage Drop
TCAP Pin Current
–
300
600
mΩ
320
352
384
kHz
–
3.8
–
A
600
800
1000
mV
–12.5
–10
–7.5
μA
IDISCHG
TCAP capacitor (C7) discharging
7.5
10
12.5
μA
Output Voltage Rise Time2
tr(VLNB)
For VLNB 13 → 18 V; CTCAP = 5.6 nF,
ILOAD = 500 mA
–
500
–
μs
Output Voltage Pull-Down Time2
tf(VLNB)
For VLNB 18 → 13 V; CLOAD = 100 μF,
ILOAD = 0 mA
–
12.5
–
ms
IRLNB
ENB bit = 0, VLNB = 33 V , BOOST capacitor
(C5) fully charged
–
1
5
mA
Vrip,n(pp)
20 MHz BWL; reference circuit shown in
Functional Block diagram; contact Allegro for
additional information on application circuit
board design
–
30
–
mVPP
Output Overcurrent Limit4
ILIMLNB
VBOOST – VLNB = 800 mV
Overcurrent Disable Time
tDIS
Output Reverse Current
Ripple and Noise on LNB Output3
Protection Circuitry
800
900
1000
mA
40.0
48
56.0
ms
V
VIN Undervoltage Lockout Threshold
VUVLO
VIN falling
7.05
7.35
7.65
VIN Turn On Threshold
VIN(th)
VIN rising
7.40
7.70
8.00
V
VUVLOHYS
–
350
–
mV
Thermal Shutdown Threshold2
TJ
–
165
–
°C
Thermal Shutdown Hysteresis2
∆TJ
–
20
–
°C
Undervoltage Hysteresis
Power Not Good Flag Set
PNGSET
With respect to VLNB
77
85
93
%
Power Not Good Flag Reset
PNGRESET
With respect to VLNB
82
90
98
%
Power Not Good Hysteresis
PNGHYS
With respect to VLNB
–
5
–
%
22.0
22.8
23.5
V
20.16
21.00
21.84
V
1.0
1.75
2.5
mA
Cable Disconnect Boost Voltage
VCAD
Cable Disconnect Set
VCADSET
Cable Disconnect Current Source
ICADSRC
CADT bit = 1, ENB bit = 1, VSEL0 through
VSEL3 = 1
VLNB = 21.00 V, VBOOST = 22.8 V
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A8286
Dual LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Tone
20
22
24
kHz
Tone Amplitude, Peak-to-Peak
VTONE(pp)
ILOAD = 0 to 500 mA, CLOAD = 750 nF
400
620
800
mV
Tone Duty Cycle
DCTONE
ILOAD = 0 to 500 mA, CLOAD = 750 nF
40
50
60
%
Tone Rise Time
trTONE
ILOAD = 0 to 500 mA, CLOAD = 750 nF
5
10
15
μs
tfTONE
ILOAD = 0 to 500 mA, CLOAD = 750 nF
Tone Frequency
Tone Fall Time
EXTM Logic Input
EXTM Input Leakage
fTONE
5
10
15
μs
VEXTM(H)
2.0
–
–
V
VEXTM(L)
–
–
0.8
V
IEXTMLKG
–1
–
1
μA
fTONE = 22 kHz sine wave, TMODE = 0
300
–
–
mV
VTDT(pp)Int
fTONE = 22 kHz sine wave, using internal tone
(options 1 and 2, in figure 2)
400
–
–
mV
VTDT(pp)Ext
fTONE = 22 kHz sine wave, using external
tone (options 3 and 4, in figure 2)
300
–
–
mV
–
–
100
mV
17.6
–
26.4
kHz
–
8.6
–
kΩ
Tone Detector
Tone Detect Input Amplitude Receive, Peak-toPeak
Tone Detect Input Amplitude Transmit, Peakto-Peak
Tone Reject Input Amplitude, Peak-to-Peak
VTDR(pp)
VTRI(pp)
Frequency Capture
fTDI
Input Impedance2
ZTDI
fTONE = 22 kHz sine wave
600 mVpp sine wave
TDO Output Voltage
VTDO(L)
Tone present, ILOAD = 3 mA
–
–
0.4
V
TDO Output Leakage
ITDOLKG
Tone absent, VTDO = 7 V
–
–
10
μA
VSCL(L)
–
–
0.8
V
Logic Input (SDA,SCL) High Level
VSCL(H)
2.0
–
–
V
Logic Input Hysteresis
VI2CIHYS
–
150
–
mV
–10
<±1.0
10
μA
–
–
0.4
V
I2C™-Compatible Interface
Logic Input (SDA,SCL) Low Level
Logic Input Current
II2CI
Logic Output Voltage SDA and IRQ
Vt2COut(L)
Logic Output Leakage SDA and IRQ
Vt2CLKG
SCL Clock Frequency
Output Fall Time
VI2CI = 0 to 7 V
ILOAD = 3 mA
Vt2COut = 0 to 7 V
fCLK
tfI2COut
–
10
μA
–
400
kHz
–
–
250
ns
tBUF
1.3
–
–
μs
Hold Time Start Condition
tHD:STA
0.6
–
–
μs
Setup Time for Start Condition
tSU:STA
0.6
–
–
μs
Bus Free Time Between Stop/Start
Vt2COut(H) to Vt2COut(L)
–
–
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
A8286
Dual LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
I2C™-Compatible Interface (continued)
SCL Low Time
tLOW
1.3
–
–
μs
SCL High Time
tHIGH
0.6
–
–
μs
100
–
–
ns
0
–
900
ns
0.6
–
–
μs
Data Setup Time
tSU:DAT
Data Hold Time
tHD:DAT
Setup Time for Stop Condition
tSU:STO
For tHD:DAT(min) , the master device must
provide a hold time of at least 300 ns for the
SDA signal in order to bridge the undefined
region of the SCL signal falling edge
I2C™ Address Setting
ADD Voltage for Address 0001,000
Address1
0
–
0.7
V
ADD Voltage for Address 0001,001
Address2
1.3
–
1.7
V
ADD Voltage for Address 0001,010
Address3
2.3
–
2.7
V
ADD Voltage for Address 0001,011
Address4
3.3
–
5.0
V
1Operation
at 16 V may be limited by power loss in the linear regulator.
by worst case process simulations and system characterization. Not production tested.
3LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layout
recommendations. Not production tested.
4Current from the LNB output may be limited by the choice of Boost components.
2Guaranteed
I2C™ Interface Timing Diagram
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
SDA
SCL
tLOW
tHIGH
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A8286
Dual LNB Supply and Control Voltage Regulator
Functional Description
Protection
The A8286 has a wide range of protection features and fault diagnostics which are detailed in the Status Register section.
Boost Converter/Linear Regulator
Each channel contains a tracking current-mode boost converter
and linear regulator. The boost converter tracks the requested
LNB voltage to within 800 mV, to minimize power dissipation.
Under conditions where the input voltage, VBOOST , is greater than
the output voltage, VLNB, the linear regulator must drop the differential voltage. When operating in these conditions, care must
be taken to ensure that the safe operating temperature range of the
A8286 is not exceeded.
The A8286 has internal pulse-by-pulse current limit on the boost
converter, and DC current limiting on the LNB output, to protect
the IC against short circuits. When the LNB output is shorted, the
LNB output current is limited to 900 mA typical, and the IC will
be shut down if the overcurrent condition lasts for more than 48
ms. If this occurs, the A8286 must be re-enabled for normal operation. The system should provide sufficient time between successive
restarts to limit internal power dissipation; a period of 5 s is recommended.
Each of the boost converters operates at 352 kHz typical:
16 times the internal 22 kHz tone frequency. All the loop compensation, current sensing, and slope compensation functions are provided internally.
At extremely light loads, and the boost converters operate in
a pulse-skipping mode. Pulse skipping occurs when the BOOST
voltage rises to approximately 450 mV above the BOOST target
output voltage. Pulse skipping stops when the BOOST voltage
drops 200 mV below the pulse skipping level.
In the case that two or more set top box LNB outputs are connected together by the customer (e.g., with a splitter), it is possible
that one output could be programmed at a higher voltage than the
other. This would cause a voltage on one output that is higher than
its programmed voltage (e.g., 19 V on the output of a 13 V programmed voltage). The output with the highest voltage will effectively turn off the other outputs. As soon as this voltage is reduced
below the value of the other outputs, the A8286 output will autorecover to their programmed levels.
Charge Pump. Each generates a supply voltage above the internal
tracking regulator output to drive the linear regulator control.
Slew Rate Control. During either start-up, or when the output
voltage at the LNB pin is transitioning, the output voltage rise and
fall times can be set by the value of the capacitor connected from
the TCAP1 pin to GND (CTCAP or C7 in the Applications Schematic). Note that during start-up, the BOOST pin is pre-charged to
the input voltage minus a voltage drop. As a result, the slew rate
control for the BOOST pin occurs from this voltage.
The value of CTCAP can be calculated using the following formula:
CTCAP = (ITCAP × 6) / SR ,
where SR is the required slew rate of the LNB output voltage,
in V/s, and ITCAP is the TCAP pin current specified in the datasheet. The recommended value for CTCAP, 10 nF, should provide
satisfactory operation for most applications. However, in some
cases, it may be necessary to increase the value of CTCAP to avoid
activating the current limit of the LNB output.
One such situation is when two set-top boxes are connected in
parallel. If this is the case, the following formula can be used to
calculate a larger value for CTCAP:
CTCAP ≥ (ITCAP × 6)(2 × CBOOST) / ILIMLNB ,
CTCAP ≥ (10 μA × 6)(2 × 100 μF) / 800 mA = 15 nF .
The minimum value of CTCAP is 2.2nF. There is no theoretical
maximum value of CTCAP , however, too large a value will probably cause the voltage transition specifications to be exceeded. Tone
generation is unaffected by the value of CTCAP.
Pull-Down Rate Control. In applications that have to operate at
very light loads and that require large load capacitances (in the
order of tens to hundreds of microfarads), the output linear stage
provides approximately 40 mA of pull-down capability. This
ensures that the output volts are ramped from 18 V to 13 V in a
reasonable amount of time.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
A8286
Dual LNB Supply and Control Voltage Regulator
ODT (Overcurrent Disable Time)
If the LNB output current exceeds 900 mA typical, for more than
48 ms, then the LNB output will be disabled and the OCP bit will
be set.
DC current
The A8286 can handle up to 700 mA per channel individually,
or 950 mA to both channels simultaneously, during continuous
operation.
Short Circuit Handling
Tone Detection
If the LNB output is shorted to ground, the LNB output current
will be clamped to 900 mA, typical. If the short circuit condition
lasts for more than 48 ms, the A8286 will be disabled and the
OCP bit will be set.
A 22 kHz tone detector is provided in each channel of the A8286
solution. The detector extracts the tone signal and provides it as
an open-drain signal on the TDO pins. The maximum tone out
error is ±1 tone cycle, and the maximum tone out delay with
respect to the input is 1 tone cycle. Detection thresholds are given
in table 1.
Auto-Restart
After a short circuit condition occurs, the host controller should
periodically re-enable the A8286 to check if the short circuit has
been removed. Consecutive startup attempts should allow at least
5 s of delay between restarts.
Table 1. Detection Thresholds for Tone Generation Options
Transmit
Option
(Fig. 1)
In-rush Current
At start-up or during an LNB reconfiguration event, a transient surge current above the normal DC operating level can be
provided by the A8286. This current increase can be as high as
900 mA, typical, for as long as required, up to a maximum of
48 ms.
1
2
TMODE
1
TGATE
Control
0/1
Receive
3
4
n.a.
n.a.
1
0
0
0
1
1
Control
0/1
1
22 kHz
Control
logic
0/1
signal,
continuous
Control
gated
22 kHz
logic
signal
At least one
must be 0 to
prevent tone
transmission
EXTM
1
Guaranteed
Detection
Threshold
(mVPP)
400
400
300
300
300
400
Rejection
Threshold
(mVPP)
100
100
100
100
100
100
ODT (Overcurrent Disable Timing) Mode Timing Diagram
+A
900 mA, typ.
per channel
IOUT(LNBX),
per channel
700 mA for one channel,
and 1.1 A total current
650 mA for one channel,
and 950 mA total current
Safe Operating Area
0
t
≤ tDIS
2000 ms
Start-up
≤ tDIS
≤ tDIS
Continuous Operation
Continuous Operation
LNB
Reconfiguration
Short
Circuit
Figure 1. ODT (Overcurrent Disable Timing) Mode Timing Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A8286
Dual LNB Supply and Control Voltage Regulator
Tone Generation
The A8286 solution offers four options for tone generation,
providing maximum flexibility to cover every application. The
EXTM pins (external modulation), in conjunction with the I2C™
control bits: TMODE (tone modulation) and TGATE (tone gate),
provide the necessary control. The TMODE bit controls whether
the tone source is either internal or external (via the EXTM pin).
EXTM
TMODE
TGATE
I2C™-Compatible Interface
Tone
(LNB Ref)
LNB (V)
Option 1 – Use internal tone, gated by the TGATE bit.
EXTM
TMODE
TGATE
Tone
(LNB Ref)
LNB (V)
Option 2 – Use internal tone, gated by the EXTM pin.
EXTM
TMODE
TGATE
Tone
(LNB Ref)
LNB (V)
Option 3 – Use external tone, gated by the TGATE bit.
EXTM
TMODE
TGATE
Tone
(LNB Ref)
Option 4 – Use external tone.
Figure 2. Options for tone generation
Both the EXTM pin and TGATE bit determine the 22 kHz control, whether gated or clocked.
Four options for tone generation are shown in figure 2. Note
that when using option 4, when EXTM stops clocking, the LNB
volts park at the LNB voltage, either plus or minus half the tone
signal amplitude, depending on the state of EXTM. For example,
if the EXTM is held low, the LNB DC voltage is the LNB programmed voltage minus 325 mV (typical).
With any of the four options, when a tone signal is generated,
TDET is set in the status register. When the internal tone is used
(options 1 or 2), the minimum tone detect amplitude is 400 mV,
and when an external tone is used (options 3 or 4), the minimum
tone detection amplitude is 300 mV.
LNB (V)
This is a serial interface that uses two bus lines, SCL and SDA,
to access the internal Control and Status registers of the A8286.
Data is exchanged between a microcontroller (master) and the
A8286 (slave). The clock input to SCL is generated by the master,
while SDA functions as either an input or an open drain output,
depending on the direction of the data.
Timing Considerations
The control sequence of the communication through the I2C™compatible interface is composed of several steps in sequence:
1. Start Condition. Defined by a negative edge on the SDA line,
while SCL is high.
2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1)
or write (0), and an acknowledge bit. The first five bits of the
address are fixed as: 00010. The four optional addresses, defined by the remaining two bits, are selected by the ADD input.
The address is transmitted MSB first.
3. Data Cycles.
Write – 6 bits of data and 2 bits for addressing four internal
control registers, followed by an acknowledge bit. See Control
Register section for more information.
Read – Two status registers, where register 1 is read first,
followed by register 2, then register 1, and so on. At the start
of any read sequence, register 1 is always read first. Data is
transmitted MSB first.
4. Stop Condition. Defined by a positive edge on the SDA line,
while SCL is high. Except to indicate a Start or Stop condition, SDA must be stable while the clock is high. SDA can
only be changed while SCL is low. It is possible for the Start or
Stop condition to occur at any time during a data transfer. The
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9
A8286
Dual LNB Supply and Control Voltage Regulator
indicate that the data has been successfully received. In both cases,
the master device must release the SDA line before the ninth clock
cycle, in order to allow this handshaking to occur.
During a data read, the A8286 acknowledges the address in the
same way as in the data write sequence, and then retains control
of the SDA line and send the data from register 1 to the master.
On completion of the eight data bits, the A8286 releases the SDA
line before the ninth clock cycle, in order to allow the master to
acknowledge the data. If the master holds the SDA line low during this Acknowledge bit, the A8286 responds by sending the data
from register 2 to the master. Data bytes continue to be sent to the
master until the master releases the SDA line during the Acknowledge bit. When this is detected, the A8286 stops sending data and
waits for a stop signal.
A8286 always responds by resetting the data transfer sequence.
The Read/Write bit is used to determine the data transfer direction. If the Read/Write bit is high, the master reads the contents of
register 1, followed by register 2 if a further read is performed. If
the Read/Write bit is low, the master writes data to one of the four
Control registers. Note that multiple writes are not permitted. All
write operations must be preceded with the address.
The Acknowledge bit has two functions. It is used by the master
to determine if the slave device is responding to its address and
data, and it is used by the slave when the master is reading data
back from the slave. When the A8286 decodes the 7-bit address
field as a valid address, it responds by pulling SDA low during the
ninth clock cycle.
During a data write from the master, the A8286 also pulls SDA
low during the clock cycle that follows the data byte, in order to
acknowledge
from LNBR
Start
Address
acknowledge
from LNBR
W
Control Data
SDA
0
0
0
1
0
A1
A0
0
AK
SCL
1
2
3
4
5
6
7
8
9
I1
I0
D5
D4
D3
Stop
D2
D1
D0
AK
Write to Register
acknowledge
from LNBR
Start
Address
no acknowledge
from master
R
Status Register 1
SDA
0
0
0
1
0
A1
A0
1
AK
SCL
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
Stop
D1
D0 NAK
Read One Byte from Register
acknowledge
from LNBR
Start
Address
R
acknowledge
from LNBR
Status Data in Register 1
SDA
0
0
0
1
0
A1
A0
1
AK
SCL
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
no acknowledge
from master
Status Data in Register 2
D0
AK
-
-
-
-
D3
D2
D1
Stop
D0 NAK
Read Multiple Bytes from Register
Figure 3. I2C™ Interface. Read and write sequences.
10
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A8286
Dual LNB Supply and Control Voltage Regulator
or due to a fault, or is enabled.
When the master recognizes an interrupt, it addresses all slaves
connected to the interrupt line in sequence, and then reads the
status register to determine which device is requesting attention.
The A8286 latches all conditions in the Status register until the
completion of the data read. The action at the resampling point is
further defined in the Status Register section. The bits in the Status register are defined such that the all-zero condition indicates
that the A8286 is fully active with no fault conditions.
When VIN is initially applied, the I2C™-compatible interface
does not respond to any requests until the internal logic supply
VREG has reached its operating level. Once VREG has reached this
point, the IRQ output goes active, and the VUV bit is set. After the
A8286 acknowledges the address, the IRQ flag is reset. After the
master reads the status registers, the registers are updated with the
VUV reset.
Interrupt Request
The A8286 also provides an interrupt request pin, IRQ, which
is an open-drain, active-low output. This output may be connected
to a common IRQ line with a suitable external pull-up and can
be used with other I2C™-compatible devices to request attention
from the master controller.
The IRQ output becomes active when either the A8286 first
recognizes a fault condition, or at power-on, when the main supply, VIN , and the internal logic supply, VREG , reach the correct
operating conditions. It is only reset to inactive when the I2C™
master addresses the A8286 with the Read/Write bit set (causing a
read). Fault conditions are indicated by the TSD, VUV, and OCP
bits and are latched in the Status register. See the Status register
section for full description.
The DIS, PNG, CAD and TDET status bits do not cause an interrupt. All these bits are continually updated, apart from the DIS
bit, which changes when the LNB is either disabled, intentionally
Start
Address
R
Status Register 1
SDA
0
0
0
1
0
A1
A0
1
AK
SCL
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
Stop
D1
D0 NAK
IRQ
Fault
Event
Read after Interrupt
Reload
Status Register
Figure 4. I2C™ Interface. Read sequences after interrupt request.
11
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A8286
Dual LNB Supply and Control Voltage Regulator
Control Registers (I2C™-Compatible Write Register)
All main functions of the A8286 are controlled through the
I2C™-compatible interface via the 8-bit Control registers. As the
A8286 contains numerous control options, as well as featuring
two channels, it is necessary to have four Control registers. Each
register contains up to 6 bits of data (bit 0 to bit 5), followed by
2 bits for the register address (bit 6 and bit 7). The power-up
states for the control functions are all 0s.
The following tables define the control bits for each address
and the settings for output voltage:
Table 2. Control Registers with Address (I1, I0) = 00 and 01
Name
Bit
Channel 1
(Address: I1, I0 = 00)
Channel 2
(Address: I1, I0 = 01)
0
VSEL01
VSEL02
1
VSEL11
VSEL12
2
VSEL21
VSEL22
3
VSEL31
VSEL32
4
ODT1
ODT2
1 (recommended): The ODT functions are always
enabled, but setting 1 recommended at all times.
5
ENB1
ENB2
0: Disable LNBx Output
1: Enable LNBx Output
6
I0
I0
7
I1
I1
Setting
See table 4, Output Voltage Amplitude Selection
0: LNBx = Low range
1: LNBx = High range
Address Bit
Channel 1: 0
Channel 2: 1
Address Bit
Bit 0
Bit 1
Bit 2
VSEL0x
VSEL1x
VSEL2x
Bit 3
VSEL3x
Bit 4
Bit 5
ODTx
ENBx
Bit 6
Bit 7
I0
I1
Channel 1: 0
Channel 2: 0
These three bits provide incremental control over the voltage on the LNBx output.
The available voltages provide the necessary levels for all the common standards
plus the ability to add line compensation in increments of 333 mV. The voltage levels are
defined in table 4, Output Voltage Amplitude Selection.
Switches between the low level and high level output voltages on the LNBx output. 0 selects
the low level voltage and 1 selects the high level. The low-level center voltage is 12.709 V
nominal and the high level is 18.042 V nominal. These may be increased in steps of 333 mV
using the VSEL2x, VSEL1x and VSEL0x control register bits.
The overcurrent disable timers are always enabled.
Enables the LNBx output. When set to 1 the LNBx output is switched on. When set to 0,
the LNBx output is disabled.
Address
Address
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Table 3. Control Registers with Address (I1, I0) = 10 and 11
Name
Bit
Channel 1
(Address: I1, I0 = 10)
Channel 2
(Address: I1, I0 = 11)
0
TMODE1
TMODE2
0: External Tone
1: Internal Tone
1
TGATE1
TGATE2
0: Tone Gated Off
1: Tone Gated On
2
CADT1
CADT2
0: Cable Disconnect Test Off
1: Cable Disconnect Test On
3
–
–
Not Used
4
–
–
Not Used
5
–
–
Setting
Not Used
Address Bit
6
I0
I0
7
I1
I1
Channel 1: 0
Channel 2: 1
Address Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Channel 1: 1
Channel 2: 1
TMODEx ToneMode. Selects between the use of an external 22 kHz logic signal or the use
of the internal 22 kHz oscillator to control the tone generation on the LNBx output.
A 0 selects the external tone and a 1 selects the internal tone. See the Tone Generation section for more information
TGATEx Tone Gate. Allows either the internal or external 22 kHz tone signals to be gated,
unless the EXTMx is selected for gating. When set to 0, the selected tone (via
TMODEx) is off. When set to 1, the selected tone is on. See Tone Generation Section for more information.
CADTx Cable Disconnect Test. To perform this test, set bits CADT, ENB, and VSEL0
through VSEL3 through the I2C-compatible interface. During this test, the LNB
linear regulator is disabled, a 1 mA current source between the BOOST output and
the LNB output is enabled, and the BOOST voltage is increased to 22.8 V. After
these conditions are set, if the LNB voltage is above 21 V, it is assumed that the
coaxial cable connection between the LNBR output and the LNB head has been
disconnected. In this case, the CAD bit is set in the Status register. If there is a load
on the LNB pin, then the LNB voltage will decrease proportionally to the load
current. If the LNB volts drop below 19.95 V, it is assumed that the coaxial cable is
connected and the CAD bit in the Status register is set to 0.
–
Not Used.
–
Not Used.
–
Not Used.
I0
Address.
I1
Address.
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A8286
Dual LNB Supply and Control Voltage Regulator
Table 4. Output Voltage Amplitude Selection
VSEL3x
VSEL2x
VSEL1x
VSEL0x
LNB (V)
0
0
0
0
12.709
0
0
0
1
13.042
0
0
1
0
13.375
0
0
1
1
13.709
0
1
0
0
14.042
0
1
0
1
14.375
0
1
1
0
14.709
0
1
1
1
15.042
1
0
0
0
18.042
1
0
0
1
18.375
1
0
1
0
18.709
1
0
1
1
19.042
1
1
0
0
19.375
1
1
0
1
19.709
1
1
1
0
20.042
1
1
1
1
20.375
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A8286
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Status Registers (I2C™-Compatible Read Register)
The main fault conditions: overcurrent (OCP), under voltage
(VUV) and overtemperature (TSD), are all indicated by setting
the relevant bits in the Status registers. In all fault cases, once the
bit is set, it remains latched until the A8286 is read by the I2C™
master, assuming the fault has been resolved.
The current status of each LNB output is indicated by the disable
bit, DIS, for that channel. A DIS bit is set when either a fault occurs
or if the LNB is disabled intentionally. These bits are latched and
are reset when the LNB is commanded on again. The power not
good (PNG), tone detect (TDET), and cable disconnected (CAD)
flags are the only bits which may be reset without an I2C™ read
sequence. Table 5 summarizes the condition of each bit when set
and how it is reset.
As the A8286 has a comprehensive set of status reporting bits,
it is necessary to have two Status registers. When performing a
multiple read function, register 1 is read followed by register 2,
then register 1 again and so on. Whenever a new read function is
performed, register 1 is always read first.
The normal sequence of the master in a fault condition will be
to detect the fault by reading the Status registers, then rereading
the Status registers until the status bit is reset indicating the fault
condition is reset. The fault may be detected either by continuously
polling, by responding to an interrupt request (IRQ), or by detecting
a fault condition externally and performing a diagnostic poll of all
slave devices. Note that the fully-operational condition of the Status
registers is all 0s, to simplify checking of the Status bit.
Table 5. Status Register Bit Setting
Status Bit
CAD1, CAD2
Function
Cable disconnected
Set
Non-latched
Reset
Condition
Cable disconnect test off or
cable connected
LNB disabled, either intentionally or
due to fault
Latched
LNB enabled and no fault
OCP1, OCP2
Overcurrent
Latched
I2C™ read and fault removed
PNG1, PNG2
Power not good
Non-latched
LNB volts in range
Tone detect
Non-latched
Tone removed
DIS1, DIS2
TDET1, TDET2
TSD
Thermal shutdown
Latched
I2C™ read and fault removed
VUV
Undervoltage
Latched
I2C™ read and fault removed
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A8286
Dual LNB Supply and Control Voltage Regulator
Table 6. Status Register 1
Bit 0
DIS1
Bit 1
Bit 2
DIS2
OCP1
Bit 3
Bit 4
OCP1
PNG1
Bit 5
Bit 6
PNG2
TSD
Bit 7
VUV
Bit
Name
Function
0
DIS1
LNB output disabled (Channel 1)
1
DIS2
LNB output disabled (Channel 2)
2
OCP1
Overcurrent (Channel 1)
3
OCP2
Overcurrent (Channel 2)
4
PNG1
Power Not Good (Channel 1)
5
PNG2
Power Not Good (Channel 2)
6
TSD
Thermal Shutdown
7
VUV
VIN Undervoltage
LNB Output Disabled. DIS is used to indicate the current condition of the LNB
output for channel 1. At power-on, or if a fault condition occurs, DIS1 is set. This
bit changing to 1 does not cause the IRQ to activate because the LNB output may
be disabled intentionally by the I2C™ master. This bit will be reset at the end of a
write sequence if the LNB output is enabled.
See description for DIS1. This indicates status for channel 2.
Overcurrent. If the LNB output detects an overcurrent condition for greater than
48 ms the LNB output will be disabled. The OCP bit will be set to indicate that an
overcurrent has occurred and the disable bit, DIS1, will be set. The Status register
is updated on the rising edge of the 9th clock pulse in the data read sequence, where
the OCP bit is reset in all cases, allowing the master to reenable the LNB output.
See description for OCP1. This indicates status for channel 2.
Power Not Good. Set to 1 when the LNB voltage is below 85% of the programmed
voltage. The PNG bit is reset when the LNB voltage is within 90% of the programmed LNB voltage. PNG is always active so, if the LNB output is disabled,
then PNG will be a logic 1. At power-up, PNG reports a logic 1 until the LNB
output is enabled and within 90% of the programmed LNB voltage.
See description for PNG1. This indicates status for channel 2.
Thermal shutdown. 1 indicates that the A8286 has detected an overtemperature
condition and has disabled the LNB outputs. The disable bits, DISx, will also be
set. The status of the overtemperature condition is sampled on the rising edge of
the 9th clock pulse in the data read sequence. If the condition is no longer present,
then the TSD bit will be reset, allowing the master to reenable the LNB output if
required. If the condition is still present, then the TSD bit will remain at 1.
Undervoltage Lockout. 1 indicates that the A8286 has detected that the input supply, VIN is, or has been, below the minimum level and an undervoltage lockout has
occurred disabling the LNB outputs. The disable bits, DISx, will also be set, and the
A8286 will not reenable the output until so instructed by writing the relevant bit into
the control registers. The status of the undervoltage condition is sampled on the rising edge of the 9th clock pulse in the data read sequence. If the condition is no longer present, then the VUV bit will be reset allowing the master to reenable the LNB
output if required. If the condition is still present, then the VUV bit will remain at 1.
16
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Table 7. Status Register 2
Bit 0
CAD1
Bit 1
Bit 2
CAD2
TDET1
Bit 3 TDET2
Bits 4 to 7
Bit
Name
Function
0
CAD1
Cable Disconnected (Channel 1)
1
CAD2
Cable Disconnected (Channel 2)
2
TDET1
Tone Detect (Channel 1)
3
TDET2
Tone Detect (Channel 2)
4
–
Not Used
5
–
Not Used
6
–
Not Used
7
–
Not Used
Cable between LNB and the LNB head is disconnected. When cable disconnect
test mode is applied, the LNB linear regulator is disabled and a 1 mA current
source is applied between the BOOST1 and LNB1 output. If the LNB volts rise
above 21 V, CAD1 will be set to 1. The CAD1 bit is reset if the LNB volts drop
below 19.95 V.
See description for CAD1. This indicates status for channel 2.
Tone Detect. When tone is enabled by whatever option, or if a tone signal is received
from the LNB, TDET1 will be set to 1 if the tone appears at the LNB1 output. When
the tone is disabled and no tone is received from the LNB, TDET1 is reset.
See description for CAD1. This indicates status for channel 2.
Not used.
17
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A8286
Dual LNB Supply and Control Voltage Regulator
Table 8. Component Selection Tablea
Component
C3
Characteristics
220 nF, 10 VMIN, X5R or X7R, 0402 or 0603
C8, C9b, C12b
220 nF, 50 V, X5R or X7R, 0805
C1, C4
100 nF, 50 V, X5R or X7R, 0603
C2, C5
100 μF, 35 VMIN , ESR < 75 mΩ, IRIPPLE > 700 mA
C7
C10, C13
Manufacturer and Device
ChemiCon: EKZE500ELL101MHB5D
Nichicon: UHC1V101MPT
Panasonic: EEU-FM1H101B
22 nF, 10 VMIN, X5R or X7R, 0402 or 0603
10 nF, 50 V, X5R or X7R, 0402 or 0603
C11
0.68 μF, 25 VMIN, X5R or X7R, 0805
TDK: C2012X5R1E684K
Murata: GRM21BR71E684KA88
Kemet: C0805C684K3PAC
AVX: 08053D684KAT2A
C6
1.0 μF, 25 VMIN, X5R or X7R, 1206
TDK: C3216X7R1E105K
Murata: GRM31MR71E105KA01
Taiyo Yuden: TMK316BJ105KL-T
Kemet: C1206C105K3RACTU
Schottky diode, 40 V, 3 A, SMA
Sanken: SFPB-74
Vishay: B340A-E3/5AT
Diodes, Inc.: B340A-13-F
Central Semi: CMSH3-40MA
Schottky diode, 40 V, 1 A, SOD-123
Diodes, Inc.: B140HW-7
Central Semi: CMMSH1-40
D4
TVS, 20 VRM, 32 VCL at 500 A (8/20 μs), 3000 W
Littelfuse: SMDJ20A
ST: LNBTVS6-221S
L1
33 H, ISAT > 2.6 A, DCR < 90 mΩ
TDK: TSL1112RA-330K2R3-PF
Taiyo Yuden: LHLC10TB330K
Coilcraft: DR0810-333L
L2
220 H, ISAT > 0.5 A, DCR < 0.8 mΩ
TDK: TSL0808RA-221KR54-PF
Taiyo Yuden: LHLC08TB221K
Coilcraft: DR0608-224L
1 H, 1 A, DCR < 120 mΩ, 1206
Kemet: LB3218-T1R0MK
Murata: LQM31PN1R0M00L
Taiyo Yuden: LB3218T1R0M
TDK: MLP3216S1R0L
D1
D2, D3
L3
R1 to R5
Determined by VDD, bus capacitance, etc.
R6
15 Ω, 1%, 1/8 W
R7
100 Ω, 1%, 1/8 W
R8
30 Ω, 1%, 1/8 W
aComponents
bEither
for channel 1 and channel 2 are identical.
C9 or C12 are used, but not both.
18
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A8286
Dual LNB Supply and Control Voltage Regulator
Package ET 28-Pin MLP/QFN
0.30
5.00 ±0.15
1.15
28
1
2
0.50
28
1
A
5.00 ±0.15
3.15
4.80
3.15
29X
D
SEATING
PLANE
0.08 C
C
4.80
C
+0.05
0.25 –0.07
PCB Layout Reference View
0.90 ±0.10
0.50
For Reference Only
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
+0.20
0.55 –0.10
A Terminal #1 mark area
B
3.15
2
1
28
3.15
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
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Revision History
Revision
Revision Date
Rev. 17
February 15, 2012
Description of Revision
Absolute Maximum Ratings
I2C™ is a trademark of Philips Semiconductors.
DiSEqC™ is a trademark of Eutelsat S.A.
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright ©2005-2013, Allegro MicroSystems, LLC
For the latest version of this document, visit our website:
www.allegromicro.com
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