Datasheet 6ED-F2 - 2nd generation

Eice DR IV ER ™
High voltage gate driver IC
6E D f a mil y - 2 nd g e nera tion
3 phase 600 V gate drive IC
6ED003L06-F2
6ED003L02-F2
EiceDRIVER™
datash eet
<Revision 2.7>, 15.04.2015
Indust rial Po wer & Con trol
Edition 15.04.2015
Published by
Infineon Technologies AG
81726 Munich, Germany
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EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
Revision History
Page or Item
Subjects (major changes since previous revision)
<Revision 2.7>, 15.04.2015
all
revised wording for test temperature
p. 14
inserted Figure 14: ITRIP input filter time
p.17
revised Figure 8 and Figure 9
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datasheet
3
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
Table of Contents
1
Overview ............................................................................................................................................. 5
2
Blockdiagram...................................................................................................................................... 6
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Pin configuration, description, and functionality ........................................................................... 7
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) .................................................................. 7
EN (Gate Driver Enable, Pin 10) .......................................................................................................... 8
/FAULT (Fault Feedback, Pin 8) .......................................................................................................... 8
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) ........................................................... 9
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) ........................................................................ 9
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) ............................................... 9
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) ................................. 9
4
4.1
4.2
4.3
4.4
4.5
4.6
Electrical Parameters ....................................................................................................................... 10
Absolute Maximum Ratings ............................................................................................................... 10
Required operation conditions ........................................................................................................... 11
Operating Range ................................................................................................................................ 11
Static logic function table ................................................................................................................... 12
Static parameters ............................................................................................................................... 12
Dynamic parameters .......................................................................................................................... 14
5
Timing diagrams............................................................................................................................... 15
6
6.1
6.2
Package ............................................................................................................................................. 18
PG-DSO-28 ........................................................................................................................................ 18
PG-TSSOP-28.................................................................................................................................... 19
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Typical Application ............................................................................................................................... 6
Block diagram for 6ED003L06-F2 / 6ED003L02-F2 ............................................................................ 6
Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2 ................................................................... 7
Input pin structure................................................................................................................................. 7
Input filter timing diagram ..................................................................................................................... 8
EN pin structures .................................................................................................................................. 8
/FAULT pin structures .......................................................................................................................... 8
Timing of short pulse suppression ..................................................................................................... 15
Timing of internal deadtime ................................................................................................................ 15
Enable delay time definition ............................................................................................................... 15
Input to output propagation delay times and switching times definition ............................................. 16
Operating areas.................................................................................................................................. 16
ITRIP-Timing ...................................................................................................................................... 16
ITRIP input filter time .......................................................................................................................... 17
Package drawing ................................................................................................................................ 18
PCB reference layout ......................................................................................................................... 18
Package drawing ................................................................................................................................ 19
PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint19
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
datasheet
nd
Members of 6ED family – 2 generation ............................................................................................. 5
Pin Description ..................................................................................................................................... 7
Abs. maximum ratings ........................................................................................................................ 10
Required Operation Conditions .......................................................................................................... 11
Operating range ................................................................................................................................. 11
Static parameters ............................................................................................................................... 12
Dynamic parameters .......................................................................................................................... 14
Data of reference layout ..................................................................................................................... 19
4
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
EiceDRIVER™
3 phase 600 V gate drive IC
Overview
1
Main features

Thin-film-SOI-technology

Maximum blocking voltage +600V

Separate control circuits for all six drivers

CMOS and LSTTL compatible input (negative logic)

Signal interlocking of every phase to prevent cross-conduction

Detection of over current and under voltage supply

externally programmable delay for fault clear after over current
PG-DSO28
PG-TSSOP28
detection
Product highlights

Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology

'shut down' of all switches during error conditions
Typical applications

Home appliances

Fans, pumps

General purpose drives
Product family
Table 1
nd
Members of 6ED family – 2
Sales Name
6ED003L06-F2 / 6ED003L02-F2
generation
high side control input
HIN1,2,3 and LIN1,2,3
typ. UVLOThresholds
Bootstrap Package
diode
negative logic
11.7 V / 9.8 V
No
DSO28 / TSSOP28
Description
The devices are full bridge drivers to control power devices like MOS-transistors or IGBTs in 3-phase systems
with a maximum blocking voltage of +600 V. Based on the used SOI-technology there is an excellent
ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic
latch-up may occur at all temperatures and voltage conditions.
The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals, down
to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic and an overcurrent detection. The over-current level is adjusted by choosing the resistor value and the threshold level at pin
ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut down of all six switches. An
error signal is provided at the FAULT open drain output pin. The blocking time after over-current can be
adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of 2.8 µA. Therefore,
the resistor RRCIN is optional. The typical output current can be given with 165 mA for pull-up and 375 mA for pull
down. Because of system safety reasons a 310 ns interlocking time has been realised. The function of input EN
can optionally be extended with an over-temperature detection, using an external NTC-resistor (see Fig.1).
datasheet
5
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EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
DC-Bus
VCC
VCC
HIN1,2,3
LIN1,2,3
EN
HIN1,2,3
LIN1,2,3
EN
VB1,2,3
HO1,2,3
To Load
VS1,2,3
5V
FAULT
FAULT
LO1,2,3
RRCIN
CRCIN
COM
RCIN
ITRIP
VSS
R Sh
VSS
Figure 1
Typical Application
Blockdiagram
2
BIAS NETWORK / VDD2
INPUT NOISE
FILTER
HIN1
LIN1
INPUT NOISE
FILTER
HIN2
INPUT NOISE
FILTER
LIN2
INPUT NOISE
FILTER
HIN3
INPUT NOISE
FILTER
VB1
BIAS NETWORK - VB1
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
HV LEVEL-SHIFTER
+ REVERSE-DIODE
z
COMPAR
ATOR
UVDETECT
GateDrive
VS1
VB2
BIAS NETWORK - VB2
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
UVDETECT
GateDrive
HO2
VS2
VB3
BIAS NETWORK / VB3
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
UVDETECT
GateDrive
INPUT NOISE
FILTER
LIN3
HO1
HO3
VS3
>1
INPUT NOISE
FILTER
EN
ITRIP
VCC
UVDETECT
DELAY
VSS / COM
LEVELSHIFTER
GateDrive
LO1
DELAY
VSS / COM
LEVELSHIFTER
GateDrive
LO2
DELAY
VSS / COM
LEVELSHIFTER
GateDrive
LO3
INPUT NOISE
FILTER
S
VDD2
Q
SET
DOMINANT
LATCH
R
IRCIN
RCIN
COM
FAULT
VSS
>1
Figure 2
datasheet
Block diagram for 6ED003L06-F2 / 6ED003L02-F2
6
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
3
Pin configuration, description, and functionality
1
VCC
VB1
2
HIN1
HO1 27
3
HIN2
VS1
26
4
HIN3
nc
25
5
LIN1
VB2
24
6
LIN2
HO2 23
7
LIN3
VS2
22
8
FAULT
nc
21
9
ITRIP
VB3
20
10 EN
HO3 19
11 RCIN
VS3
18
nc
17
13 COM
LO1
16
14 LO3
LO2
15
12 VSS
Figure 3
Table 2
28
Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2
Pin Description
Symbol
Description
VCC
Low side power supply
VSS
Logic ground
/HIN1,2,3
High side logic input
/LIN1,2,3
Low side logic input
/FAULT
Indicates over-current and under-voltage (negative logic, open-drain output)
EN
Enable I/O functionality (positive logic)
ITRIP
Analog input for over-current shut down, activates FAULT and RCIN to VSS
RCIN
External RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR)
COM
Low side gate driver reference
VB1,2,3
High side positive power supply
HO1,2,3
High side gate driver output
VS1,2,3
High side negative power supply
LO1,2,3
Low side gate driver output
nc
Not connected
3.1
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7)
The Schmitt trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. Input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses
according to Figure 4 and Figure 5.
Vcc
Schmitt-Trigger
HINx
LINx
INPUT NOISE
FILTER
UZ=10.5V
SWITCH LEVEL
VIH; VIL
Figure 4
datasheet
Input pin structure
7
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EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
An internal pull-up of about 75 k (negative logic) pre-biases the input during supply start-up and a ESD zener
clamp is provided for pin protection purposes. The zener diodes are therefore designed for single pulse stress
only and not for continuous voltage stress over 10V.
tFILIN
tFILIN
LIN on
HIN
off
HIN
LIN
on
off
on
off
high
HO
LO
LO
HO
Figure 5
low
Input filter timing diagram
It is anyway recommended for proper work of the driver not to provide input pulse-width lower than 1 µs.
The 6ED-F2 driver IC provide additionally a shoot through prevention capability which avoids the simultaneous
on-state of two channels of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When two inputs of
a same leg are activated, only one leg output is activated, so that the leg is kept steadily in a safe state. Please
refer to the application note AN-Gatedrive-6ED2-1 for a detailed description.
A minimum dead time insertion of typ. 310 ns is also provided, in order to reduce cross-conduction of the
external power switches.
3.2
EN (Gate Driver Enable, Pin 10)
The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW
logic level. The internal structure of the pin is given in Figure 6. The switching levels of the Schmitt-Trigger are
here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The typical propagation delay time is tEN = 780 ns. There is an internal
pull down resistor (75 k), which keeps the gate outputs off in case of broken PCB connection.
IEN+, IEN-
EN
INPUT NOISE
FILTER
VEN,TH+,
VEN,TH-
VZ= 10.5 V
6ED family – 2nd generation
Figure 6
3.3
EN pin structures
/FAULT (Fault Feedback, Pin 8)
/Fault pin is an active low open-drain output indicating the status of the gate driver (see Figure 7). The pin is
active (i.e. forces LOW voltage level) when one of the following conditions occur:

Under-voltage condition of VCC supply: In this case the fault condition is released as soon as the
supply voltage condition returns in the normal operation range (please refer to VCC pin description for
more details).

Over-current detection (ITRIP): The fault condition is latched until current trip condition is finished and
RCIN input is released (please refer to ITRIP pin).
VDD
6ED family –
2nd generation
VCC
RON,FLT
FAULT
Figure 7
datasheet
>1
from ITRIP-Latch
from uv-detection
/FAULT pin structures
8
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EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
3.4
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11)
nd
The 6ED family – 2 generation provides an over-current detection function by connecting the ITRIP input with
the motor current feedback. The ITRIP comparator threshold (typ 0.44 V) is referenced to VSS ground. A input
noise filter (typ. tITRIPMIN = 230 ns) prevents the driver to detect false over-current events.
Over-current detection generates a hard shut down of all outputs of the gate driver and provides a latched fault
feedback at /FAULT pin. RCIN input/output pin is used to determine the reset time of the fault condition. As
soon as ITRIP threshold is exceeded the external capacitor connected to RCIN is fully discharged. The
capacitor is then recharged by the RCIN current generator when the over-current condition is finished. As soon
as RCIN voltage exceeds the rising threshold of typ VRCIN,TH = 5.2 V, the fault condition releases and the driver
returns operational following the ontrol input pins according to section 3.1. Please refer to AN-Gatedrive-6ED2-1
for details on setting RCIN time constant.
3.5
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13)
VCC is the low side supply and it provides power both to input logic and to low side output power stage. Input
logic is referenced to VSS ground as well as the under-voltage detection circuit. Output power stage is
referenced to COM ground. COM ground is floating respect to VSS ground with a maximum range of operation
of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VCCUV+ is present.
The IC shuts down all the gate drivers power outputs, when the VCC supply voltage is below V CCUV- = 9.8 V.
This prevents the external power switches from critically low gate voltage levels during on-state and therefore
from excessive power dissipation. Please consult the individual output characteristic of the driven transistor.
3.6
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28)
VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VCC.
The device operating area as a function of the supply voltage is given in Figure 12. Details on bootstrap supply
section and transient immunity can be found in application note AN-Gatedrive-6ED2-1.
3.7
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive of IGBT
and MOSFET devices. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs, while high
side outputs (i.e. HO1,2,3) are edge triggered by the respective inputs. In particular, after an under voltage
condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the respective high side
output, while after a under voltage condition of the VCC supply, the low side outputs switch to the state of their
respective inputs.
datasheet
9
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EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
4
Electrical Parameters
4.1
Absolute Maximum Ratings
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are
valid for Ta=25 °C.
Table 3
Abs. maximum ratings
Parameter
High side offset voltage(Note 1)
DSO28
TSSOP28
Symbol
VS
Max.
Unit
VCC-VBS-6
600
180
V
VCC -VBS – 50 –
High side offset voltage (tp<500ns, Note 1)
High side offset voltage(Note 1)
Min.
DSO28
TSSOP28
VB
High side offset voltage (tp<500ns, Note 1)
VCC – 6
620
200
VCC – 50
–
High side floating supply voltage (VB vs. VS) (internally clamped)
VBS
-1
20
High side output voltage (VHO vs. VS)
VHO
-0.5
VB + 0.5
Low side supply voltage (internally clamped)
Low side supply voltage (VCC vs. VCOM)
VCC
-1
20
VCCOM
-0.5
25
Gate driver ground
Low side output voltage (VLO vs. VCOM)
VCOM
-5.7
VLO
-0.5
5.7
VCCOM + 0.5
Input voltage /LIN, /HIN, EN, ITRIP
VIN
-1
FAULT output voltage
VFLT
-0.5
RCIN output voltage
VRCIN
VCC + 0.5
TJ
-0.5
–
–
–
–
–
Storage temperature
TS
- 40
150
offset voltage slew rate (Note 3)
dVS/dt
Power dissipation (to package) Note 2
Thermal resistance
(junction to ambient, see section 6)
Junction temperature
DSO28
TSSOP28
DSO28
TSSOP28
PD
Rth(j-a)
10
VCC + 0.5
1.3
0.6
75
165
125
50
W
K/W
°C
V/ns
Note :The value for ESD immunity is 1.0kV (Human Body Model). ESD immunity for pins inside the low side (i.e. VCC, /HINx, /LINx, FAULT,
EN, RCIN, ITRIP, VSS, COM, LOx) and ESD immunity for pins inside each high side itself (i.e. VBx, HOx, VSx) is guaranteed up to 1.5kV
(Human Body Model).
Note 1 : Insensitivity of bridge output to negative transient voltage up to –50V is not subject to production test – verified by design /
characterization. External bootstrap diode is mandatory. Refer to application note.
Note 2: Consistent power dissipation of all outputs. All parameters inside operating range.
Note 3: Not subject of production test, verified by characterisation
datasheet
10
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EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
4.2
Required operation conditions
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are
valid for Ta=25 °C.
Table 4
Required Operation Conditions
Parameter
High side offset voltage (Note 1)
DSO28
TSSOP28
Low side supply voltage (VCC vs. VCOM)
DSO28
TSSOP28
4.3
Symbol
VB
Min.
Max.
Unit
7
620
200
V
VCCOM
10
25
Operating Range
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (Ta = 25°C)
Table 5
Operating range
Parameter
Symbol
VS
High side floating supply offset voltage
Min.
VCC VBS -1
Max.
Unit
V
500
High side floating supply offset voltage (VB vs. VCC, statically)
VBCC
-1.0
500
High side floating supply voltage (VB vs. VS, Note 1)
VBS
13
High side output voltage (VHO vs. VS)
VHO
10
17.5
VBS
Low side output voltage (VLO vs. VCOM)
VLO
0
VCC
Low side supply voltage
VCC
13
17.5
Low side ground voltage
VCOM
-2.5
2.5
Logic input voltages /LIN, /HIN, EN, ITRIP (Note 2)
VIN
0
FAULT output voltage
VFLT
0
5
VCC
RCIN input voltage
VRCIN
0
VCC
Pulse width for ON or OFF (Note 3)
tIN
1
–
µs
Ambient temperature
Ta
-40
95
°C
Note 1 : Logic operational for VB (VB vs. VSS) > 7,0V
Note 2 : All input pins (/HINx, /LINx) and EN, ITRIP pin are internally clamped (see abs. maximum ratings)
Note 3 : In case of input pulse width at /LINx and /HINx below 1µs the input pulse may not be transmitted properly
datasheet
11
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EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
4.4
Static logic function table
VCC
VBS
RCIN
ITRIP
ENABLE
FAULT
LO1,2,3
HO1,2,3
<VCCUV–
X
X
X
X
0
0
0
15V
<VBSUV–
X
0
3.3 V
High imp
/LIN1,2,3
0
15V
15V
<3.2 V 
0
3.3 V
0
0
0
15V
15V
X
> VIT,TH+
3.3 V
0
0
0
15V
15V
> VRCIN,TH
0
3.3 V
High imp
/LIN1,2,3
/HIN1,2,3
15V
15V
> VRCIN,TH
0
0
High imp
0
0
4.5
Static parameters
VCC = VBS = 15V unless otherwise specified. All parameters are valid for Ta=25 °C.
Table 6
Static parameters
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Test condition
High level input voltage
VIH
1.7
2.1
2.4
Low level input voltage
VIL
0.7
0.9
1.1
EN positive going threshold
VEN,TH+
1.9
2.1
2.3
EN negative going threshold
VEN,TH-
1.1
1.3
1.5
ITRIP positive going threshold
VIT,TH+
380
445
510
mV
ITRIP input hysteresis
VIT,HYS
45
70
RCIN positive going threshold
VRCIN,TH
-
5.2
6.4
V
RCIN input hysteresis
VRCIN,HYS
-
2.0
-
Input clamp voltage
(/HIN, /LIN, EN, ITRIP)
Input clamp voltage at high impedance
(/HIN, /LIN)
VIN,CLMAP
9
10.3
12
IIN = 4mA
VIN,FLOAT
-
5.3
5.8
controller output
pin floating
High level output voltage
LO1,2,3
HO1,2,3
VOH
-
VCC -0.7 VCC -1.4
VB -0.7 VB -1.4
IO = 20mA
Low level output voltage
LO1,2,3
VOL
-
VCOM+
0.6
VS + 0.6
IO = -20mA
12.5
HO1,2,3
VCC and VBS supply undervoltage positive
going threshold
VCC and VBS supply undervoltage negative
going threshold
-
VCOM+
0.2
VS+ 0.2
VCCUV+
VBSUV+
VCCUV–
VBSUV–
11
11.7
9.5
9.8
VCC and VBS supply undervoltage lockout
hysteresis
VCCUVH
VBSUVH
1.2
1.9
datasheet
12
10.8
V
V
-
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
Table 6
Static parameters
Parameter
Symbol
Values
Unit
Test condition
µA
VS = 600V
TJ = 125°C,
VS = 600V
Min.
Typ.
Max.
High side leakage current betw. VS and VSS ILVS+
1
High side leakage current betw. VS and VSS ILVS+
-
1
12.5
-
10
-
High side leakage current between VSx and ILVS–
VSy (x=1,2,3 and y=1,2,3)
IQBS1
Quiescent current VBS supply (VB only)
1
-
10
-
-
210
400
Quiescent current VBS supply (VB only)
IQBS2
-
210
400
Quiescent current VCC supply (VCC only)
IQCC1
-
1.1
1.8
Quiescent current VCC supply (VCC only)
IQCC2
-
1.3
2
Input bias current
ILIN+
-
70
100
µA
VLIN=3.3 V
Input bias current
ILIN-
-
110
200
µA
VLIN=0
Input bias current
IHIN+
-
70
100
VHIN=3.3 V
Input bias current
IHIN-
-
110
200
VHIN=0
Input bias current (ITRIP=high)
IITRIP+
45
120
VITRIP=3.3 V
Input bias current (EN=high)
IEN+
45
120
VENABLE=3.3 V
Input bias current RCIN (internal current
source)
Mean output current for load capacity
charging in range from 3 V (20%) to 6 V
(40%)
IRCIN
Peak output current turn on (single pulse)
IOpk+1
IO+
-
TJ = 125°C
VSx - VSy = 600V
µA
HO=low
mA
HO=high
VLIN=float.
VLIN=0, VHIN=3.3 V
VRCIN = 2 V
2.8
120
165
-
CL=10 nF
RL = 0 , tp <10 µs
240
Mean output current for load capacity
discharging in range from 12 V (80%) to 9 V
(60%)
IOpk-1
Peak output current turn off (single pulse)
250
RCIN low on resistance of the pull down
transistor
Ron,RCIN
-
40
100
VRCIN=0.5 V
FAULT low on resistance of the pull down
transistor
Ron,FLT
-
45
100
VFAULT=0.5 V
IO-
1
375
mA
-
CL=10 nF
RL = 0 , tp <10 µs
420
Not subject of production test, verified by characterisation
datasheet
13
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
4.6
Dynamic parameters
VCC = VBS = 15 V, VS = VSS = VCOM unless otherwise specified. All parameters are valid for Ta=25 °C.
Table 7
Dynamic parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Test condition
ns
VLIN/HIN = 0 or 3.3 V
Turn-on propagation delay
Turn-off propagation delay
ton
toff
400
360
530
490
800
760
Turn-on rise time
tr
-
60
100
Turn-off fall time
tf
-
26
45
VLIN/HIN = 0 or 3.3 V
CL = 1 nF
Shutdown propagation delay ENABLE
tEN
-
780
1100
VEN=0
Shutdown propagation delay ITRIP
tITRIP
400
670
1000
VITRIP=1 V
Input filter time ITRIP
tITRIPMIN
155
230
380
Propagation delay ITRIP to FAULT
tFLT
-
420
700
Input filter time at LIN/HIN for turn on and off tFILIN
tFILEN
Input filter time EN
120
300
-
300
600
-
Fault clear time at RCIN after ITRIP-fault,
(CRCin=1nF)
tFLTCLR
1.0
1.9
3.0
ms
VLIN/HIN = 0 & 3.3 V
VITRIP = 0
Dead time
DT
150
310
-
ns
VLIN/HIN = 0 & 3.3 V
Matching delay ON, max(ton)-min(ton), ton
are applicable to all 6 driver outputs
MTON
-
20
100
external dead time
> 500 ns
-
40
100
external dead time
>500 ns
40
100
PW in > 1 µs
Matching delay OFF, max(toff)-min(toff), toff MTOFF
are applicable to all 6 driver outputs
Output pulse width matching. Pwin-PW out
PM
datasheet
14
VLIN/HIN = 0 & 3.3 V
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
Timing diagrams
5
tFILIN
tFILIN
tIN
HIN/LIN
HIN/LIN
tIN
tIN < tFILIN
tIN < tFILIN
high
HO/LO
low
HO/LO
HIN/LIN
tIN
HIN/LIN
tIN
tIN > tFILIN
tIN > tFILIN
HO/LO
HO/LO
Figure 8
Timing of short pulse suppression
LIN1,2,3
1.65V
1.65V
HIN1,2,3
12V
LO1,2,3
3V
DT
DT
12 V
HO1,2,3
3V
Figure 9
Timing of internal deadtime
EN
tEN
HO1,2,3
LO1,2,3
Figure 10
datasheet
3V
Enable delay time definition
15
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
PWIN
LIN1,2,3
1.65V
1.65V
HIN1,2,3
ton
toff
tr
12V
tf
12V
HO1,2,3
LO1,2,3
3V
Figure 11
3V
PWOUT
Input to output propagation delay times and switching times definition
20
V
17.5
VCCMAX , VBSMAX
vCC
vBS
13
VCCUV+, VBSUV+ 11.7
VCCUV-, VBSUV- 9.8
t
IC STATE
OFF
Figure 12
ON
ON
Recommended
Area
ON
Forbidden
Area
ON
ON
Recommended
Area
ON
OFF
Operating areas
VRCIN,TH
RCIN
ITRIP
0.1V
0.1V
FAULT
1V
0.5V
tFLT
tFLTCLR
Any
output
Figure 13
datasheet
3V
tITRIP
ITRIP-Timing
16
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
tITRIPMIN
ITRIP
tITRIPMIN
tIN
tIN
high
tFLTCLR
/FAULT
Figure 14
datasheet
ITRIP input filter time
17
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
6
Package
6.1
PG-DSO-28
Figure 15
Figure 16
datasheet
Package drawing
Dimensions
80.0  80.0  1.5 mm³
therm [W/mK]
Material
FR4
0.3
Metal (Copper)
70µm
388
PCB reference layout
18
<Revision 2.7>, 15.04.2015
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
6.2
PG-TSSOP-28
Footprint for Reflow soldering
e = 0.65
A = 6.10
L = 1.30
B = 0.40
Figure 17
Package drawing
Figure 18
PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint
Table 8
Data of reference layout
Dimensions
Material
Metal (Copper)
76.2  114.3  1.5 mm³
FR4 (therm = 0.3 W/mK)
70µm (therm = 388 W/mK)
datasheet
19
<Revision 2.7>, 15.04.2015
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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