SPOC Front Light BTS5482SF - Application hints Application Note Rev. 1.0, 2013-08-27 Automotive Power SPOC Front Light BTS5482SF - Application hints Abstract 1 Abstract Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. This Application Note is intended to provide application hints when using the BTS5482SF in a typical 12V automotive lighting application. It will be shown what to consider when dimensioning external components to improve the robustness in the application. Furthermore, the protection mechanisms of the device will be detailed and some basic software hints will be given. Finally, information about the thermal behavior of the BTS5482SF will be presented. This Application Note must be used in conjunction with the latest BTS5482SF data sheet. For detailed component information, this Application Note has to be used as an additional information to the data sheet and not as a document explaining the device in detail. This Application Note refers to the latest Data Sheet. Table 1 Terms in use Abbreviation Meaning DMOS Double diffused MOS EMC Electromagnetic compatibility ESD Electro Static Discharge GND Ground IN Input LED Light Emitting Diode KILIS Current sense ratio (IL/IS) µC Micro Controller SC Short circuit VBAT VDD VS Battery voltage, measured at the battery terminal SPI Serial peripheral interface SPOC SPI Power Controller OEM Original Equipment Manufacturer OpAmp Operational amplifier PROFET Protected FET TIER1 Supplier of the ECU to the OEM Application Note Logic supply voltage Supply voltage of the device, measured at the device pin 2 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Introduction 2 Introduction The BTS5482SF is a four channel high-side Smart Power Switch designed for automotive lighting applications. It features embedded protection and diagnosis functions. The device further supports: • • • • Configuration and status diagnosis via SPI Fail-safe feature via limp home input pin Dedicated LED features for channel 2 and 3 Control of two additional loads with external smart power switches Figure 1 shows a typical lighting application where the BTS5482SF controls front light functions. HB IND LB FOG PL SPI Ch0 µC Ch1 Ch3 SPOC FL HB: High Beam LB: Low Beam PL: Park Light Ch2 IN & N DE Driver Control IND: Indicator FOG: Fog Light CL: Corner Light IN & DEN Ch0 Profet Profet Ch0 CL Figure 1 BTS5482SF application example Application Note 3 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Automotive Environment 3 Automotive Environment In automotive applications several events may occur, which could disturb or overstress an electronic component. Due to the fact that several loads are sharing the same supply line, disturbances could be induced on the battery line and propagated to each connected device. For a detailed description of these conditions please refer to the following Infineon Application note: “What the designer should know. Short introduction to PROFETTM + 12V” To increase the robustness under these conditions it is recommended to place external components for filtering. Figure 2 shows a typical application circuit for BTS5482SF. Vbat 1 5V 100nF 3 500Ω 100nF WD-OUT VDD VCC GPIO 8kΩ IN1 GPIO 8kΩ IN2 VS IN3 OUT0 IS OUT1 1kΩ AD 27 W OUT3 2.7kΩ 10W GND µC 10nF 3 e. g. XC 2267 SPI 65 W OUT2 1nF 2µF 65 W VDD 3.9kΩ CS 3.9kΩ SCLK 3.9kΩ SO 3.9kΩ SI SPI LHI 8kΩ WD -OUT 100nF 3 10kΩ VS IN0 VSS external driver EDO0 control EDD0 IN1 PROFET OUT0 Ch0 DEN EDO1 DSEL EDD1 GND IS PROFET Ch1 OUT1 GND 10Ω 2 1 2 3 Figure 2 For filtering and protection purposes For increased ISO-pulse robustness For improved electromagnetic compatibility(EMC) Circuit _STD_EXT .emf Application Proposal BTS5482SF Note: The application circuit above shows a typical case. The circuit in the real application has to be optimized towards application requirements. Application Note 4 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Automotive Environment The BTS5482SF requires two supply lines. The battery supply VS and the logic supply VDD. On the battery supply a 100nF capacitor is recommended to improve the electromagnetic compatibility (EMC) of the device (see Chapter 6). The VDD line is the supply for the SPI block of the device which has to be a very stable supply similar to what a µC needs. Due to this reason, a capacitor for buffering the supply is recommended. This capacitor has to be connected between VDD pin and GND pin of the SPOC and should be in the range of 100nF. In addition, a series resistor is recommended on the VDD. The voltage regulator for the logic supply should be reverse battery protected, to protect the parts connected to VDD (µC, SPOC,...) during reverse battery or negative transients on battery. To switch channels directly (e.g. in Limp Home mode), the device offers three parallel input pins. Since these pins are possible current paths in reverse battery or during negative transients on battery, series resistors are needed to ensure that the maximum ratings are not exceeded. This is also valid for all other logic pins of the device. For the LHI pin a pull-down resistor is recommended in addition to avoid unwanted Limp Home activations. For the SPI pins the series resistors have an impact on the SPI speed. In case a higher value of the resistor has to be used, the clock frequency of the SPI has to be reduced. It has to be ensured that under worst case conditions the timings of the SPI signals are not violating the specified limits. Chapter 4 shows which current paths need to be considered when dimensioning the external components. The amount and size of external components depend on the application schematic itself and the requirements for the different application conditions (reverse battery, battery transients, EMC,...). Application Note 5 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Protection Functions 4 Protection Functions The BTS5482SF provides several functions to protect the device under fault conditions which are considered as “outside” of the normal operating range. These protective functions should not be activated in the normal operating range. 4.1 Reverse battery A reverse battery condition exists, when the supply line VBAT is connected to ground and the ground line GND to the battery supply. The voltage and the duration for a reverse battery condition is defined by the OEM. In reverse battery operation, power dissipation is normally from the body diode of the DMOS and the ESD diodes of the logic pins. The BTS5482SF provides a reverse battery protection called ReverSaveTM. Due to this feature, all internal channels are switched ON in case of reverse battery and the power dissipation is reduced to the losses caused by the reverse ON-state resistance RDS(REV). Since there are no protection functions available during reverse operation, the current through the DMOS has to be limited by the connected loads. For further information refer to the latest Data Sheet. Even so, the logic pins have to be protected by series resistors to ensure that the maximum rating for each pin is not exceeded. When dimensioning these resistors, all currents flowing from GND to battery have to be considered. Figure 3 shows the possible current paths from GND to battery in a reverse battery condition. VBAT 1) 500Ω Ire v 100nF Ir ev VDD Irev 8kΩ Irev 8kΩ Irev 8kΩ IN2 IN3 Irev AD Ire v GPIO Ir ev GPIO VS IN1 IS OUT0 Ir ev VCC OUT1 OUT2 Ire v 1kΩ 2.7kΩ OUT3 Ir ev Ire v Ir ev 1nF Irev 2µF 100nF WD-OUT Irev GPIO 3.9kΩ LHI Ire v VDD = 0V Ir ev 0V WD-OUT SPI 8kΩ 100nF VS Irev INx Dx Ire v EDOx Ir ev Irev OUTx Ire v GND Ir ev Ir ev Ire v Irev Ir ev Irev VSS EDDx Ire v Ir ev Ir ev 10kΩ Irev IS Ir ev GND 10Ω 14V BCM GND Figure 3 1) In case a reverse protected voltage regulator is used this point would be high impedant and there would be no current flowing . Inverse_Current_EXT .emf Application diagram with current paths during reverse battery As shown in Figure 3, there are multiple current paths in reverse battery, although the BTS5482SF provides the ReverSaveTM feature. It has to be ensured in the application, that none of these current paths are exceeding the maximum rating of any pin. There could be additional current paths in case other devices are sharing SPI lines. Therefore it is important that the additional current paths are checked and considered in the calculation. Another current path would exist in case the VDD supply is not reverse protected or is shared between several devices. Some calculation examples are shown in Chapter 9.1. Application Note 6 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Protection Functions 4.2 Transients on battery Transients on the battery line could happen due to several reasons. For example, due to the starter-alternator, when switching inductive loads, during jump start or when a load dump occurs. To increase the robustness against these transients, it is recommended to use a central protection circuit on each battery line. This circuit could be realized by a suppressor diode and a capacitor. For the capacitor a value of >2µF is recommended. In case there is no central clamping available, it has to be ensured that transients on battery (negative or positive) will not exceed the maximum rating of each pin. Possible current paths for negative transients on battery are shown in Figure 3. For positive pulses please refer to Figure 4. Irev Vbat > 40V 5V 500Ω 100nF 100nF WD-OUT VS IN1 8kΩ IN2 8kΩ IN3 8kΩ OUT0 IS Ire v AD OUT1 OUT2 1kΩ OUT3 2.7kΩ Ire v 1nF 2µF LHI GPIO 3.9kΩ WD-OUT 8kΩ SPI 100nF VS EDOx Dx Irev INx Ir ev 10kΩ EDDx Irev GPIO Ire v GPIO Ir ev Ire v VDD VCC VSS GND Ir ev OUTx IS Ire v GND 10Ω Positive _Transient_EXT .emf BCM GND = 0V Figure 4 Possible current paths with positive transients on battery Note: If a transient on the battery generates a GND shift, which is above one diode forward voltage, there could be a current flowing into the GPIO of the µC. In this case the current state (high/low) of the GPIO has to be considered. For protection purposes there are several sensors integrated in the device. To reach the highest accuracy, some of these sensors are placed in the power DMOS of the device. Due to this fact, the sensors are exposed to every noise which is coupled through battery or output lines. Up to a certain level of noise, the function of the device is not disturbed. This robustness is achieved through analog and digital filtering. Since the level of filtering is limited to ensure the robustness of the device, the application has to provide the additional hardware and software filtering. Application Note 7 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Protection Functions 4.3 Protection of logic pins of the device The logic pins of the device are low voltage inputs which have to be protected against voltages or currents which are exceeding the maximum ratings. Depending on the function of each logic pin the requirements and possibilities for protection could be different. 4.3.1 Protection on VDD The VDD line is the supply for the SPI block of the device. This has to be a very stable supply as a micro controller requires. Due to this reason, a capacitor for buffering the supply is recommended. This capacitor has to be between the VDD and the GND of the SPOC and should have a value of around 100nF. In addition, a series resistor is recommended on the VDD. The voltage regulator on VDD should be reverse protected, to protect the parts connected to VDD (µC, SPOC,...) during reverse battery and negative transients on battery. 4.3.2 Protection on SPI Pins The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface working at a frequency up to 5 MHz. Due to this reason the size of the used series resistors is limited. The value of the needed series resistors depend on the application circuit and it’s requirements for the different application cases (positive transients, negative transients, reverse battery,...). In case devices on different supply lines are sharing the SPI lines, cross currents between the devices have to be considered. The reason for this are possible potential differences between the battery lines due to transients. For the calculation the internal structures in Figure 3 and Figure 4 can be used. It has to be ensured, that the maximum ratings from the datasheet are not exceeded. 4.3.3 Protection on Parallel Input Pins INx and LHI Pin The parallel input pins and the LHI pin in a SPOC device are mainly used for PWM operation and in fail safe mode. Typically the switching frequency at these pins is low. Therefore it is possible to use serial resistors of several kΩ. For the fail safe mode there are two points which need to be considered: • • In case the INx and LHI pins are connected to battery in fail safe mode, it has to be ensured, that the maximum ratings of the device are not violated. Depending on the fail safe circuit, it could be necessary to use pull-down resistors at the INX and LHI pin. 4.3.4 Protection on Sense Pin (IS) The sense pin is an output pin which provides a current proportional to the load current of a selected channel. For protection, there is a clamp mechanism implemented which limits the maximum voltage on the sense pin. When sharing the same sense resistor with another device, it has to be ensured that the maximum ratings are not violated. Please refer to Chapter 9.2 for further information. Application Note 8 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Protection Functions 4.4 Overload Protection 4.4.1 General Protection Concept The BTS5482SF embeds an over load protection concept which is based on • • • • Over current threshold detection Over temperature detection in the power stage Dynamic temperature protection which considers a temperature gradient detection in the power stage Retry counter The over current threshold detection depends on the battery voltage as well as on the operating state. In the “Inrush state” at nominal battery conditions the over current threshold is set to the datasheet parameter IL(Htrip). At low battery conditions (VS ~ 5.7 V) the limit is reduced to IL(Ltrip). Once the device exits “Inrush state” and enters “Operative state” the over current threshold is reduced from IL(Htrip) to IL(Ltrip). Legend: OT ... Over Temperature E v ent DT ... Dy namic Temperature E v ent OC ... Over Current E v ent Fault (*) (*) ITCx bit will be cleared HWCR .CL =1b or OT /DT or OC LHI HWCR. CL=1b & TimerInrush ex pired or VS < VS( U V) or LHI & TimerInrus h expired OT/ DT or OC with n re try or OC at V D S(Vtri p ) Operative IL(Ltrip) , no retries (*) TimerInrus h E x pired or VS < VS( U V) TimerOn expired Inrush IL(Htrip), nretry S tartup S tate_Diagram _E N2.emf Figure 5 State Diagram BTS5482SF The protection mechanism for each channel of the device supports the following states: • • • Inrush state Operative state Fault state Application Note 9 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Protection Functions 4.4.2 Inrush State Whenever the device initializes (Power-ON reset, VS undervoltage reset) or the TimerInrush is expired, the device enters “Inrush state”. During “Inrush state” the BTS5482SF tries to drive the load even if an overcurrent condition occurs. The TimerOn for each channel is started when the channel is switched ON. Whenever an overload condition occurs the device switches OFF as soon as the threshold IL(Htrip) is exceeded and the TimerOn is reset. As long as a channel is in “Inrush state” and – – – – the maximum number of retries (nretry) is not exceeded over temperature condition (Tj > Tj(SC)-∆Tj) is not reached dynamic temperature condition is not reached the drain source voltage during switch ON condition does not exceed VDS(Vtrip) the device will do automatic restarts. As soon as one of the above listed conditions is exceeded the device will enter “Fault state”. To increase the device robustness at low VS condition, the device provides VS monitoring functionality. In case VS < VS(mon) the load current trip level is reduced to IL(Ltrip). In case IL > IL(Ltrip) the channel will restart until the maximum number of retries (nretry(LV)) is reached. If the undervoltage shut down occurs before current trip level is reached, the protection mechanism is reset and the channels are restart with the low current trip level IL(Ltrip). If this occurs after over current detection (e.g. due to oscillations on battery) the protection mechanism is reset and the channels are restart with the high current trip level IL(Htrip). To mitigate oscillations on the battery an adequate filtering on the battery supply is recommended. Inrush IN / OUTx Fault startup t VS VS(nor) V S(mon) Current trip level reduced due to VS undervoltage IL IL(Htrip) I L(Ltrip) nretry 0 ERR 1 2 3 4 * Latch off due to nretry ( LV) 31 32 * * ERR-flag will be reset by standard diagnosis readout during restart Figure 6 Undervoltage behavior of current trip level of BTS5482SF 4.4.3 Operative state t t t VS_undervoltage.emf The “Operative state” is entered whenever the "TimerOn" time of typical 10 ms is expired. As long as the device does not reach a condition which caused a mode transition from “Inrush state” to “Fault state”, “Operative state” will be entered. In “Operative state” the over current threshold is reduced to IL(Ltrip). Whenever an over load condition results in a current higher then IL(Ltrip) or an over temperature condition the device enters “Fault state”. “Inrush state” can be entered again whenever “TimerInrush” (typical 160 ms) is expired. TimerInrush is running as soon as the respective channel is deactivated (INx = 0 V or OUTL.OUTn = 0b) or the bit SCCR.ITCx is set. Application Note 10 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Protection Functions 4.4.4 Fault State “Fault state” is entered whenever a severe fault condition is observed – – – – – maximum number of retries exceeded over temperature condition reached dynamic temperature condition reached over current condition at high VDS is detected (IL≥IL(Vtrip)) over current condition in “Operative state” is detected (IL≥IL(Ltrip)) During “Fault state” the BTS5482SF remains latched OFF. “Fault state” can be exited by executing the clear latch command (HWCR.CL=1b), by activating the Limp Home, or by an undervoltage reset (VS < VS(UV)). Depending on the status of the TimerInrush, the device enters either “Inrush” or “Operative state”. • • When TimerInrush is expired, device enters “Inrush state” When TimerInrush is not expired, device enters “Operative state” Inrush Fault Operative IN / OUTx t VDS normal operation over current VDS(Vtrip ) IL IL(trip ) Switch off by over current switch off t over load removed Latch off due to over temperature Tj Tj(SC) Tj (SC) - ∆Tj Tj(start1) t n < n retry n =1 IIS t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart Figure 7 CL = 1 t CurrentTripping_OT .emf Latch due to Overcurrent shutdown Application Note 11 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Protection Functions 4.5 Overvoltage Protection BTS5482SF is protected against overvoltage on the battery line as well as on the outputs of the device. As long as the battery voltage stays below VS(CL) the output transistors are still operational. When switching OFF loads at high currents (e.g. short circuit condition), the inductance of the wire harness intends to continue driving the current. As a result the voltage at the outputs VOUT drops below ground potential. To prevent device destruction due to high voltages, there is a voltage clamp mechanism implemented, which limits the negative output voltage. 4.6 Undervoltage Behavior The device provides a stable behavior in undervoltage condition. The device is supplied by a battery supply (VS) and a logic supply (VDD). For an overview of the possible supply modes for the device please refer to the Chapter 5.1 in the datasheet. 4.6.1 VDD Undervoltage The VDD line is the supply for the SPI block of the device. If the voltage drops below VDD(PO) the SPI registers of the device are reset. In case INx = 0 V and LHI = 0 V all channels are deactivated and the standby mode is entered. As soon as the device enters the standby mode all errors and protection latches are cleared. In case limp home mode is activated (LHI = 5 V) or at least one channel is activated by a parallel input pin (INx = 5 V), the device will not enter the standby mode and the protection latches are not influenced by a VDD undervoltage event. To ensure a stable operation of the device, a stable VDD supply has to be ensured. In case a stable VDD supply cannot be guaranteed any more, the limp home mode of the device has to be activated. 4.6.2 VS Undervoltage In case VS drops below the undervoltage threshold which is typically in the range of 2.7 V the power stages are switched OFF. As long as VDD stays in the operating range, the SPI registers keep the information and the power stages will turn ON again as soon as VS is raising up again. To increase the device robustness at low VS condition, the device provides VS monitoring functionality, which is decreasing the load current trip level in case VS < VS(mon). See Chapter 4.4.2 for further information. Application Note 12 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Diagnosis 5 Diagnosis Note: All below stated diagnosis functions are valid for internal channels only. To support diagnosis requirements, the SPOC - BTS5482SF provides a current sense signal at the IS pin and the diagnosis word via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal is also enabled and disabled by an SPI command. A switch bypass monitor allows a short circuit detection between the output pin and the battery voltage. An integrated current source, switched via SPI, allows Open Load detection in OFF-state. 5.1 Diagnosis Functions Diagnosis Word in SPI The standard diagnosis register provides information about each channel. The error flags, an OR combination of the over temperature flags and over load monitoring signals, are provided in the standard diagnosis bits ERRn. The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via SPI. This is the case after each write command and after a dedicated read command for reading the standard diagnosis. The overtemperature flags, which cause an overheated channel to latch OFF, are latched directly at the gate control block. The same behavior is valid for the over current flags which cause a channel driving an excessive current to switch OFF. Those latches are cleared by SPI command HWCR.CL. Load Current Sense Diagnosis There is a current sense signal available at pin IS, providing a current proportional to the load current of a channel, which is selected via the current sense multiplexer. The sense signal is provided during ON-state as long no failure mode occurs. For more details (e.g. sense resistor, LED mode) please refer to the datasheet. Current Sense Offset Trimming One part of the KILIS inaccuracy is caused by the offset error of the internal operational amplifier which creates an offset on the sense current. To improve the accuracy the device provides the possibility to adjust the offset by 15 steps via SPI commands. The easiest way to perform this “calibration” is at the end of line test of the module. During the calibration, the sense current in Open Load condition is measured and trimmed until the current shows the lowest positive value. The setting of the calibration register (KILIS.OSTn) is stored in the µC and programmed at every start-up of the device. The other calibration method the device is providing is the calibration in the application. To support this function the device allows a state (calibration mode), where a current proportional to the offset of the OpAmp is provided to the sense pin. This state is activated by the SPI command ICR.CAL = 1b. With this reading the µC can reduce the offset by modifying the KILIS register. When calibration is finished, the command ICR.CAL = 0b has to be sent to exit the calibration mode. During calibration, the state of the current sense multiplexer should not be changed, otherwise the measurement could be affected. When performing the calibration in the application a proper software algorithm (e.g. averaging) has to used, since transients on the battery could influence the calibration. Switch Bypass Monitoring The switch bypass monitor compares the voltage across the power transistor (VDS) of a selected channel with the threshold VDS(SB). The channel is selected by the current sense multiplexer (DCR.MUX), whereas the result of the comparison can be read in the SPI register DCR.SBM or in the standard diagnosis. The SBM bit will be set as soon as VDS > VDS(SB). Application Note 13 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Diagnosis 5.2 Diagnosis Requirements Depending on the target application, switched load and OEM, there could be different requirements for diagnosis functions. A set of the typical diagnosis requirements for exterior lighting loads are shown in the following paragraphs. 5.2.1 Short Circuit to GND Detection In case a power output is shorted to GND, the current usually exceeds the current trip level of the device. As soon as the current trip level is reached, the device switches OFF the output and the error bit for the affected channel is set in the standard diagnosis. For this overload condition there are three cases to be considered: Short circuit current is reaching the high current trip level (IL > IL(Htrip)) Depending on the current state of the device, the device could allow a limited number of automatic restarts until the channel is latched OFF. During the automatic retries of the device, the error bits are cleared as soon as the standard diagnosis is transferred and is set again as soon as the channel reaches the trip level again. When a channel is latched OFF (“Fault state”), the respective error bit in the standard diagnosis cannot be cleared any more. To distinguish between a restarting and a latched channel, a consecutive reading of the standard diagnosis could be used (e.g. three times reading the standard diagnosis in a time frame < 200µs). Short circuit current between high and low current trip level (IL(Ltrip) < IL < IL(Htrip)) In case the affected channel is in “Inrush state”, the device is not reporting an error flag as long as the junction temperature Tj is not exceeding the thermal shut down temperature Tj(SC). As soon as t > tdelay(trip), the affected channel is entering the “Operative state”. In this state the device switches OFF the affected output and latches immediately because the low current trip level IL(Ltrip) is reached. The respective error bit in the standard diagnosis will be set. It is recommended to use the current sense diagnosis to detect this overload condition. Short circuit current stays below the low current trip level (IL <IL(Ltrip)) In this case the device is not reporting an error flag as long as the junction temperature Tj is not exceeding the thermal shut down temperature Tj(SC). It is recommended to use the current sense diagnosis to detect this overload condition and switch OFF the channel before an overtemperature condition is reached. 5.2.2 Short Circuit to Battery Detection Short Circuit to Battery Detection in ON-state When a short circuit to battery in ON-state occurs, the device is not reporting an error flag in the standard diagnosis, because the function of the device is not impacted. To fulfill this diagnosis requirement, the current sense diagnosis can be used. Due to the short circuit a part of the load current is supplied directly from battery which effects a lower current through the device. The current sense signal will show a lower reading which is interpreted by the micro controller as an Under Load or Open Load event. Short Circuit to Battery Detection in OFF-state In OFF-state the switch bypass monitoring could be used to detect this fault. Due to the short circuit to battery, the output voltage is close to battery. This means a small VDS whereas a high VDS would be expected. The µC could evaluate the SBM bit transferred in the standard diagnosis to detect this fault. Note: To distinguish between Short circuit to battery and Open Load in OFF-state an additional pull down resistor on the output is needed to compensate the output leakage of the device. Application Note 14 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Diagnosis 5.2.3 Open Load Detection Open Load detection in ON-state To detect an Open Load in ON-state the current sense signal could be used. In case of an Open Load, the reading of the current sense signal is much lower then expected. Open Load detection in OFF-state In OFF-state, the switch bypass monitoring in combination with the integrated current source could be used. The current source is switched in parallel to the DMOS and is activated by SPI (DCR.CSOL). The current level of this current source can be programmed in two steps (see 8.5.16 in the datasheet). In case of a disconnected load, the current causes the output voltage to raise up to battery voltage. By reading the SBM bit the µC can detect this fault. The timing, until the SBM bit is stable depends on the application circuit (e.g. capacitance on the OUT) and has to be evaluated in the application. The following procedure could be used: • • • • Select the dedicated channel with the multiplexer Enable the Open Load current with the DCR.CSOL bit Read the DCR.SBM or the standard diagnosis Disable the Open Load current with the DCR.CSOL bit Note: To distinguish between Short circuit to battery and Open Load in OFF-state an additional pull down resistor on the output is needed to compensate the output leakage of the device. Note: When using the current sense functionality for load current diagnosis, there are several parameters which are influencing the accuracy. Therefor when calculating the diagnosis thresholds, the whole system has to be included in the calculation. For detailed information on how the current sense diagnosis could be used, please refer to the Application Note - PROFET+ CURRENT SENSE - What the designer should know. Application Note 15 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Design optimization for improved EMC 6 Design optimization for improved EMC For an EMC optimized design, it is essential to place the recommended filter capacitors directly at the pin of the SPOC device. The reference potential for the filtering capacitors should be module GND. It is important that the GND connections have a very low impedance. Therefore a common GND plane would be recommended (see Figure 9). Figure 8 shows a simplified schematic with included capacitors in order to improve the EMC behavior. The capacitors are highlighted with a green rectangle. Vbat 5V 100nF 500Ω 100nF WD-OUT VDD VCC GPIO 8kΩ IN1 GPIO 8kΩ IN2 VS IN3 OUT0 IS AD 27W OUT3 1nF 10W GND µC 10nF 10nF 10nF 10nF e.g. XC 2267 SPI 65W OUT2 2.7kΩ 2µF 65W OUT1 1kΩ VDD 3.9kΩ CS 3.9kΩ SCLK 3.9kΩ SO 3.9kΩ SI SPI LHI 8kΩ WD-OUT 100nF 10kΩ IN0 VSS external driver EDO0 control EDD0 EDO1 EDD1 GND IN1 VS PROFET OUT0 Ch0 DEN DSEL IS PROFET OUT1 Ch1 GND 10nF 10nF 10Ω EMC_EXT .emf Figure 8 BTS5482SF EMC Schematic For BTS5482SF the following capacitance values showed good results in our EMC investigations. • • VS: 100 nF (Figure 9 - C1_VS) OUTx: 10 nF (Figure 9 - C0 ... C3) The capacitors which were used in our tests were 0805 X7R types. For EMC purposes it is not only the value of the components which influences the behavior of the system, but also the placement of these components. Therefore, it is important that the board layout is optimized for EMC. Figure 9 shows an example of an EMC optimized layout. Application Note 16 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Design optimization for improved EMC Vias are connected to a common GND plane (dashed line) Layout_proposal.emf Figure 9 Layout proposal It is acknowledged that it is not always possible to do the layout in exactly this way, but basic rules for an EMC optimized layout should be considered: • • • • Place the EMC capacitors as close as possible to the device pins. Ensure a low impedance connection of EMC capacitors to the module GND. The routing of SPI lines should be as short as possible, with no layer changes if possible. Routing of GND lines in parallel to the SPI lines for shielding purpose. Note: The above mentioned values for filtering capacitances are recommended values which showed good EMC results in our test setup. Depending on the board layout it could be necessary to adjust this values for an optimized EMC performance. The report of our EMC investigations is available and is provided on request. Application Note 17 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Software Implementation 7 Software Implementation 7.1 Basic software requirements A basic approach for a robust software implementation is to assume that over a period of time the content of some registers is changed unintentionally. To address this issue the following measures can be used: • • • Refresh routines Check and restore routines Error debouncing routines 7.1.1 Refresh routines Software is periodically updating registers which are needed for a proper operation. If it’s possible from software timing point of view, it is also recommended to update registers, which are not used in the application but could have an impact to the correct operation of the device. (e.g. if the current sense offset trimming is not used, it is recommended to check if the KILIS register is not changed unintentionally) 7.1.2 Check and restore routines Software is periodically verifying the content of the used registers at a minimum. In case of a mismatch from the read to the expected value, the device is reprogrammed. 7.2 Error debouncing routines In the BTS5482SF there is digital and analog information available to monitor the status of the device. In case software is using error bits of the device to react to an overload condition, it’s recommended to use a debouncing routine. For this reason, an error counter could be implemented which is incremented in case an error bit is read, and decremented in case standard diagnosis is reporting no errors. At a certain value, the counter gets an overflow and software reacts to the fault condition. By changing the value for incrementing and decrementing, the strength of the filtering can be adjusted. The same approach can be used for the analog reading of current sense values. With a consecutive reading, a wrong value due to noise on the battery could be filtered. 7.3 Routine to improve device robustness in overload condition When the device is in Inrush state, a maximum of 32 automatic restarts at high current trip level is provided. The short circuit tests are done according the AEC standard where only the hardware protections of the device are used. To increase the robustness of the device, a software routine could be implemented, which is disabling the channel after a few retries. These retries could be detected and counted by using the error bit information in the standard diagnosis. Application Note 18 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 8 Thermal behavior The thermal performance of a device is one of the most frequent topics tackled by developers during the concept phase. Indeed, it influences in a significant way the power-loss balance and the selection of device RDS(ON) class. Nevertheless, thermal performance also depends on PCB type and on dissipation surface used on the application, as well as the time. In other words, it is also determined by parameters outside of the device. This chapter focuses on the Thermal Cauer Ladder Model and on the Thermal Foster Model for BTS5482SF. Those networks are only valid for the boundary conditions considered. 8.1 Thermal Cauer & Foster Networks The Cauer Network model describes the thermal behavior with an equivalent electrical network. This modeling helps in determining dynamic and static thermal behavior. The Foster network is an equivalent thermal Network to Cauer allowing one simple mathematical solution. 8.1.1 Cauer equivalent thermal network The PCB thermal Network can be simulated by an equivalent electrical schematic. The power dissipated into the device and PCB has the same behavior as a current flowing through resistances and capacitances. This power flows into thermal resistances and thermal capacitances. Thermal resistances correspond to thermal behavior in steady state and thermal capacitances are added to simulate the transient phases. Figure 10 sketches the equivalent electrical network to thermal behavior. It is called the Thermal Cauer Network. RC_THi and CC_THi represent respectively Cauer thermal resistances and capacitances. TJ R C_TH1 RC_TH2 RC_TH3 R C_TH4 R C_TH5 RC_TH6 R C_TH7 R C_TH8 C C_TH1 C C_TH2 CC_TH3 C C_TH4 C C_TH5 CC_TH6 C C_TH7 C C_TH8 Tamb RC_network.emf Figure 10 BTS5482SF Thermal Cauer Network Table 2 shows correspondences between thermal and electrical quantities. Table 2 Thermal / Electrical model equivalence Thermal parameter Equivalent electrical parameter Symbol Unit Parameter Symbol Unit Parameter P W Power losses into the junction I A Current T ΔT °C Temperature of one layer U V Potential K Delta of temperature U V Voltage RTH K/W Thermal resistance R Ω Resistance CTH Ws/K Thermal capacitance C F Capacitance Application Note 19 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 8.1.2 BTS5482SF Cauer Network For the BTS5482SF in package PG-DSO-36-43, Cauer Networks have been determined by simulation. The concept for this determination is introduced below, followed by a presentation of the Cauer Network concept. 22.214.171.124 Cauer Network determination process Cauer models are based on finite element analysis. In the finite element tool, the different layers of the BTS5482SF integrated on a PCB are conceptualized: BTS5482SF package (die, glue, lead frame, heat-slug, etc), soldering paste on PCB and PCB type. Based on these models, simulation results provide system thermal impedance curves. Ambient temperature and power losses dissipated by the BTS5482SF also play a role in the finite element simulation. The Cauer Ladder Network is obtained from thermal impedance curves through simulations fitted to real measurements. Simulations have been run to obtain 7 or 8 (RTH, CTH) subdivisions for a Cauer Network as shown in Figure 10. This determination process is shown in Figure 11. Finite Element Simulation Thermal impedance curves ZTHij FIT with measurements Cauer models ZTHij Process .emf Figure 11 Cauer Network determination concept Application Note 20 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 126.96.36.199 Convention For a quad channel device, different types of thermal impedance curves and Cauer Ladder Networks are obtained: • • • • • • • • • • Thermal impedance curves and (RTH, CTH) Network for channel 0 if channel 0 is heated Thermal impedance curves and (RTH, CTH) Network for channel 0 if channel 1 is heated Thermal impedance curves and (RTH, CTH) Network for channel 0 if channel 2 is heated Thermal impedance curves and (RTH, CTH) Network for channel 0 if channel 3 is heated Thermal impedance curves and (RTH, CTH) Network for channel 1 if channel 0 is heated Thermal impedance curves and (RTH, CTH) Network for channel 1 if channel 1 is heated Thermal impedance curves and (RTH, CTH) Network for channel 1 if channel 2 is heated Thermal impedance curves and (RTH, CTH) Network for channel 1 if channel 3 is heated ... Thermal impedance curves and (RTH, CTH) Network for channel 3 if channel 3 is heated In other words, in Cauer Ladder models, two types of information are considered by channel: the self-heating of channel and the influence of one heated channel to another. For quad channel devices, sixteen thermal impedance curves and Cauer ladder Networks are necessary. Note: The heat of a channel is induced by power losses when this channel conducts. In this application note, the following conventions are considered: • ZTH, ij defines the thermal impedance curve of channel i if channel j is heated • Cauer ij defines Cauer Ladder Network as sketched in Figure 10 of channel i if channel j is heated • i and j are integer from 0 to 3 188.8.131.52 Cauer Network concept Cauer Ladder Networks help to determine junction temperature TCHi of channel i for i = 0 to 3. To simulate device thermal behavior, four (RTH, CTH) Networks - one Cauerii and three Cauerij - have to be built. Simulation tools like PSpice can be used. First, Cauerii determines self-heated junction temperature TChi,i of channel i. Then 3 networks Cauerij quantify the influence of channel j on channel i through junction temperature TChi,j, where j = 0 to 3 and j ≠ i. Channel i junction temperature is the sum of TChi,i and TChi,j, where j = 0 to 3 and j ≠ i. The (RTH, CTH) Cauerij Networks are shown in Figure 12 where i = j and i ≠ j for (i, j) = 0 to 3. R C_TH1i,j TCHi,j RC_TH2i,j R C_TH3i,j R C_TH4i,j RC_TH5i,j R C_TH6i,j CC_TH2i,j C C_TH4i,j C C_TH5i,j C C_TH6i,j R C_TH7i,j RC_TH8i,j Pj CC_TH1i,j CC_TH3i,j C C_TH7i,j C C_TH8i,j Tamb Cauer.emf Figure 12 Cauer Ladder Network of channel i if channel j is heated The BTS5482SF Thermal Cauer Networks Cauerii and Cauerij where i and j can be 0, 1, 2 or 3 are provided on Chapter 8.2 for several PCB types. Application Note 21 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 184.108.40.206 Mathematical expression For mathematical expression, delta of temperature ∆TCHi is considered instead of junction temperature TCHi. The following equation links both parameters. (1) TCHi = ΔTCHi + Tamb As introduced in Figure 12, the Cauer Ladder responses are determined through power losses Pj. Power losses are time dependent. Therefore, delta of temperature ∆TCHi and Cauer Ladder Network Cauerij are also time dependent. Then, if the four channels are heated, the increase of temperature can be determined by the following equations: TCH 0 ( t ) = Δ T00 ( P0 ( t ), t ) + Δ T01 ( P1 ( t ), t ) + Δ T02 ( P2 ( t ), t ) + Δ T03 ( P3 ( t ), t ) (2) TCH 1 ( t ) = Δ T10 ( P0 ( t ), t ) + Δ T11 ( P1 ( t ), t ) + Δ T12 ( P2 ( t ), t ) + Δ T13 ( P3 ( t ), t ) (3) TCH 2 ( t ) = Δ T20 ( P0 ( t ), t ) + Δ T21 ( P1 ( t ), t ) + Δ T 22 ( P2 ( t ), t ) + Δ T 23 ( P3 ( t ), t ) (4) TCH 3 ( t ) = Δ T30 ( P0 ( t ), t ) + Δ T31 ( P1 ( t ), t ) + Δ T32 ( P2 ( t ), t ) + Δ T33 ( P3 ( t ), t ) (5) Where ΔTCHi (t ) Delta of temperature of channel i Pi (t ) Power losses of channel i Δ T ij ( P j ( t ), t ) Temperature increase of channel i if channel j is heated with power Pj(t) or Temperature response of Cauer Network Cauerij if power profile Pj(t) is applied The Mathematical expression ∆Tij(Pj(t),t) defined during time τ is: Δ Tij ( P j ( t ), t = ∫ τ . 0 Ζ . THij ( t − τ ) ⋅ P j (τ ) d τ = Ζ THij ( t ) ∗ P j ( t ) (6) Where Convolution symbol used as convention in this application note * Ζ THij Thermal impedance of channel i if channel j is heated (Unit step response). Note: Graphical expression of ZTHij is with thermal impedance curves. If the channel j is switched OFF, Pj is null. As Junction temperature TCHi, i is considered to be equal to Tamb at t = 0, temperature increase ∆Tij(Pj(t),t) is also null. Matrix representation can be built based on those equations: ⎛ Δ TCH 0 ⎞ ⎜ ⎟ ⎜ Δ TCH 1 ⎟ ⎜ ΔT ⎟= ⎜ CH 2 ⎟ ⎜ ΔT ⎟ ⎝ CH 3 ⎠ ⎡. ⎢ Ζ. TH 00 (t ) ⎢ Ζ TH 10 (t ) ⎢. ⎢ Ζ TH 20 (t ) ⎢. ⎢⎣ Ζ TH 30 (t ) Application Note . Ζ TH 01 (t ) . Ζ TH 11 (t ) . Ζ TH 21 (t ) . Ζ TH 31 (t ) . Ζ TH 02 (t ) . Ζ TH 12 (t ) . Ζ TH 22 (t ) . Ζ TH 32 (t ) . ⎤ Ζ TH 03 (t ) ⎥ ⎛ P0 (t ) ⎞ ⎜ ⎟ . Ζ TH 13 (t ) ⎥ ⎜ P1 (t ) ⎟ ⎥ ∗⎜ . ⎟ Ζ TH 23 (t ) ⎥ ⎜ P2 (t ) ⎟ ⎥ ⎜ P (t ) ⎟ . Ζ TH 33 (t ) ⎥⎦ ⎝ 3 ⎠ 22 (7) Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 8.1.3 BTS5482SF Foster Network Cauer networks are of interest because in the thermal world, they are the natural representation of the physics. Nodes store energy, represented by capacitors to ground, and heat flowing between nodes is represented by resistors. Unfortunately, although those (RTH, CTH) subdivisions are easy to draw, the analysis of a Cauer Network might become harder with basic tools. It can be simulated through “PSpice” tool for instance but a license would be required. The Foster Ladder is an equivalent thermal network to the Cauer. It sketches the mathematical description of ZTHij curves. This network is shown in Figure 13. The electrical equivalence provided in Table 2 can also be applied to this network. CF_THn and RF_THn represent respectively thermal capacitance and resistance of node n in the Foster Network. TJ C F_TH1 C F_TH2 RF_TH1 R F_TH2 C F_TH3 R F_TH3 CF_TH4 RF_TH4 C F_TH5 C F_TH6 R F_TH5 R F_TH6 CF_TH7 RF_TH7 C F_TH8 RF_TH8 Tamb Foster.emf Figure 13 Thermal Foster Network The implementation and the analysis of the Foster Network is easier. If a constant power is applied to the network, the response of the end node is merely the sum of each node response, based on exponentially terms, as follows: ΔTCH = P ⋅ ∑k =1 RF _ TH ,k ⋅ (1 −e −t /τ k ) n (8) Where ΔTCH Delta of temperature P Power losses n Number of Foster nodes R F _ TH , k Thermal resistance of node k in Foster Network τk RC constant of node k in Foster Network Note: Equation (8) is only valid if constant power is applied. Applied to BTS5482SF, the solutions to Foster Networks are: = ∑ 3 Δ T CH 1 = ∑ 3 Δ T CH = ∑ 3 2 Δ T CH = ∑ 3 3 Δ T CH 0 j=0 j=0 j=0 j=0 Application Note [∑ [∑ [∑ [∑ n k =1 n k =1 n k =1 n k =1 [R (1 − e − t /τ 0 [R (1 − e − t /τ 0 [R (1 − e − t /τ 0 [R (1 − e − t /τ 0 j ,k 0 j ,k (9) )]⋅ P ] (10) )]⋅ P ] (11) )]⋅ P ] (12) j j ,k 1 j ,k j j ,k 2 j ,k 3 j ,k )]⋅ P ] j j ,k j 23 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior Where ΔTCHi Delta of temperature of channel i Pj Power losses of channel i n Number of Foster nodes R ij , k Foster thermal resistance of node k for channel i if channel j is heated τ Foster RC constant of node k for channel i if channel j is heated ij , k i, j Defined as integer from 0 to 3 Note: Power losses Pi of channel i are considered as constant. Foster Thermal Network quantities Rij,k and τij,k where i and j can be 0, 1, 2 or 3 are provided on Chapter 8.2. Application Note 24 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 8.2 Simulation results One type of PCB has been considered to build Thermal Cauer and Foster Networks: 2s2p PCB. Note: The Cauer and Foster ladder (R,C) networks must not be considered for times below or equal to 100µs. 8.2.1 Cauer Network mathematical interpretation This paragraph contains instructions on how to use the Cauer Models to calculate channel temperatures. Cauerij represents the Cauer (RTH, CTH) Networks and can be used to determine the temperature increase ∆Tij of channel i if channel j is heated. For a channel i, the total temperature increase ∆TCHi is the sum of all ∆Tij. For the BTS5482SF, this sum is expressed as follow: ΔTCHi = ∑ j =0 ΔTij 3 (13) And the junction temperature as: TCHi = ∑ j =0 ΔTij + Tamb 3 (14) As an example, the junction temperature of channel 0 is obtained with following expression: T CH 0 = Δ T 00 + Δ T 01 + Δ T 02 + Δ T 03 + T amb (15) Where ∆T00, ∆T01, ∆T02 and ∆T03 are the temperature increases determined respectively with Cauer00, Cauer01, Cauer02 and Cauer03 Networks. As channels are symmetric for the BTS5482SF, the following Cauer Networks are equal: Cauer 00 = Cauer 11 (16) Cauer 01 = Cauer 10 (17) Cauer 02 = Cauer 13 (18) Cauer 03 = Cauer 12 (19) Cauer 20 = Cauer 31 (20) Cauer 21 = Cauer 30 (21) Cauer 22 = Cauer 33 (22) Cauer 23 = Cauer 32 (23) Application Note 25 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 8.2.2 Foster Network mathematical interpretation This paragraph contains instructions on how to use the Foster equations to determine channel temperatures. As for the Cauer Networks Cauerij, Foster Networks are composed of (RTH_F, CTH_F) Networks. Those networks and their mathematical solutions can be used to determine the temperature increase ∆Tij of channel i if channel j is heated. For a channel i, the total temperature increase ∆TCHi is the sum of all ∆Tij. For the BTS5482SF, this sum is expressed as follows: ΔTCHi = ∑j =0 ΔTij 3 (24) And the junction as: TCHi = ∑j=0 ΔTij +Tamb 3 (25) As an example, the junction temperature of channel 0 is obtained with following expression: Δ T CH 0 = ∑ 3 j=0 [∑ [R ⋅(1 − e n −t /τ 0 )]⋅ P ] j ,k 0 j ,k k =1 (26) j Where Δ T 00 = ∑ n Δ T 01 = ∑ n Δ T 02 = ∑ n Δ T 03 = ∑ n k =1 k =1 k =1 k =1 [R 00 , k ⋅1− e [R 01 , k ⋅1− e [R 02 , k ⋅1− e [R 03 , k ⋅1− e ( − t / τ 00 , k ( − t / τ 01 , k ( − t / τ 02 , k ( − t / τ 03 , k )]⋅ P (27) 0 )]⋅ P (28) )]⋅ P (29) )]⋅ P (30) 1 2 3 In this Foster equation, the RC constant τk of node k is expressed as: τ k = RF _ TH ,k ∗ CF _ TH ,k (31) Where RF _ TH ,k Thermal resistance of node k in the Foster Network CF _ TH ,k Thermal capacitance of node k in the Foster Network Note: The Foster equation is only valid if constant power is applied. Application Note 26 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior As channels are symmetric for the BTS5482SF, the following simplification can be applied: R 00 , k = R11 , k (32) R 01 , k = R10 , k (33) R 02 , k = R13 , k (34) R 03 , k = R12 , k (35) R 20 , k = R 31 , k (36) R 21 , k = R 30 , k (37) R 22 , k = R 33 , k (38) R 23 , k = R 32 , k τ 00 , k = τ 11 , k (39) τ 01 , k = τ 10 , k (40) τ 02 , k = τ 13 , k (41) τ 03 , k = τ 12 , k (42) τ 20 , k = τ 31 , k (43) τ 21 , k = τ 30 , k (44) τ 22 , k = τ 33 , k (45) τ 23 , k = τ 32 , k Application Note 27 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 8.2.3 2s2p PCB Figure 14 and Figure 15 show 2s2p PCB details, i.e. footprint on topside and details of solder area on topside. An ambient temperature of 25°C and power dissipations of 0.4 W on channels 0 and 1 and 0.2 W on channels 2 and 3 have been considered. Figure 16 provides the PCB vertical section. Channel 0 Cauer and Foster networks if channel 0 is heated are provided on Table 3. It describes Cauer00 and Foster00. Channel 0 Cauer and Foster networks if channel 1 is heated are provided on Table 4. It describes Cauer01 and Foster01. Channel 0 Cauer and Foster networks if channel 2 is heated are provided on Table 5. It describes Cauer02 and Foster02. Channel 0 Cauer and Foster networks if channel 3 is heated are provided on Table 6. It describes Cauer03 and Foster03. Channel 2 Cauer and Foster networks if channel 0 is heated are provided on Table 7. It describes Cauer20 and Foster20. Channel 2 Cauer and Foster networks if channel 1 is heated are provided on Table 8. It describes Cauer21 and Foster21. Channel 2 Cauer and Foster networks if channel 2 is heated are provided on Table 9. It describes Cauer22 and Foster22. Channel 2 Cauer and Foster networks if channel 3 is heated are provided on Table 10. It describes Cauer23 and Foster23. 2s2p_detail.emf 2s2p_footprint.emf Figure 14 2s2p footprint (Topside) Figure 15 2s2p details of solder area (Topside) 70µm modelled (traces) 1.5 mm 35µm, 90% metallization* 35µm, 90% metallization* 70µm, 5% metallization * * Percentual Cu metallization on each layer Figure 16 2s2p_cross_section.emf Cross Section (JEDEC 2s2p) Application Note 28 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior Table 3 Channel 0 Cauer and Foster networks if channel 0 heated for 2s2p PCB Cauer Ladder Foster Ladder Step RC_TH00 [K/W] CC_TH00 [Ws/K] RF_TH00 [K/W] CF_TH00 [Ws/K] 1 0.501 0.0013 0.3374 0.0019 2 1.117 0.0056 0.6593 0.0092 3 2.276 0.0179 1.6843 0.0266 4 5.142 0.0750 3.3100 0.1148 5 10.981 0.2630 10.3824 0.3428 6 7.240 2.6263 8.9280 2.1967 7 6.841 25.0709 8.6327 22.1462 8 0.415 2125.8800 0.6781 1293.7580 Table 4 Channel 0 Cauer and Foster networks if channel 1 heated for 2s2p PCB Cauer Ladder Foster Ladder Step RC_TH01 [K/W] CC_TH01 [Ws/K] RF_TH01 [K/W] CF_TH01 [Ws/K] 1 1.073 0.0106 0.3361 0.0260 2 2.191 0.0245 1.1729 0.0432 3 4.528 0.0719 2.6006 0.1227 4 9.157 0.2153 6.5569 0.3348 5 6.829 1.1344 10.4760 0.9250 6 6.829 11.3326 6.6281 11.1197 7 2.773 94.7811 5.3379 60.2542 8 0.081 24379.0300 0.1534 10603.7300 Table 5 Channel 0 Cauer and Foster networks if channel 2 heated for 2s2p PCB Cauer Ladder Foster Ladder Step RC_TH02 [K/W] CC_TH02 [Ws/K] RF_TH02 [K/W] CF_TH02 [Ws/K] 1 1.648 0.0170 0.2478 0.0360 2 2.648 0.0316 1.2388 0.0405 3 5.067 0.0937 2.8123 0.1120 4 9.003 0.2892 6.1755 0.3541 5 5.853 1.8855 10.4205 0.9292 6 6.202 13.2833 6.5639 11.3432 7 2.450 103.5901 5.3934 58.8746 8 0.116 14388.8900 0.1253 15935.7600 Application Note 29 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior Table 6 Channel 0 Cauer and Foster networks if channel 3 heated for 2s2p PCB Cauer Ladder Foster Ladder Step RC_TH03 [K/W] CC_TH03 [Ws/K] RF_TH03 [K/W] CF_TH03 [Ws/K] 1 0.770 0.0018 0.5977 0.0042 2 1.617 0.0057 1.2841 0.0139 3 3.250 0.0262 2.3500 0.0511 4 7.629 0.1285 4.3067 0.2069 5 11.043 0.5421 12.0814 0.5129 6 8.764 11.7535 6.8645 6.6012 7 1.621 244.3760 6.9747 37.1682 8 - - 0.1921 10280.5300 Table 7 Channel 2 Cauer and Foster networks if channel 0 heated for 2s2p PCB Cauer Ladder Foster Ladder Step RC_TH20 [K/W] CC_TH20 [Ws/K] RF_TH20 [K/W] CF_TH20 [Ws/K] 1 2.131 0.0403 0.1231 0.2428 2 2.740 0.0457 1.6138 0.0870 3 4.933 0.1107 4.2256 0.2243 4 7.917 0.2903 12.0728 0.5158 5 5.424 1.9400 6.9254 6.6178 6 5.550 11.6189 6.7804 38.9100 7 3.091 61.7051 0.2013 8381.0300 8 0.290 2923.1310 - - Table 8 Channel 2 Cauer and Foster networks if channel 1 heated for 2s2p PCB Cauer Ladder Foster Ladder Step RC_TH21 [K/W] CC_TH21 [Ws/K] RF_TH21 [K/W] CF_TH21 [Ws/K] 1 0.188 0.0036 0.2769 0.0348 2 0.581 0.0106 1.0508 0.0504 3 2.143 0.0194 2.5806 0.1265 4 4.939 0.0732 6.2696 0.3526 5 10.798 0.2720 10.4111 0.9254 6 7.069 2.6582 6.5693 11.2469 7 6.893 24.7956 5.4166 58.1673 8 0.361 2620.6110 0.1525 12806.0200 Application Note 30 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior Table 9 Channel 2 Cauer and Foster networks if channel 2 heated for 2s2p PCB Cauer Ladder Foster Ladder Step RC_TH22 [K/W] CC_TH22 [Ws/K] RF_TH22 [K/W] CF_TH22 [Ws/K] 1 0.852 0.0002 0.4728 0.0002 2 1.217 0.0006 1.2969 0.0007 3 2.014 0.0051 1.4882 0.0065 4 3.454 0.0247 2.8852 0.0304 5 7.796 0.1277 5.3461 0.1831 6 11.080 0.5597 13.1013 0.5967 7 8.775 11.5410 8.9640 10.9201 8 1.736 233.6499 3.2065 139.4895 Table 10 Channel 2 Cauer and Foster networks if channel 3 heated for 2s2p PCB Cauer Ladder Foster Ladder Step RC_TH23 [K/W] CC_TH23 [Ws/K] RF_TH23 [K/W] CF_TH23 [Ws/K] 1 1.139 0.0134 0.4189 0.0185 2 2.126 0.0155 1.4895 0.0335 3 4.932 0.0720 2.8840 0.1093 4 10.584 0.2843 6.1348 0.3576 5 7.180 2.6349 10.3315 0.9409 6 6.784 25.2113 6.5901 11.2681 7 0.402 2203.2350 5.4130 58.2187 8 - - 0.1680 10683.4700 Application Note 31 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior Annex: Cauer Network vs. PCB type One question frequently asked when considering the Cauer Ladder Network is correspondence between Cauer step and the device and PCB physical layers. However, there is no correlation between Cauer (RTH, CTH) stages and layers of the physical thermal system. Finite element simulations have been run by considering 8 (RTH, CTH) iterations. Each subdivision might represent only a part of a layer or even several layers. Nevertheless, based on knowledge of the physical thermal system, a name has been put on the different Cauer Ladder layers. This is just an approximation without any physical reality. This correspondence is introduced in Table 11 for 2s2p PCBs. Table 11 Step Cauer Ladder layers for a 2s2p PCB Layer 1 Die 2 Glue 3 Lead frame 4 Pins 5 Soldering paste 6 PCB 7 Thermal vias & intermediate copper layers 8 Bottom copper layer to air Application Note 32 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Thermal behavior 8.2.4 Thermal impedance curves Figure 17 and Figure 18 give thermal impedance curves with semi and logarithmic scales respectively for a 2s2p PCB with thermal via holes. Those figures assume all channels are activated and the following power applied: Channel 0 0.4 W Channel 1 0.4 W Channel 2 0.2 W Channel 3 0.2 W Two types of data are shown in the following figures: Thermal impedance curve for an ambient temperature of 25°C and 85°C. ZTHJA_semi_logarithmic.emf Figure 17 BTS5482SF ZTHJA curves for 2s2p PCB (semi logarithmic scale) ZTHJA_full_logarithmic.emf Figure 18 BTS5482SF ZTHJA curves for 2s2p PCB (full logarithmic scale) Application Note 33 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Appendix 9 Appendix 9.1 Calculation of series resistor for reverse battery case As described in Chapter 4, series resistors have to be placed to protect the device and to avoid that the maximum ratings of the device are exceeded. 9.1.1 BTS5482SF with a PROFET+ connected to the external drive Figure 3 show the possible current paths during reverse battery condition. In case a reverse protected voltage regulator is used, the possible current paths are reduced. Figure 19 show the current paths which have to be considered in this case. To calculate the needed series resistors, the maximum ratings from the datasheet have to be considered. In this calculation example the SPOC - BTS5482SF is controlling a 2-channel PROFET+ - BTS5020-2EKA. VBAT Ire v 0V VDD 100nF VS IN1 IN2 IN3 OUT0 IS OUT1 OUT2 LHI Ire v Irev OUT3 WD-OUT 8kΩ SPI 100nF 8V VS Irev Dx OUTx GND Ire v Ire v Ir ev Irev Ire v Irev Ire v EDO x INx Ire v Irev EDDx 8V Irev Ire v Ir ev 10kΩ Irev IS 2.7kΩ Ir ev Irev GND 10Ω 14V Calculation_PROFET +.emf BCM GND Figure 19 Application diagram with current paths during reverse battery Application Note 34 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Appendix For the calculation the Maximum Ratings for the used devices have to be considered: SPOC FL EN2: Profet+: IEDDx_max: 1 mA (for t ≤ 2 min) IEDOx_max: 1 mA (for t ≤ 2 min) IGND_max: 25 mA (for t ≤ 2 min) ILHI_max: 2 mA (for t ≤ 2 min) IIS_max = 8 mA (for t ≤ 2 min) VIN_max: 7 V (for t < 2 min) VDEN_max: 7 V (for t < 2 min) VDSEL_max: 7 V (for t < 2 min) IIN_max: 2 mA IDEN_max: 2 mA IDSEL_max: 2 mA IIS_max = 25 mA For all diodes a forward voltage drop of 700mV is considered. Reverse battery voltage VREV = 14V. Calculation of voltage drop on the series resistor at EDDx and EDOx: Vseries = 14 - 0.7 - 7 - 0.7 = 5.6 V Calculation of series resistor value: (The resistor in the GND of the SPOC could be neglected in the calculation) Rseries = Vseries / IEDxx = 5.6 V / 1 mA = 5.6 kΩ Calculation of voltage drop on the series resistor at IS Vseries = 14 - 0.7 - 8 - 0.7 = 4.6 V Calculation of series resistor value: (The resistor in the GND of the SPOC could be neglected in the calculation) Rseries = Vseries / IEDxx = 4.6 V / 8 mA = 575 Ω For each EDD and EDO pin of the SPOC series resistors of > 5.6 kΩ are needed to not exceed maximum ratings for a reverse battery case of -14 V. A series resistors of > 575 Ω is needed to not exceed maximum ratings for a reverse battery case of -14 V. This is the minimum value which could be used for reverse battery case. The final value for this resistor is also depending on the value of the sense resistor itself. See Chapter 9.2 for more details. Application Note 35 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Appendix 9.1.2 BTS5482SF and BTS54220-LBE sharing SPI pins When using the SPI concept in an application, usually several devices are sharing SPI lines to save µC I/Os. Depending on the SPI concept, the devices could be connected in “independent slave” configuration (see Figure 20) or in “daisy chain” configuration (see Figure 21). Both configurations give some benefits to the application, but when dimensioning the series resistors for device protection, some attention has to be spent for the reverse battery case. There are multiple current paths in reverse battery condition which have to be considered when dimensioning the series resistors. Basically the current paths for all the logic pins are the same. As soon the voltage at a logic pin is exceeding the maximum rating, the zener diode of ESD protection starts conducting. 220.127.116.11 BTS5482SF and BTS54220-LBE in Independent Slave SPI configuration Figure 20 shows the current paths which have to be considered when dimensioning the series resistors in reverse battery condition. VBAT 0V LDO µ-Controller Irev MSI/MSO Irev Irev MO1 Irev Irev MCS2 Irev Irev MCS1 Irev Irev Irev VDD VS RVDD2 RSI2/RSO2 RCS2 RSCLK2 RVDD1 RSCLK1 RSI1/RSO1 RCS1 BTS54220 -LBE SPOC2 VS BTS5482SF SPOC1 GND Irev Irev Irev Irev VDD VDD Irev SI/SO OUT1 SI/SO SCLK OUT2 OUT0 SCLK CS OUT1 CS OUT3 OUT4 OUT2 Irev Irev 100 nF Irev Irev 100 nF Irev Irev Irev Irev OUT3 GND GND I rev 14V BCM GND Figure 20 10 Ohm 1kΩ SPI_Independent_Slave.emf SPOC FL EN2 and SPOC+ in Independent Slave SPI configuration For the calculation the Maximum Ratings for the used devices have to be considered: SPOC FL EN2: SPOC+: IVDD_max: 25 mA (for t ≤ 2 min) IGND_max: 25 mA (for t ≤ 2 min) ISI_max: 2 mA (for t ≤ 2 min) ISO_max: 2 mA (for t ≤ 2 min) ISCLK_max: 2 mA (for t ≤ 2 min) VDD_max: 5.5 V VSI_max: 6 V VSO_max: 6 V VSCLK_max: 6 V IDD_max: 12 mA ISI_max: 2 mA ISO_max: 2 mA ISCLK_max: 2 mA Application Note 36 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Appendix For all diodes a forward voltage drop of 700mV is considered. Reverse battery voltage VREV = 14V. Calculation example for SI, SO and SCLK There are 2 current paths which have to be considered: From GND of SPOC1 through SPOC2 to VS and from GND of µC through SPOC2 to VS. SPOC1 to SPOC2: Vseries = 14 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 6.6 V / 2 mA = 3.3 kΩ µC to SPOC2: Vseries = 14 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 6.6 V / 2 mA = 3.3 kΩ Calculation example for VDD There are 2 current paths which have to be considered: From GND of SPOC1 through SPOC2 to VS and from GND of µC through SPOC2 to VS. SPOC1 to SPOC2: Vseries = 14 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 6.6 V / 12 mA = 550 Ω µC to SPOC2: Vseries = 14 - 0.7 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 5.9 V / 12 mA = 492 Ω For SI, SO and SCLK pin of the SPOC a series resistors of > 3.3 kΩ is needed to not exceed maximum ratings for a reverse battery case of -14 V. For the VDD pin a series resistance of >550 Ω is needed between the two SPOC devices. From µC to each SPOC a series resistor of >492 Ω has to be placed to not exceed maximum ratings for a reverse battery case of -14 V. Application Note 37 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Appendix 18.104.22.168 BTS5482SF and BTS54220-LBE in Daisy Chain SPI configuration Figure 21 shows the current paths which have to be considered when dimensioning the series resistors in reverse battery condition. VBAT 0V LDO I rev Irev Irev VDD MO MCS/SCLK I rev Irev I rev I rev Irev MI Irev VS RSO2 RVDD2 VS BTS5482 SF SPOC1 RSI2 BTS54220 -LBE SPOC2 RCS2/RSCLK2 RSO1 RSI1 RVDD1 RCS1/RSCLK1 µ-Controller Irev GND Irev Irev Irev Irev VDD SO VDD OUT2 CS/SCLK OUT0 SI OUT3 OUT1 CS/SCLK OUT4 Irev Irev Irev Irev I rev 100 nF I rev OUT3 100 nF I rev OUT2 I rev Irev OUT1 SI SO GND GND I rev 14V BCM GND Figure 21 10 Ohm 1kΩ SPI_Daisy_Chain.emf SPOC FL EN2 and SPOC+ in Daisy Chain SPI configuration For the calculation the Maximum Ratings for the used devices have to be considered: SPOC FL EN2 SPOC+: IVDD_max: 25 mA (for t ≤ 2 min) IGND_max: 25 mA (for t ≤ 2 min) ISI_max: 2 mA (for t ≤ 2 min) ISO_max: 2 mA (for t ≤ 2 min) ISCLK_max: 2 mA (for t ≤ 2 min) VDD_max: 5.5 V VSI_max: 6 V VSO_max: 6 V VSCLK_max: 6 V IDD_max: 12 mA ISI_max: 2 mA ISO_max: 2 mA ISCLK_max: 2 mA For all diodes a forward voltage drop of 700mV is considered. Reverse battery voltage VREV = 14V. Application Note 38 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Appendix Calculation example for CS and SCLK There are 2 current paths which have to be considered: From GND of SPOC1 through SPOC2 to VS and from GND of µC through SPOC2 to VS. SPOC1 to SPOC2: Vseries = 14 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 6.6 V / 2 mA = 3.3 kΩ µC to SPOC2: Vseries = 14 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 6.6 V / 2 mA = 3.3 kΩ Calculation example for VDD There are 2 current paths which have to be considered: From GND of SPOC1 to SPOC2 to VS and from GND of µC to SPOC2 to VS. SPOC1 to SPOC2: Vseries = 14 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 6.6 V / 12 mA = 550 Ω µC to SPOC2: Vseries = 14 - 0.7 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 5.9 V / 12 mA = 492 Ω Calculation example for SO (SPOC1) to SI (SPOC2) Vseries = 14 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 6.6 V / 2 mA = 3.3 kΩ Calculation example for SO (SPOC2) to µC Vseries = 14 - 0.7 - 6 - 0.7 = 6.6 V Rseries = Vseries / IEDxx = 6.6 V / 2 mA = 3.3 kΩ For CS and SCLK pin of the SPOC a series resistors of >3.3 kΩ is needed between SPOC1 and SPOC 2 and between µC and SPOC2. From SO pin of SPOC1 to Si pin of SPOC2 and from SO pin of SPOC2 to µC a series resistance of >3.3kΩ is needed. For the VDD pin a series resistance of >550 Ω is needed between the two SPOC devices. From µC to each SPOC a series resistor of >492 Ω has to be placed to not exceed maximum ratings for a reverse battery case of -14 V. Application Note 39 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Appendix 9.2 Calculation of series resistor when sharing sense resistor for current sense diagnosis When sharing a common sense resistor between different devices / device families, it has to be ensured that the maximum rating of the sense pin for all connected devices is not exceeded. As an example there could be a SPOC FL EN2 - BTS5482SF and a PROFET+ - BTS5020-2EKA sharing a common sense resistor as shown in Figure 22. 100nF3 V bat 5V 500Ω P_IN0 IN0 P_IN1 IN1 P_DEN DEN P_DSEL DSEL VS OUT0 IS OUT1 100nF3 100nF VDD VCC GPIO 8kΩ IN1 GPIO 8kΩ IN2 GPIO 8kΩ OUT0 IS OUT1 OUT2 8V 1kΩ µC 2.7kΩ OUT3 8V GND 1nF VDD e.g. XC2267 SPI GND IN3 >2.7kΩ AD VS 3.9kΩ CS 3.9kΩ SCLK 3.9kΩ SO 3.9kΩ SI SPI LHI VSS external driver EDO 0 control EDD0 P_IN0 EDO 1 P_IN1 EDD1 P_DSEL P_DEN GND 10Ω2 BCM GND Figure 22 Shared_Sense_Resistor.emf BTS5482SF sharing sense resistor with BTS5020-2EKA The sense voltage of BTS5020-2EKA could go up to battery voltage. The maximum allowed voltage applied to sense pin of BTS5482SF would be < 8 V. When considering a maximum battery voltage of 16 V, > 8 V has to be dropped at the series resistor at sense of BTS5020-2EKA. Due to this reason a series resistor which is more high ohmic then the sense resistor itself has to be used to stay below the maximum ratings. For reverse battery condition please refer to Chapter 9.1.1. Application Note 40 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Additional Information 10 • • Additional Information Datasheet of BTS5482SF can be found at http://www.infineon.com/SPOC For further information you may contact http://www.infineon.com/ Application Note 41 Rev. 1.0, 2013-08-27 SPOC Front Light BTS5482SF - Application hints Revision History 11 Revision History SPOC Front Light Revision History: Rev. 1.0, 2013-08-27 Previous Version(s): Page Subjects (major changes since last revision) Application Note 42 Rev. 1.0, 2013-08-27 Edition 2013-08-27 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. 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