CCD Delay Line Series MN3881S PAL-Compatible CCD Video Signal Delay Element Overview The MN3881S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, 1/2nd frequency doubler, two switchable CCD analog shift registers, a clamp bias circuit, resampling output amplifiers, a mode selection circuit and booster circuits. When the switch pin is grounded, the MN3881S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the PAL system) for the Y output and 2 H for the C output. Features Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for color signal converted to low frequency. Pin Assignment VBIASC 1 16 VINC VOC 2 15 N.C. N.C. 3 14 N.C. VDD 4 13 XI –VBB 5 12 VSS N.C. 6 11 SW VOY 7 10 N.C. VBIASY 8 9 VINY ( TOP VIEW ) SOP016-P-0225 Applications VCRs 1 MN3881S CCD Delay Line Series 1 4 12 VSS VDD VBIASC Block Diagram Auto bias circuit VINC 16 Charge input block øS driver CCD 567 stages ø1 driver Charge detection block Resampling output 2 amplifier ø2 driver øR driver øSH driver øSH driver ø2 driver øR driver øSH driver øSH driver VOC Timing adjustment XI 13 Waveform amplifier 1/2nd frequency doubler adjustment block Timing adjustment øS driver ø1 driver Auto clamp circuit Resampling output 7 amplifier 8 Charge detection block VBIASY –VBB 2 CCD 566.5 stages 11 Charge input block SW 9 5 VINY VOY CCD Delay Line Series MN3881S Application Circuit Example VBIASC 0.01µF 1 VDD 0.1µF 4 12 VSS 10µF – + Auto bias circuit VINC 16 0.01µF Charge input block øS driver CCD 567 stages ø1 driver ø2 driver Charge detection block øR driver Resampling output 2 VOC amplifier øSH driver øSH driver Timing adjustment XI 13 Waveform amplifier adjustment block 1/2nd frequency doubler 1000pF Timing adjustment øS driver ø2 driver ø1 driver øR driver øSH driver øSH driver Auto clamp circuit Charge detection block –VBB 0.01µF Resampling output amplifier 7 VOY VBIASY 8 CCD 566.5 stages SW 11 Charge input block 5 VINY 9 – + 0.47µF 0.01µF Note: If the capacitor attached to pin 5 has a polarity, attach the negative pole to pin 5. 3 MN3881S CCD Delay Line Series Package Dimensions (Unit:mm) SOP016-P-0225 10.10±0.20 9 16 8 1.27 0.40±0.10 SEATING PLANE 4 0.10±0.10 (0.6) 1.60 +0.50 -0.20 +0.10 0.15 -0.05 0 to 10° 1.50±0.20 1 6.50±0.20 4.30±0.20 1.10±0.20 0.40min.