Power Estimation in ispMACH 4000V/B/C/Z Devices January 2004 Technical Note TN1005 Introduction The ispMACH™ 4000V/B/C/Z families offer an ideal mix of both high speed and low power in the same device. With an advanced low-power electrically erasable non-volatile memory cell and a full CMOS logic design approach, the ispMACH 4000V/B/C families offer fast pin-to-pin propagation delays for designs requiring high speed, while consuming only milliamps of static current. The ispMACH 4000Z family offers an even lower static current measured in microamps. The low standby and dynamic power of the ispMACH 4000 family is achieved without the need for any “turbo bits” or other power management schemes associated with traditional low power CPLD approaches. 1.8V Core E2CMOS® Technology The ispMACH 4000V/B/C/Z devices have an internal core voltage of 1.8V. For the ispMACH 4000V/B family, a builtin voltage regulator adjusts an external 3.3/2.5V supply to the core voltage of 1.8V. Because device ICC is proportional to capacitance and switching voltage, the lower 1.8V core voltage helps reduce dynamic power consumption. Special Standby ICC Considerations The Standby ICC component given in the ispMACH 4000V/B/C/Z data sheet does not include any current due to bus maintenance options such as Pull-up, Pull-down or Bus Hold, and does not allow for any application-specific DC I/O loads. A designer interested in the lowest possible standby ICC must evaluate which bus maintenance option is appropriate, taking into consideration which device outputs need to be enabled during Standby. For example, if the designer selects pull-up for bus maintenance, each steady-state active low output will add an IPU load to the standby ICC given in the data sheet. If bus maintenance is not required, designers must avoid floating inputs. Lattice recommends that all inputs and I/Os be driven or pulled to either ground or VCCO at all times. This recommendation includes unused inputs, I/O and the TCK pin. Without bus maintenance, the lowest standby current is achieved when inputs are at ground. Lattice recommends a pull-down resistor for TCK, one per chain, placed near the programming header and after each driver output used to buffer TCK, if buffers are used. Each of the devices in the ispMACH 4000 family have distinctly different static ICC characteristics. The ispMACH 4000V/B family members have an internal voltage regulator, which requires a bias current that leads to a higher static current. If standby current is a key consideration in your design, use of the ispMACH 4000C/Z family members should be considered since they do not have an internal voltage regulator and its accompanying bias current. Power Estimation This section describes how to estimate the power consumption of the ispMACH 4000 devices. It is recommended to confirm these estimates with the actual design under the intended operating conditions. Power consumption in the ispMACH 4000 family devices depends on three primary factors: 1. Operating clock frequency 2. Operating voltage 3. Power dissipated by the I/O drive current The total current consumption for the ispMACH 4000 can be estimated using the following equation: ICC = A + B * N * fMAX * AF + ICCO (1) • ICC = Current consumed by the ispMACH 4000 (mA) • A = Static component, given in the device data sheet (mA) www.latticesemi.com 1 tn1005_03 Lattice Semiconductor Power Estimation in ispMACH 4000V/B/C/Z Devices • B = Macrocell Power Coefficient, given in the device data sheet (mA/MHz) • N = Number of macrocells in the design (see report file) • fMAX = Maximum Operating clock frequency (MHz) • AF = Activity Factor of the nodes in the design • ICCO = Current attributable to output pins (mA). Only a small percentage of ICCO power is dissipated internal to the device. Power estimation coefficients A and B are given in the ispMACH 4000 V/B/C/Z Family data sheet along with the typical ICC vs. Frequency plots. ICCO Calculation Each active output pin will add current draw to the system. The sum of the current used by the I/O pins depends on the operating voltage, capacitance, output voltage swing, number of output pins and the average output frequency. The variable m in Equation 2 is the number of outputs in the design. VOH and VOL can be found in the ispMACH 4000 Family data sheet in the corresponding device section. m ICCO = Σ Cn * (VOH - VOL) * Fn (2) n=1 • ICCO = Current attributable to output pins (mA) • Fn = Output Frequency of output n (MHz) • Cn = Sum of Capacitive loading of output n (nF). When the output pin is connected to a CMOS input, typical load is 0.005 to 0.010 nF. (Note: the units nF are used to make the final ICC units be mA). • VOH = Output voltage high of the output (V) • m = number of outputs Activity Factor Calculation The Activity Factor relates to how often a register transitions. Each transition of a register adds to the current consumption of a device. The average of all the registers Activity Factors will give you the device AF. Take for example a 16-bit counter, the LSB node of a 16-bit counter is switching every clock rising edge, its Activity Factor is 1. The second node is switching every other clock rising edge that corresponds to an Activity Factor of 1/2. The third node is switching every fourth clock rising edge for an Activity Factor of 1/4. The series for the sequence of 16 nodes is 1 + 1/2 + 1/4 + 1/8 + 1/16 + ... + 1/215 converges to 2. Assuming a sum of 2 for the counter, divide by the total number of nodes (16) to measure the average AF per counter of 2/16 = 0.125. Estimated Power Consumption Example Calculation The following is an example calculation of the current consumption of an ispMACH 4032Z device. The Power Consumption section of the ispMACH 4000V/B/C/Z Family data sheet shows graphs that reflect the relationship between ICC and operating frequency for the ispMACH 4000 at typical operating voltage and room temperature. The pattern used in the device to generate the graphs is a 16-bit up-down counter, with an Activity Factor equal to 0.125, clocking every macrocell at frequency. The graphs provided only show the core current consumption and do not include the current required for output switching. Additional current drawn by the switching of the output pins needs to be added by calculating ICCO. For this example, the ispMACH 4032Z is used with two 16-bit counters. As described above, a single 16-bit counter has an Activity Factor which series sums to a value approximating 2. Summing the two counters’ Activity Factors results in a value of ~4 (i.e. 2 + 2). Dividing the accumulated register activity factors by the total number of registers results in 4/32 or ~0.125. From the ispMACH 4000 data sheet, the power estimation coefficients for A and B are 0.010mA and 0.010mA/MHz for the ispMACH 4032Z. Calculate the core ICC for an ispMACH 4032Z clocked at 150MHz (not including the ICCO factor as shown in Equation 1) as follows: 2 Lattice Semiconductor Power Estimation in ispMACH 4000V/B/C/Z Devices Core ICC = A + B * N * fMAX * AF (3) • Core ICC = Core current (no outputs) consumed by the ispMACH 4032Z (mA) • A = 0.010 (mA) • B = 0.010 (mA/MHz) • N = 32 Macrocells • fMAX = 150 (MHz) • AF = 0.125 Core ICC = 0.010 mA + 0.010 mA/MHz * 32 * 150 MHz * 0.125 = 6.01 mA Now add the current drawn from each output. If the least significant four bits are routed from each counter to pins on the ispMACH 4032Z, four frequency components would need to be used to calculate ICCO. For the four least significant bits, an output would switch at 150 MHz, 75 MHz, 37.5 MHz and 18.75 MHz. Assume that each output drives a single LVCMOS load of 10pF with the exception of the two least significant bits of each counter, which will be 20 pF. The following shows the ICCO calculation for a VCCO of 1.8V: m ICCO = Σ Cn * (VOH - VOL) * Fn (4) n=1 • ICCO = Total current attributable to output pins (mA). • Fn => F1 = 150 MHz, F2 = 75 MHz, F3 = 37.5 MHz, F4 = 18.75 MHz, F5 = 150 MHz, F6 = 75 MHz, F7 = 37.5 MHz, F8 = 18.75 MHz • Cn = 0.01 (nF) Assume worst case typical capacitance for all output pins accept the 150 MHz pins which will be 0.02 (nF) for this example • VOH = VCCO - 0.4 = 1.6 (V) • VOL = 0.2 (V) • m=8 m ICCO = Σ [(0.02 nF * 1.4 V * 150 MHz) + (0.01 nF * 1.4 V * 75 MHz) + n=1 (0.01 nF * 1.4 V * 37.5 MHz) + (0.01 nF * 1.4 V * 18.75 MHz) + (0.02 nF * 1.4 V * 150 MHz) + (0.01 nF * 1.4 V * 75 MHz) + (0.01 nF * 1.4 V * 37.5 MHz) + (0.01 nF* 1.4 V * 18.75 MHz)] ICCO = 0.01 nF * 1.4 V * (75 + 37.5 + 18.75 + 75 + 37.5 + 18.75) MHz + 0.02 nF * 1.4V * (150 + 150) MHz = 3.675mA + 8.4mA = 12.075 mA To calculate the overall current consumption of the device, add the Core ICC to ICCO to get the final power estimation for the device and pattern being used at 150 MHz is: ICC = Core ICC + ICCO = 6.01 mA + 12.075 mA = 18.085 mA Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-408-826-6002 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com 3