8342DxxA

GS8342D08/09/18/36AE-250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
250 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
36Mb SigmaQuad-II
Burst of 4 SRAM
Clocking and Addressing Schemes
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write (x36, x18, and x9) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with 9Mb, 18Mb, 72Mb and 144Mb devices
The GS8342D08/09/18/36AE SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock quasi independently with the C and C
clock inputs. C and C are also independent single-ended clock
inputs, not differential inputs. If the C clocks are tied high, the
K clocks are routed internally to fire the output registers
instead.
Each internal read and write operation in a SigmaQuad-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II B4 RAM is always two address pins
less than the advertised index depth (e.g., the 4M x 8 has a 1M
addressable index).
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The GS8342D08/09/18/36AE are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342D08/18/36AE SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
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SigmaQuad™ Family Overview
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Features
Parameter Synopsis
-200
-167
tKHKH
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.45 ns
0.50 ns
No
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-250
Rev: 1.07 8/2012
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
2
3
4
5
6
7
8
9
10
11
A
CQ
NC
NC
W
BW2
K
BW1
R
SA
NC
CQ
B
Q27
Q18
D18
SA
BW3
K
BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
NC
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
R
TDO
TCK
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1M x 36 SigmaQuad-II SRAM—Top View
Q26
SA
SA
C
SA
SA
Q9
D0
Q0
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35
2. A2, A3, and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Rev: 1.07 8/2012
Expansion Addresses
A3
72Mb
A10
144Mb
A2
288Mb
2/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
3
4
5
6
7
8
9
10
11
A
CQ
NC
SA
W
BW1
K
NC
R
SA
NC
CQ
B
NC
Q9
D9
SA
NC
K
BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
NC
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
R
TDO
TCK
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2M x 18 SigmaQuad-II SRAM—Top View
Q17
SA
SA
C
SA
SA
NC
D0
Q0
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
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Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. A2, A7, and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Rev: 1.07 8/2012
Expansion Addresses
A10
72Mb
A2
144Mb
A7
288Mb
3/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
4M x 9 SigmaQuad-II SRAM—Top View
2
3
4
5
6
7
8
9
10
11
A
CQ
NC
SA
W
NC
K
NC
R
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
BW0
SA
NC
NC
Q4
C
NC
NC
NC
VSS
SA
D
NC
D5
NC
VSS
VSS
E
NC
NC
Q5
VDDQ
VSS
F
NC
NC
NC
VDDQ
VDD
G
NC
D6
Q6
VDDQ
VDD
H
Doff
VREF
VDDQ
VDDQ
VDD
J
NC
NC
NC
VDDQ
VDD
K
NC
NC
NC
VDDQ
VDD
L
NC
Q7
D7
VDDQ
VSS
M
NC
NC
NC
VSS
N
NC
D8
NC
VSS
P
NC
NC
Q8
SA
R
TDO
TCK
SA
SA
VSS
NC
NC
D4
VSS
VSS
VSS
NC
NC
NC
VSS
VSS
VDDQ
NC
D3
Q3
VSS
VDD
VDDQ
NC
NC
NC
VSS
VDD
VDDQ
NC
NC
NC
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
VSS
VDD
VDDQ
NC
Q2
D2
VSS
VDD
VDDQ
NC
NC
NC
VSS
VSS
VDDQ
NC
NC
Q1
VSS
VSS
VSS
VSS
NC
NC
D1
SA
SA
SA
VSS
NC
NC
NC
SA
C
SA
SA
NC
D0
Q0
SA
C
SA
SA
SA
TMS
TDI
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SA
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NC
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1
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. BW0 controls writes to D0:D8.
2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Rev: 1.07 8/2012
Expansion Address
A2
72Mb
A7
144Mb
B5
288Mb
4/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
3
4
5
6
7
8
9
10
11
A
CQ
NC
SA
W
NW1
K
NC
R
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
NW0
SA
NC
NC
Q3
C
NC
NC
NC
VSS
SA
NC
SA
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
R
TDO
TCK
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4M x 8 SigmaQuad-II SRAM—Top View
Q7
SA
SA
C
SA
SA
NC
NC
NC
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Rev: 1.07 8/2012
Expansion Address
A2
72Mb
A7
144Mb
B5
288Mb
5/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Pin Description Table
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
NC
No Connect
—
—
R
Synchronous Read
Input
W
Synchronous Write
BW0–BW3
Synchronous Byte Writes
NW0–NW1
Nybble Write Control Pin
K
Input Clock
K
Input Clock
C
Output Clock
C
Output Clock
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock Input
TDO
Test Data Output
VREF
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Symbol
Active Low
Active Low
Input
Active Low
x9/x18/x36 only
Input
Active Low
x8 only
Input
Active High
Input
Active Low
Input
Active High
Input
Active Low
Input
—
Input
—
Input
—
Output
—
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
Qn
Synchronous Data Outputs
Output
—
Dn
Synchronous Data Inputs
Input
—
Doff
Disable DLL when low
Input
Active Low
CQ
Output Echo Clock
Output
—
Output Echo Clock
Output
—
Power Supply
Supply
1.8 V Nominal
Isolated Output Buffer Supply
Supply
1.5 or 1.8 V Nominal
Power Supply: Ground
Supply
—
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Input
CQ
VDD
VDDQ
VSS
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Notes:
1. NC = Not Connected to die or any other pin
2. C, C, K, or K cannot be set to VREF voltage.
Rev: 1.07 8/2012
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Background
ct
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II B4 Double Data Rate SRAM Read First
Read A
NOP
Read B
Write C
K
K
A
B
Read D
C
R
W
Ne
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BWx
D
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C
C
A
Q
CQ
A+2
A+3
NOP
E
C
C+1
C+2
C+3
E
E+1
C
C+1
C+2
C+3
E
E+1
B
B+1
B+2
B+3
D
D+1
D+2
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CQ
A+1
Write E
D
De
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Address
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SigmaQuad-II B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data
can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following
rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,
and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read
port deselect cycle.
Rev: 1.07 8/2012
7/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
SigmaQuad-II B4 SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous
command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge
of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.
NOP
Read B
Write C
K
K
A
Address
B
C
R
W
BWx
A
A+1
A+2
A+3
D
A
A+1
A+2
A+3
C
De
sig
C
Q
CQ
Write E
D
B
NOP
E
C
C+1
C+2
C+3
E
E+1
E+
C
C+1
C+2
C+3
E
E+1
E+
B+1
B+2
B+3
D
D+1
D+2
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CQ
Read D
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Write A
ct
SigmaQuad-II B4 Double Data Rate SRAM Write First
Rev: 1.07 8/2012
8/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Power-Up Sequence for SigmaQuad-II SRAMs
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1a. Apply VDD.
1b. Apply VDDQ.
1c. Apply VREF (may also be applied at the same time as VDDQ).
ct
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
1. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30 ns. 1024 cycles of clean K clocks are always required to relock the DLL after reset.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar ).
• The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired operating clock
frequency.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or
failures during the initial stage.
Special Functions
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Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
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Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
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Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discussion above.
Rev: 1.07 8/2012
9/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Example x18 RAM Write Sequence using Byte Write Enables
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Beat 3
0
0
Data In
Beat 4
1
0
Byte 2
Byte 1
Byte 2
D0–D8
D9–D17
D0–D8
D9–D17
Written
Unchanged
Unchanged
Written
Beat 1
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Don’t Care
Resulting Write Operation
Byte 1
ct
Data In Sample Time
Beat 2
Byte 1
Byte 2
Data In
Data In
Byte 1
Byte 2
D0–D8
D9–D17
D0–D8
D9–D17
Written
Written
Unchanged
Written
Beat 3
Beat 4
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Output Register Control
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
Rev: 1.07 8/2012
10/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Example Four Bank Depth Expansion Schematic
R3
W3
W2
R1
W1
R0
W0
A0–An
K
Bank 1
A
A
W
W
R
R
K
D
CQ
K
D
Q
C
CQ
Q
C
Bank 2
Bank 3
A
A
W
W
R
R
K
D
CQ
K
CQ
Q
D
Q
C
C
me
nd
ed
for
C
De
sig
Bank 0
Ne
w
D1–Dn
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Pr
od
u
ct
R2
Q1–Qn
CQ0
CQ1
Re
co
m
CQ2
No
t
CQ3
Note:
For simplicity BWn, NWn, K, and C are not shown.
Rev: 1.07 8/2012
11/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
Rev: 1.07 8/2012
B
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
12/35
CQ[2]
CQ[2]
Q(2)
C[2]
C[2]
CQ[1]
CQ(1)
Q(1)
C[1]
A
B
D(2)
C[1]
Read C
B+1
B+1
A+2
B+2
B+2
D
B+3
B+3
C
D
D
E
C+1
Read E
D+1
D+1
C+2
D+2
D+2
F
Write F
C+3
D+3
D+3
E
F
F
NOP
E+1
n—
Di
sco
nt
inu
ed
Pr
od
u
A+3
Write D
De
sig
A+1
Ne
w
C
B
me
nd
ed
for
Re
co
m
A
Write B
BWx(2)
D(1)
BWx(1)
W(2)
W(1)
R(2)
R(1)
Address
K
No
t
K
Read A
Σ2x2B4 SigmaQuad-II SRAM Depth Expansion
ct
F+1
F+1
E+2
F
F
GS8342D08/09/18/36AE-250/200/167
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Separate I/O SigmaQuad-II B4 SRAM Truth Table
Previous
Operation
A
R
W
Current
Operation
D
K↑
(tn-1)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K↑
(tn)
Deselect
X
1
1
Write
X
1
Read
X
Deselect
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
D
D
Q
Q
Q
Q
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
Deselect
X
X
—
—
Hi-Z
Hi-Z
—
—
X
Deselect
D2
D3
—
—
Hi-Z
Hi-Z
—
—
X
1
Deselect
X
X
—
—
Q2
Q3
—
—
V
1
0
Write
D0
D1
D2
D3
Hi-Z
Hi-Z
—
—
Deselect
V
0
X
Read
X
X
—
—
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
—
—
Write
V
0
X
D2
D3
—
—
Q0
Q1
Q2
Q3
me
nd
ed
for
Ne
w
De
sig
D
Read
No
t
Re
co
m
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when
preceded by a Read command.
6. Users should not clock in metastable addresses.
Rev: 1.07 8/2012
13/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Byte Write Clock Truth Table
BW
BW
BW
Current Operation
D
D
D
D
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
K↑
(tn)
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
T
T
T
T
Write
Dx stored if BWn = 0 in all four data transfers
D0
D2
D3
D4
T
F
F
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if BWn = 0 in 3rd data transfer only
X
X
D2
X
F
F
F
T
Write
Dx stored if BWn = 0 in 4th data transfer only
X
X
X
D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
BW
No
t
Re
co
m
me
nd
ed
for
Ne
w
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
Rev: 1.07 8/2012
14/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
x36 Byte Write Enable (BWn) Truth Table
BW1
BW2
BW3
D0–D8
D9–D17
D18–D26
D27–D35
1
1
1
1
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
1
1
1
Data In
Don’t Care
Don’t Care
Don’t Care
1
0
1
1
Don’t Care
Data In
Don’t Care
Don’t Care
0
0
1
1
Data In
Data In
Don’t Care
Don’t Care
1
1
0
1
Don’t Care
Don’t Care
Data In
Don’t Care
0
1
0
1
Data In
Don’t Care
Data In
Don’t Care
1
0
0
1
Don’t Care
Data In
Data In
Don’t Care
0
0
0
1
Data In
Data In
Data In
Don’t Care
1
1
1
0
Don’t Care
Don’t Care
Don’t Care
Data In
0
1
1
0
Data In
Don’t Care
Don’t Care
Data In
1
0
1
0
Don’t Care
Data In
Don’t Care
Data In
0
0
1
0
Data In
Data In
Don’t Care
Data In
1
1
0
0
Don’t Care
Don’t Care
Data In
Data In
0
1
0
0
Data In
Don’t Care
Data In
Data In
1
0
0
0
Don’t Care
Data In
Data In
Data In
0
0
0
0
Data In
Data In
Data In
Data In
BW1
1
1
0
1
1
0
0
0
n—
Di
sco
nt
inu
ed
Pr
od
u
De
sig
Ne
w
BW0
me
nd
ed
for
x18 Byte Write Enable (BWn) Truth Table
ct
BW0
D0–D8
D9–D17
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Data In
BW0
1
D0–D8
Don’t Care
Data In
No
t
0
Re
co
m
x09 Byte Write Enable (BWn) Truth Table
Rev: 1.07 8/2012
1
Don’t Care
0
Data In
15/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Nybble Write Clock Truth Table
NW
NW
NW
Current Operation
D
D
D
D
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
K↑
(tn)
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
T
T
T
T
Write
Dx stored if NWn = 0 in all four data transfers
D0
D2
D3
D4
T
F
F
F
Write
Dx stored if NWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if NWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if NWn = 0 in 3rd data transfer only
X
X
D2
X
F
F
F
T
Write
Dx stored if NWn = 0 in 4th data transfer only
X
X
X
D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
NW
NW1
1
1
0
1
1
0
0
0
D0–D3
D4–D7
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Data In
No
t
Re
co
m
NW0
me
nd
ed
for
x8 Nybble Write Enable (NWn) Truth Table
Ne
w
De
sig
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
Rev: 1.07 8/2012
16/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 2.9
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
VREF
Voltage in VREF Pins
VI/O
Voltage on I/O Pins
VIN
Voltage on Other Input Pins
IIN
Input Current on Any Pin
IOUT
Output Current on Any I/O Pin
TJ
Maximum Junction Temperature
TSTG
Storage Temperature
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
V
–0.5 to VDDQ
V
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
V
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
V
+/–100
mA dc
+/–100
mA dc
125
oC
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
De
sig
Recommended Operating Conditions
Power Supplies
Reference Voltage
Min.
Typ.
Max.
Unit
VDD
1.7
1.8
1.95
V
VDDQ
1.4
—
VDD
V
VREF
0.68
—
0.95
V
me
nd
ed
for
Supply Voltage
I/O Supply Voltage
Symbol
Ne
w
Parameter
Re
co
m
Notes:
1. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The
power down sequence must be the reverse. VDDQ must not exceed VDD.
2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
Operating Temperature
Symbol
Min.
Typ.
Max.
Unit
Ambient Temperature
(Commercial Range Versions)
TA
0
25
70
°C
Ambient Temperature
(Industrial Range Versions)
TA
–40
25
85
°C
No
t
Parameter
Rev: 1.07 8/2012
17/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
HSTL I/O DC Input Characteristics
Symbol
Min
Max
Units
Notes
DC Input Logic High
VIH (dc)
VREF + 0.1
VDD + 0.3
V
1
DC Input Logic Low
VIL (dc)
–0.3
VREF – 0.1
V
1
ct
Parameter
HSTL I/O AC Input Characteristics
Parameter
Symbol
AC Input Logic High
VIH (ac)
AC Input Logic Low
VIL (ac)
VREF Peak to Peak AC Voltage
VREF (ac)
n—
Di
sco
nt
inu
ed
Pr
od
u
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
3. VIL (Min)DC = –0.3 V, VIL(Min)AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
Min
Max
Units
Notes
VREF + 200
—
mV
2,3
—
VREF – 200
mV
2,3
—
5% VREF (DC)
mV
1
VIH
VSS
50%
VSS – 1.0 V
Capacitance
Overshoot Measurement and Timing
20% tKHKH
VDD + 1.0 V
50%
VDD
VIL
Re
co
m
20% tKHKH
me
nd
ed
for
Undershoot Measurement and Timing
Ne
w
De
sig
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
No
t
(TA = 25oC, f = 1 MHZ, VDD = 1.8 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Output Capacitance
COUT
VOUT = 0 V
6
7
pF
Clock Capacitance
CCLK
VIN = 0 V
5
6
pF
Note:
This parameter is sample tested.
Rev: 1.07 8/2012
18/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
AC Test Conditions
Conditions
Input high level
1.25 V
Input low level
0.25 V
Max. input slew rate
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Parameter
2 V/ns
Input reference level
0.75 V
VDDQ/2
Output reference level
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
50Ω
Input and Output Leakage Characteristics
Symbol
Input Leakage Current
(except mode pins)
Max
IIL
VIN = 0 to VDD
–2 uA
2 uA
IINDOFF
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–2 uA
–2 uA
2 uA
2 uA
IOL
Output Disable,
VOUT = 0 to VDDQ
–2 uA
2 uA
No
t
Re
co
m
Output Leakage Current
Min.
me
nd
ed
for
Doff
Test Conditions
Ne
w
Parameter
De
sig
VT = VDDQ/2
RQ = 250 Ω (HSTL I/O)
VREF = 0.75 V
Rev: 1.07 8/2012
19/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Symbol
Min.
Max.
Units
Notes
Output High Voltage
VOH1
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
1, 3
Output Low Voltage
VOL1
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
2, 3
VOH2
VDDQ – 0.2
VDDQ
V
4, 5
VOL2
Vss
0.2
V
4, 6
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Parameter
Output High Voltage
Output Low Voltage
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. 0Ω ≤ RQ ≤ ∞Ω
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Parameter
Symbol
Test Conditions
Operating Current (x36): DDR
IDD
Operating Current (x9): DDR
Standby Current (NOP): DDR
Notes:
-200
-167
Notes
0
to
70°C
–40
to
85°C
0
to 7
0°C
–40
to
85°C
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
850 mA
875 mA
725 mA
750 mA
625 mA
650 mA
2, 3
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
775 mA
800 mA
650 mA
675 mA
575 mA
600 mA
2, 3
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
750 mA
775 mA
650 mA
675 mA
575 mA
600 mA
2, 3
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
750 mA
775 mA
650 mA
675 mA
575 mA
600 mA
2, 3
270 mA
280 mA
255 mA
265 mA
245 mA
255 mA
2, 4
Ne
w
–40
to
85°C
Re
co
m
Operating Current (x8): DDR
-250
0
to
70°C
me
nd
ed
for
Operating Current (x18): DDR
ISB1
Device deselected,
IOUT = 0 mA, f = Max,
All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
Power measured with output pins floating.
Minimum cycle, IOUT = 0 mA
Operating current is calculated with 50% read cycles and 50% write cycles.
Standby Current is only after all pending read and write burst operations are completed.
No
t
1.
2.
3.
4.
De
sig
Operating Currents
Rev: 1.07 8/2012
20/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
AC Electrical Characteristics
Parameter
Symbol
-250
-200
-167
Min
Max
Min
Max
Min
8.4
5.0
8.4
6.0
Units
Max
Notes
tKHKH
tCHCH
4.0
tKC Variable
tKCVar
—
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.6
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.6
K to K High
C to C High
tKHKH
tCHCH
1.8
K to K High
C to C High
tKHKH
tCHCH
1.8
K, K Clock High to C, C Clock High
tKHCH
0
DLL Lock Time
tKCLock
1024
K Static to DLL reset
tKCReset
30
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
ns
0.2
—
0.2
—
0.2
ns
—
2.0
—
2.4
—
ns
—
2.0
—
2.4
—
ns
—
2.2
—
2.7
—
ns
—
2.2
—
2.7
—
ns
1.8
0
2.3
0
2.8
ns
—
1024
—
1024
—
cycle
—
30
—
30
—
ns
De
sig
Output Times
8.4
n—
Di
sco
nt
inu
ed
Pr
od
u
K, K Clock Cycle Time
C, C Clock Cycle Time
ct
Clock
6
7
0.45
—
0.45
—
0.5
ns
4
tKHQX
tCHQX
–0.45
—
–0.45
—
–0.5
—
ns
4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
—
0.45
—
0.45
—
0.5
ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
tKHCQX
tCHCQX
–0.45
—
–0.45
—
–0.5
—
ns
tCQHQV
—
0.30
—
0.35
—
0.40
ns
8
tCQHQX
–0.30
—
–0.35
—
–0.40
—
ns
8
tCQHCQH
tCQHCQH
1.55
—
1.95
—
2.45
—
ns
tKHQZ
tCHQZ
—
0.45
—
0.45
—
0.5
ns
4
tKHQX1
tCHQX1
–0.45
—
–0.45
—
–0.5
—
ns
4
tAVKH
0.5
—
0.6
—
0.7
—
ns
Control Input Setup Time (R, W)
tIVKH
0.5
—
0.6
—
0.7
—
ns
2
Control Input Setup Time (BWX, NWX)
tIVKH
0.35
—
0.4
—
0.5
—
ns
3
Data Input Setup Time
tDVKH
0.35
—
0.4
—
0.5
—
ns
CQ, CQ High Output Hold
CQ Phase Distortion
Re
co
m
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
Setup Times
No
t
Address Input Setup Time
Rev: 1.07 8/2012
me
nd
ed
for
CQ, CQ High Output Valid
Ne
w
—
21/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
AC Electrical Characteristics (Continued)
Parameter
Symbol
-250
-200
-167
Min
Max
Min
Max
Min
Max
—
Units
Notes
Hold Times
0.5
—
0.6
—
0.7
Control Input Hold Time (R, W)
tKHIX
0.5
—
0.6
—
0.7
Control Input Hold Time (BWX, NWX)
tKHIX
0.35
Data Input Hold Time
tKHDX
0.35
ns
ct
tKHAX
n—
Di
sco
nt
inu
ed
Pr
od
u
Address Input Hold Time
—
ns
2
3
—
0.4
—
0.5
—
ns
—
0.4
—
0.5
—
ns
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W.
3. Control signals are BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
4. If C, C are tied high, K, K become the references for C, C timing parameters
5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus
contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a
MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and
temperatures.
6. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
8. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet
parameters reflect tester guard bands and test setup variations.
Rev: 1.07 8/2012
22/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
Rev: 1.07 8/2012
A
B
KHKL
KLKH
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
23/35
CQ
CQ
Q
KHCQV
KHCQX
KHCQV
B
D
A
KHQX1
KHIX
CQHQX
A+1
KHQV
DVKH
IVKH
IVKH
NOP
B+1
B+1
C
CQHQV
A+2
B+2
KHDX
B+2
Write C
A+3
KHQX
De
sig
KHIX
KHKHbar
Ne
w
B
KHCQX
IVKH
me
nd
ed
for
KHIX
AVKH
Re
co
m
KHKH
Write B
BWx
W
R
Address
K
No
t
K
Read A
B+3
KHQZ
C
C
C+1
C+1
C+2
C+2
E
Write E
C+3
C+3
D
E
E
D+1
NOP
E+1
E+1
n—
Di
sco
nt
inu
ed
Pr
od
u
B+3
D
Read D
K and K Controlled Read-Write-Read Timing Diagram
ct
D+2
GS8342D08/09/18/36AE-250/200/167
© 2006, GSI Technology
Rev: 1.07 8/2012
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
24/35
CQ
CQ
Q
C
C
D
BWx
W
R
Address
K
No
t
K
A
CHCQV
CHCQX
CHCQX
CHCQX
KHIX
IVKH
KHAX
AVKH
KHKH
KHKL
NOP
B
Read B
C
CQHQX
A+3
C
C+1
KHDX
IVKH
NOP
C+2
C+2
D
DVKH
KHIX
Write D
C+3
C+3
D
D
NOP
B
C
B+1
C+1
B+2
B+3
CHQZ
n—
Di
sco
nt
inu
ed
Pr
od
u
CQHQV
A+2
A
A+1
CHQX
CHQV
KHIX
IVKH
De
sig
KHKHbar
Write C
CHQX1
Ne
w
KLKH
me
nd
ed
for
Re
co
m
Read A
C and C Controlled Read-Write-Read Timing Diagram
ct
D+1
D+1
D
D
GS8342D08/09/18/36AE-250/200/167
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDD.
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin Name
I/O
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Test Data In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Ne
w
TDI
Description
De
sig
Pin
JTAG Port Registers
me
nd
ed
for
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Re
co
m
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
No
t
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.07 8/2012
25/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
0
De
sig
Bypass Register
0
108
1
·
2 1 0
Ne
w
Instruction Register
TDI
TDO
ID Code Register
me
nd
ed
for
31 30 29
·
· ··
2 1 0
Control Signals
TMS
Test Access Port (TAP) Controller
Re
co
m
TCK
No
t
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.07 8/2012
26/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
GSI Technology
JEDEC Vendor
ID Code
n—
Di
sco
nt
inu
ed
Pr
od
u
Bit #
ct
Not Used
Presence Register
ID Register Contents
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
Tap Controller Instruction Set
X
X
X
X
X
X
X
0
0 0 1 1 0 1 1 0 0 1
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.07 8/2012
27/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
Run Test Idle
1
Select DR
1
0
ct
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
1
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
De
sig
1
Update DR
0
0
Pause IR
1
Exit2 IR
0
1
0
0
Update IR
1
0
Ne
w
1
1
Select IR
n—
Di
sco
nt
inu
ed
Pr
od
u
0
me
nd
ed
for
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
No
t
Re
co
m
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.07 8/2012
28/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z except CQ.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
Places Bypass Register between TDI and TDO.
1
Ne
w
Description
me
nd
ed
for
Code
Re
co
m
Instruction
De
sig
JTAG TAP Instruction Set Summary
BYPASS
111
No
t
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.07 8/2012
29/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Symbol
Min.
Max.
Unit Notes
Test Port Input Low Voltage
VILJ
–0.3
0.3 * VDD
V
1
Test Port Input High Voltage
VIHJ
0.6 * VDD
VDD +0.3
V
1
IINHJ
–300
1
uA
2
IINLJ
–1
100
uA
3
IOLJ
–1
1
uA
4
VOHJ
VDD – 200 mV
—
V
5, 6
VOLJ
—
0.4
V
5, 7
VOHJC
VDD – 100 mV
—
V
5, 8
VOLJC
—
100 mV
V
5, 9
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
ct
JTAG Port Recommended Operating Conditions and DC Characteristics
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
me
nd
ed
for
Ne
w
De
sig
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Input high level
Re
co
m
Input low level
Conditions
VDD – 0.2 V
TDO
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDD/2
No
t
JTAG Port AC Test Load
50Ω
30pF*
VDD/2
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.07 8/2012
30/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTS
TMS
tTKQ
TDO
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Symbol
Min
Max
TCK Cycle Time
tTKC
50
—
TCK Low to TDO Valid
tTKQ
—
TCK High Pulse Width
tTKH
20
TCK Low Pulse Width
tTKL
20
TDI & TMS Set Up Time
tTS
TDI & TMS Hold Time
tTH
Unit
ns
De
sig
Parameter
n—
Di
sco
nt
inu
ed
Pr
od
u
tTH
tTS
ct
TDI
ns
—
ns
—
ns
10
—
ns
10
—
ns
No
t
Re
co
m
me
nd
ed
for
Ne
w
20
Rev: 1.07 8/2012
31/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
BOTTOM VIEW
Ø0.10 M C
Ø0.25 M C A B
Ø0.40~0.60 (165x)
A1 CORNER
ct
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11
14.0
1.0
1.0
10.0
15±0.05
0.20(4x)
No
t
Re
co
m
0.36~0.46
1.50 MAX.
SEATING PLANE
C
B
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
me
nd
ed
for
0.15 C
Ne
w
A
De
sig
17±0.05
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
n—
Di
sco
nt
inu
ed
Pr
od
u
11 10 9 8 7 6 5 4 3 2 1
Rev: 1.07 8/2012
32/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Ordering Information—GSI SigmaQuad-II SRAM
Part Number1
Type
Package
Speed
(MHz)
TA2
4M x 8
GS8342D08AE-250
SigmaQuad-II SRAM
165-Pin BGA
250
C
4M x 8
GS8342D08AE-200
SigmaQuad-II SRAM
165-Pin BGA
200
C
4M x 8
GS8342D08AE-167
SigmaQuad-II SRAM
165-Pin BGA
167
C
4M x 8
GS8342D08AE-250I
SigmaQuad-II SRAM
165-Pin BGA
250
I
4M x 8
GS8342D08AE-200I
SigmaQuad-II SRAM
165-Pin BGA
200
I
4M x 8
GS8342D08AE-167I
SigmaQuad-II SRAM
165-Pin BGA
167
I
4M x 9
GS8342D09AE-250
SigmaQuad-II SRAM
165-Pin BGA
250
C
4M x 9
GS8342D09AE-200
SigmaQuad-II SRAM
165-Pin BGA
200
C
4M x 9
GS8342D09AE-167
SigmaQuad-II SRAM
165-Pin BGA
167
C
4M x 9
GS8342D09AE-250I
SigmaQuad-II SRAM
165-Pin BGA
250
I
4M x 9
GS8342D09AE-200I
SigmaQuad-II SRAM
165-Pin BGA
200
I
4M x 9
GS8342D09AE-167I
SigmaQuad-II SRAM
165-Pin BGA
167
I
2M x 18
GS8342D18AE-250
SigmaQuad-II SRAM
165-Pin BGA
250
C
2M x 18
GS8342D18AE-200
SigmaQuad-II SRAM
165-Pin BGA
200
C
2M x 18
GS8342D18AE-167
SigmaQuad-II SRAM
165-Pin BGA
167
C
2M x 18
GS8342D18AE-250I
SigmaQuad-II SRAM
165-Pin BGA
250
I
2M x 18
GS8342D18AE-200I
SigmaQuad-II SRAM
165-Pin BGA
200
I
2M x 18
GS8342D18AE-167I
SigmaQuad-II SRAM
165-Pin BGA
167
I
1M x 36
GS8342D36AE-250
SigmaQuad-II SRAM
165-Pin BGA
250
C
1M x 36
GS8342D36AE-200
SigmaQuad-II SRAM
165-Pin BGA
200
C
1M x 36
GS8342D36AE-167
SigmaQuad-II SRAM
165-Pin BGA
167
C
1M x 36
GS8342D36AE-250I
SigmaQuad-II SRAM
165-Pin BGA
250
I
1M x 36
GS8342D36AE-200I
SigmaQuad-II SRAM
165-Pin BGA
200
I
1M x 36
GS8342D36AE-167I
SigmaQuad-II SRAM
165-Pin BGA
167
I
4M x 8
GS8342D08AGE-250
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
250
C
GS8342D08AGE-200
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
200
C
GS8342D08AGE-167
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
167
C
GS8342D08AGE-250I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
250
I
GS8342D08AGE-200I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
200
I
GS8342D08AGE-167I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
167
I
GS8342D09AGE-250
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
250
C
4M x 8
4M x 8
No
t
4M x 8
4M x 8
n—
Di
sco
nt
inu
ed
Pr
od
u
De
sig
Ne
w
me
nd
ed
for
Re
co
m
4M x 8
4M x 9
ct
Org
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number.
Example: GS8342D3636AE-200T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.07 8/2012
33/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Ordering Information—GSI SigmaQuad-II SRAM
Part Number1
Type
Package
Speed
(MHz)
TA2
4M x 9
GS8342D09AGE-200
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
200
C
4M x 9
GS8342D09AGE-167
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
167
C
4M x 9
GS8342D09AGE-250I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
250
I
4M x 9
GS8342D09AGE-200I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
200
I
4M x 9
GS8342D09AGE-167I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
167
I
2M x 18
GS8342D18AGE-250
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
250
C
2M x 18
GS8342D18AGE-200
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
200
C
2M x 18
GS8342D18AGE-167
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
167
C
2M x 18
GS8342D18AGE-250I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
250
I
2M x 18
GS8342D18AGE-200I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
200
I
2M x 18
GS8342D18AGE-167I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
167
I
1M x 36
GS8342D36AGE-250
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
250
C
1M x 36
GS8342D36AGE-200
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
200
C
1M x 36
GS8342D36AGE-167
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
167
C
1M x 36
GS8342D36AGE-250I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
250
I
1M x 36
GS8342D36AGE-200I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
200
I
1M x 36
GS8342D36AGE-167I
SigmaQuad-II SRAM
RoHS -compliant 165-Pin BGA
167
I
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Org
No
t
Re
co
m
me
nd
ed
for
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number.
Example: GS8342D3636AE-200T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.07 8/2012
34/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342D08/09/18/36AE-250/200/167
Revision History
Types of Changes
Format or Content
Revisions
Content
GS8342DxxA_r1_01; GS8342DxxA_r1_02
Content
GS8342DxxA_r1_02; GS8342DxxA_r1_03
Content
GS8342DxxA_r1_03; GS8342DxxA_r1_04
Content
GS8342DxxA_r1_04; GS8342DxxA_r1_05
Content
Content
Ne
w
GS8342DxxA_r1_05; GS8342DxxA_r1_06
Content
• Updated tKHKH, tKHCH in AC Char table
• Added tKHKH and CQ Phase Distortion to AC Char table
• Added Power-up Sequence section
• Added CZ operating currents data
• Changed status to PQ
• Added VREF note to Pin Description table
• Updated FLXDrive-II Output Driver Impedance Control section
• Removed Preliminary banner due to production status
• Revised AC Electrical Characteristics table (pg. 22); Removed
Status column from Ordering Information table, Updated 165
BGA Package Drawing (pg. 32), Updated Four Bank Depth
Expansion Drawing (pg. 11); Revised JTAG Port AC Test Conditions (pg. 31) Rev1.06b: Replaced omitted Coherency and
PPQs Pass Through Functions diagram (pg. 13)
• (Rev1.06c: Editorial updates)
• Removed 333 & 300 MHz bins
No
t
Re
co
m
me
nd
ed
for
GS8342DxxA_r1_06; GS8342DxxA_r1_07
• Updated MAX tKHKH
• (Rev. 1.01a: Updated Note 4 in HSTL Output Driver DC
Electrical Characteristics table)
De
sig
GS8342DxxA_r1; GS8342DxxA_r1_01
n—
Di
sco
nt
inu
ed
Pr
od
u
• Creation of new datasheet
GS8342DxxA_r1
ct
File Name
Rev: 1.07 8/2012
35/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
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