Application Note CoolMOS™ CP

Version 1.1, February 2007
Application Note
AN-CoolMOS-CP- 01
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Authors:
Fanny Bjoerk, Jon Hancock, Gerald Deboy
Published by Infineon Technologies AG
http://www.infineon.com/CoolMOS
Power Management &
Supply
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Revision History
Actual Release: Rev.1.1 2007-02-12
Previous Release: Rev.1.0
Table of contents
1 Introduction...................................................................................................................................................... 3
2 Technology Comparison of CoolMOSTM CP to C3 ........................................................................................... 6
3 Dynamic Switching Behavior of CoolMOSTM CP .............................................................................................. 9
4 Circuit Design and Layout Recommendations ............................................................................................... 13
5 MOSFET Selection for the Application Based on Loss Balance .................................................................... 17
6 Examples of Application Benefits with CoolMOSTM CP.................................................................................. 19
7 Product Portfolios .......................................................................................................................................... 21
8 References .................................................................................................................................................... 23
Appendix – Typical Dynamic Switching Characteristics of CoolMOSTM CP 600V ................................................. 24
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
1
Introduction
Today’s trend in SMPS applications of system miniaturization and efficiency improvement put tough demands on
power semiconductor performance. The new CoolMOSTM CP series meets these demands by offering a dramatic
reduction of drain-source on-resistance (RDSon) in a given package, ultra-low total gate charge and a very low
TM
1
energy stored in the output capacitance. First 600V CoolMOS CP products were introduced during 2005 , with
fill-up of product spectrum and introduction of a 500V class during 2006. This application note contains technical
component details and a selection guide with design considerations.
Target applications for CoolMOSTM CP are server and telecom power supplies, notebook adapters, LCD TV, ATX
and gaming power supplies and lighting ballasts, as outlined in Table 1. Table 2 gives a quick overview of
available CoolMOSTM series today.
Application
PFC
Topology
Conventional,
Interleaved
Adapter
ATX power supplies
Server / Telecom
LCD / PDP TV
Lighting ballasts
PWM
hard switching
TTF, ITTF, Flyback,
Half-bridge
PWM
resonant switching
ZVS phase shift, res. HB,
SRC, LLC
CoolMOSTM C3*
CoolMOSTM CP**
CoolMOSTM CFD
* Easy to design in
** Takes additional care for design-in
Highest reliability
TM
Table 1 CoolMOS
recommendation table for major applications.
CoolMOSTM S5
Market
entry
1998
Voltage
class [V]
600
CoolMOSTM C3
2001
500/600/
650/800
CoolMOSTM CFD
2004
600
CoolMOSTM CP
2005
500/600
Special
characteristic
Low RDSon, Switching
speed close to
standard MOSFETs
Fast switching speed,
symmetrical rise/fall
time at Vgs=10V
Fast body diode, Qrr
1/10th of C3 series
Ultra-low RDSon,
ultra-low Qg, very fast
switching speed
Vgs,th
[V]
4.5
Gfs
[S]
Low
Internal Rg
[Ohm]
High
3
High
Low
4
High
Low
3
High
Low
Table 2 CoolMOSTM series at a glance.
1
The CoolMOS CS series is being absorbed into CoolMOS CP, employing same technology. CoolMOS CP series will be the umbrella series
for all part numbers formerly shown as CoolMOS CS, with the only modification being the suffix change to CP from CS.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
1.1
The Superjunction principle
RDSon*A [Ohm*mm2]
CoolMOSTM is a revolutionary technology for
12
high voltage power MOSFETs and designed
according to the superjunction (SJ) principle
State-of-the-art
Si Limit
10
[1], which in turn is based on the RESURF [2]
standard MOSFETs
ideas being successfully used for decades in
8
lateral power MOSFETs. Conventional power
MOSFETs suffer from the limitation of the socalled silicon limit [3], which means that
6
CoolMOSTM C3
doubling the voltage blocking capability
typically leads to an increase in the on-state
4
resistance by a factor of five. The silicon limit
is shown in Figure 2 where the area specific
CoolMOSTM CP
2
on state resistance of state-of-the-art
standard MOSFETs as well are indicated. SJ
0
500
600
700
800
900
400
technology may lower the on-state resistance
Breakdown Voltage [V]
of a power MOSFET virtually towards zero.
The basic idea is to allow the current to flow
Figure 2 Area-specific RDSon versus breakdown voltage
from top to bottom of the MOSFET in very
for standard MOSFET and CoolMOSTM technology.
high doped vertically arranged regions. In
other words, a lot more charge is available for current
G
G
conduction compared to what is the case in a standard
S
S
MOSFET structure. In the blocking state of the SJ
MOSFET, the charge is counterbalanced by exactly
n
p
the same amount of charge of the opposite type. The
- two charges are separated locally in the device by a
pp
n epi
very refined technology, and the resulting structure
shows a laterally stacked fine-pitched pattern of
alternating arranged p- and n-areas, see Figure 1. The
+
n sub
finer the pitch can be made, the lower the on-state
resistance of the device will be. With every
D
D
CoolMOSTM generation the pitch is reduced, moving
Standard
MOSFET
Superjunction
MOSFET
ever closer to the zero resistance point without losing
voltage blocking capability.
Figure 1 Schematic cross-section of a standard
power MOSFET versus a superjunction MOSFET
+
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Another signature of SJ technology is the extremely fast switching speed. The turn off behavior of a SJ MOSFET
is not characterized by the relatively slow voltage driven vertical expansion of the space charge layer but by a
sudden nearly intrinsic depletion of the laterally stacked p-n structure. This unique behavior makes the device
very fast. The neutralization of these depletion layers is done via the MOS controlled turn-on of the load current
for the n-areas and via a voltage driven drift current for the p-areas. SJ devices reach therefore theoretical
switching speeds in the range of few nanoseconds.
Figure 3 shows a comparison of the figure-of-merit RDSon*Qg between the most advanced MOSFET
technologies available in the market today.
Gen 1
25
Gen 2
20
Gen 2
Gen 1
CP
10
5
Gen 1
15
C3
FOM = Rdson, max *Qg [Ohm*nC]
30
0
Infineon 600V
Other SJ MOS 600V Other SJ MOS 600V
Best conventional
MOS 600V
Figure 3 Comparison of figure-of-merit Rdson,max*Qg for most advanced 600V MOSFETs available in the
market.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
2
Technology Comparison of CoolMOSTM CP to C3
CoolMOS™ CP is the next step towards THE IDEAL HIGH VOLTAGE SWITCH with key features:
9
Further reduced conduction and switching losses
9
Lowest on-state-resistance per package @600V blocking capability
9
Ultra-low gate charge and Lowest figure-of-merit RDSon x Qg
… which gives the application benefits:
9
Extremely reduced heat generation
9
Reduced system size and weight
9
Very low gate drive power facilitating the use of low cost ICs and gate drivers
9
Reduced overall system cost
To make an optimum MOSFET selection and apply it successfully, it’s useful to first have a clear understanding of
parameter differences with its predecessors. We present the key features of CoolMOS™ CP to C3 series in Table
3.
Specification
Symbol
SPW20N60C3
IPW60R199CP
On-state resistance,
maximum rating, 25 °C
Drain current rating
RDSon
190 mΩ
199 mΩ
ID
20A
16A
16.5 ΩnC
6.4 ΩnC
FOM RDSon x Qg,total
Typical Gate to Source,
Drain charge
Typical CRSS @ 50 V
Qgs, Qgd
11 nC, 33 nC
8 nC, 11nC
CRSS
9 pF
20 pF
Typical CRSS @ 100 V
CRSS
7.5 pF
1.8 pF
Energy stored in output
capacitance @400V
Thermal resistance, junctioncase
Gate threshold voltage,
min…max
EOSS
10 µJ
7.5 µJ
RthJC,max
0.6 K/W
0.9 K/W
VGS(th)
2.1… 3.9 V
2.5… 3.5 V
Table 3 Key features comparison of CoolMOSTM CP versus C3 series.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
The improvements in dynamic characteristics
are substantial in CoolMOSTM CP. As shown in
Figure 5, the gate to drain charge, Qgd, is
greatly reduced and contributes to lower turn-on
time and turn-off time. Furthermore, the output
capacitance is as well reduced resulting in lower
energy stored in the output capacitance, Eoss,
for VDS=400V which is a key value for PFC and
ZVS full-bridge topologies. As a consequence
turn-on and turn-off switching power losses drop
considerably for CP compared with C3 as seen
in Figure 6. Eon is reduced by a factor of two,
while Eoff is reduced by a factor of 3.3.
30
0.25
25
0.20
20
ID at 25 °C
0.10
15
10
Current capability per package
increases with lower RDSon
0.05
5
0.00
0
Standard
MOSFET
450mOhm
Standard
MOSFET
420mOhm
Other SJ
MOSFET
290mOhm
CoolMOS C3
190mOhm
Other SJ
MOSFET
170mOhm
CoolMOS CP
99mOhm
Figure 4 RDSon,max and nominal current rating for
TO220 packages, showing technology advances over
time for 600 V rated MOSFETs.
12
Lowest total gate charge,
best FoM Ron*Qg
10
8
6
4
Lowest Qgd,
best ratio Qgd / Qgs
2
190 mΩ C3 series
199 mΩ CP series
0
0
20
40
60
80
100
Gate charge [nC]
Figure 5 Gate charge characteristics comparison C3,
CP.
7 of 32
ID t 25 °C [A]
0.30
0.15
Gate voltage Vgs [V]
As the chip size for a given RDSon rating is
smaller in CP technology compared to C3, the
thermal impedance is higher and thus the
current rating is slightly lower when comparing
same RDSon. However, MOSFET selection
should be made based on system thermal
requirements, which means RDSon selection,
and not on current rating. The slightly lower
rating for CP compared to C3 has no affect in
the majority of applications as nominal peak and
rms currents are far below the rated currents in
the datasheet. For peak current capability, there
is no compromise between CP and C3 series.
RDSon,max [Ohm]
CoolMOSTM CP series has the world’s lowest area-specific RDSon for 500V and 600V MOSFETs, which results
in lowest RDSon per package type. Figure 4
shows technology advances in RDSon and
1995
2006
0.50
50
current rating for 600V class MOSFETs in TO220 package, from a 450 mOhm conventional
0.45
45
MOSFET to superjunction MOSFETs. A TO-220
RDSon,max
package in CP technology can handle an
0.40
40
outstanding high continuous drain current of
0.35
35
more than 30 A.
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
10
8
190mOhm C3 series
199 mOhm CP series
Eoss [µ]
6
4
2
0
0
100
200
300
400
500
Voltage [V]
Figure 6 Comparison of energy stored in output capacitance CP to
C3.
400
Switching losses Eon, Eoff [µJ]
C3 190 mOhm Eon
CP 199 mOhm Eon
300
C3 190 mOhm Eoff
CP 199 mOhm Eoff
200
100
0
0
20
40
60
Gate resistance [Ohm]
Figure 7 Comparison of switching power losses, CP vs. C3.
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80
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Dynamic Switching Behavior of CoolMOSTM CP
3
MOSFET switching is governed first and foremost about
resistances (gate input) and capacitances (gate to source
Cgs, gate to drain Cgd, and source to drain Cds), see
Figure 8. With the very fast switching speed of CoolMOS™
CP, secondary effects become as well important, such as
the influence of source circuit inductance and drain to
source output capacitance. Behaviors may be seen, which
are not usually encountered with conventional MOSFETs.
Understanding these behaviors and using them to
advantage within safe limits in the application requires a
deeper look into the MOSFET switching behavior. Turn-on
behavior is usually strongly influenced by the application
circuit and associated components, but turn-off behavior is
usually controlled just by the MOSFET, so this is the mode
which will be examined closely in this section.
Note that for correlation with standard data sheet terms,
Ciss = Cgs + Cgd, Crss = Cgd, and Coss = Cds + Cgd.
Figure 8 Elements controlling MOS switching.
3.1 Gate Controlled MOSFET Switching
Considering the diagram of Figure 9, the gate controlled
MOSFET turn-off occurs in three fairly discrete intervals,
and the behavior and losses for each interval is described
separately below:
In the interval t1, the gate voltage is discharged to the
current plateau level by the driver, with a time determined
largely by Ciss, the gate input resistance RG, and the
operating voltage levels for the gate drive and the plateau
voltage determined by the MOSFET gfs and load current:
 VGDrv − VG −Off 
t1 = RG ⋅ Ciss ⋅ ln 

 VPlat − VG −Off 
(1)
In the interval t2, the MOSFET is acting like an integrating
amplifier, and the gate current supplied through Rg is that
needed to charge Cgd as VDS rises, even while full ID
current flows:
t2 =
RG ⋅ Crss ⋅VDS
VPlat − VG −Off
Figure 9 Example of gate controlled turn-off
switching.
(2)
During this gate controlled interval, where dVDS/dt is controlled by gate drive, the actual rate of change can be
described by:
dVDS VPlat − VG −Off
=
dt
RG ⋅ C Rss
(3)
In the final portion of turn-off, the gate drops below the plateau region, as RG discharges Ciss further, and ID falls
following the MOSFET transfer function for ID as a function of VGS.
 VPlat − VG −Off 
t 3 = RG ⋅ Ciss ⋅ ln 

 Vth − VG −Off 
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(4)
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
500
20
400
16
Vgs C3 [V]
300
Charging Cds
Ids C3 [A]
12
Falling ID
200
Vds C3 [V]
8
100
Discharging Cgs + Cgd
4
Drain voltage [V]
Gate voltage [V], Drain current [A]
This turn-off behavior is shown in the simulation
results of Figure 10, displaying the gate input
waveform, drain to source voltage, and drain
current. In this mode, the gate drive retains
complete control over the dv/dt of the MOSFET,
and is directly sizable by adjusting the size of
the gate input resistor. However, as gate charge
becomes lower in MOSFETs, and output
capacitance non-linearity increases, using small
values of gate drive resistance eventually shifts
the switch-off behavior into a different mode.
Discharging
the
24
input capacitance Cgs + Cgd
Charging Cgd
0
0
20
40
60
80
100
0
120
Time [ns]
Figure 10 Turn-off simulation of CoolMOSTM.
3.2 Quasi-ZVS Switching
Under conditions in which the gate drive turn-off is very fast, in
combination with a relatively high Coss (as can exist in
superjunction MOSFETs when the drain to source voltage is below
50V), the switching behavior will be dominated by somewhat
different mechanisms, and the drain switching voltage will not be
controlled by the gate drive current, but by Coss and load current.
The behavior can still be roughly described by three main states
Figure 11 but externally measured gate drive or drain current can be
misleading in identifying these states. The t1 state is governed
similarly as for the gate controlled dv/dt mode; the difference arises
in the t2 region, where the gate discharging current is at such a high
level such that the load current cannot begin to charge a voltage
across COSS, and the channel current is turned off before the drain
to source voltage rises. This is approximately described by:
 VPlat − VG−Off 
t2 = RG ⋅ Ciss ⋅ ln 

 Vth − VG−Off 
Figure 11 Quasi-ZVS Coss
controlled turn-off.
(5)
This mode does result in very low turn-off losses, but it has some characteristics to consider that can become an
issue in some applications, especially PFC converters with wide range of input current, and brief but high
overloads.
Capacitances [pF]
Examining the capacitance curves of the two technologies, it is clear that CoolMOS™ CP has a substantially
higher output capacitance below 50V. This is due to the smaller cell pitch compared to C3. As blocking voltage
develops, around 50V there is a much more abrupt transition from a P-column structure to a planar depletion
region, resulting in an order of magnitude drop
in output capacitance over a small voltage
10000
range. This is the “ideal” characteristic for a low
Ciss CP
loss non-linear ZVS snubber - it keeps the
Crss CP
output voltage rate of rise low initially while gate
Coss CP
1000
Ciss C3
voltage is completing turn-off. Then, the output
Crss C3
capacitance drops to a very low level, around
Coss C3
50 pF, permitting a very fast drain voltage rise.
100
However, any possibility of drain control is lost
because the low Qgd gate design means that
gate-drain overlap capacitance is absolutely
10
minimized, and as a result Crss drops to an
astonishingly low value, less than 2 pF above
60V.
The impact of this can be seen even in
simulation, where the dv/dt is controlled by
Coss and load current in examples at 5A, 10A,
1
0
10
20
30
40
50
60
70
80
90
Drain Source voltage Vds [V]
Figure 12 Device capacitances IPP60R385CP vs.
SPP11N60C3.
10 of 32
100
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Drain source voltage Vds [V]
and 30 (Figure 14). The Coss-controlled dv/dt is nearly doubled for CP compared to C3. In order to avoid
excessively high dv/dt values, the first
recommendation is to keep the turn-off transition
600
in the gate controlled region under the highest
870 V/ns !
144 V/ns
80 V/ns
load current condition occurring in the application.
500
For example, in a forward converter the operating
current range is relatively limited, and operating
400
current tends to be low- Coss controlled turn-off
will not result in potentially destructive dv/dt.
300
However, in boost converters for PFC, the peak
CP, turn off at 5A
current is not necessarily under direct gate
CP, turn off at 10A
200
control, considering issues like input voltage
CP, turn off at 30A
C3, turn off at 5A
transients and response delays in an average
C3, turn off at 10A
100
current mode controller. In that case, more care
C3, turn off at 30A
must be exercised.
0
Drain current Ids [A]
The key to reliability under all conditions is
maintaining device control. This means using gate
drive to limit excessive di/dt and dv/dt by using the
correct range for gate driver resistance. This is in
principle no difference for CoolMOS™ CP than for
C3.
Transconductance
for
the
two
generations are actually quite similar, as the
comparison in Figure 13 shows (190 mΩ C3,
199 mΩ CP). What happens when gate
driver resistors are chosen outside a
reasonable operating range? This is
examined in the context of the 199/190 mΩ
CP/C3 MOSFETs in next paragraph.
0
5
10
15
20
25
30
Time [ns]
Figure 14 dv/dt simulation of CP, C3
160
120
CP at Vds 20 V
C3 at Vds 20 V
80
C3 at Vds 400 V
CP at Vds 400 V
With very low values of gate driver
resistance, di/dt is not under control of the
MOSFET, but instead by the surrounding
40
circuit elements. This is demonstrated in
Figure 15 with the gate input resistor of
6.8 Ohm for an IPW60R199CP, and di/dt
0
that rises quite rapidly with load current, until
0
2
4
6
8
10
limited by external parasitic inductance. In
Gate voltage Vgs [V]
this case di/dt can reach thousands of
Figure 13 Transconductance characteristics of CP, C3
amperes per microsecond. With the gate
resistor raised to 68 ohms, the picture is very
different, and the rate of charging Cgs controls the di/dt independent of drain circuit loading, keeping peak di/dt in
this case to a reasonable but fast 700A/µsec. A similar situation exists for controlling dv/dt, as would be expected.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
180
4200
C3 at Rg=3.6 Ohm
C3 at Rg=3.6 Ohm
150
CP at Rg=6.8 Ohm
di/dt, turn off [A/µs]
CP at Rg=68 Ohm
No gate control, excessive di/dt
2800
transition region
2100
1400
700
0
5
10
15
20
dv/dt limited by Coss
120
90
transition region
60
30
Full control by Rg,
no current dependency on di/dt
0
CP at Rg=6.8 Ohm
CP at Rg=68 Ohm
dv/dt, turn off [V/ns]
3500
dv/dt controlled by Rg
0
25
0
5
10
15
20
25
Load current [A]
Load current [A]
Figure 15 Left: di/dt for different load currents and gate drive resistance. Right: dv/dt for different load
currents and gate drive resistance
In the case of IPW60R199CP with a gate resistor of 6.8 ohms, the turn-off is very fast, due to low gate
charge and low output capacitance above 50V. The dv/dt shows a linear rise with increasing load current,
indicating true ZVS turn-off of the MOS channel, and rise of drain voltage which is only a function of how fast
the output load current can charge the output capacitance COSS.
The red curves shows what is called “transition region” behavior for C3 CoolMOS™, as the dv/dt is not
completely controlled by output load current, and some gate control is still evident. With a gate resistance of
68 ohms, CoolMOS™ CP shows complete control of switching behavior by the gate, and drain to source
dv/dt which is nearly invariant of load current. In this mode, the MOSFET is operating as an
inverting/integrating amplifier, with the gate as a virtual AC ground. This is why the plateau region is fixed in
voltage during switching. There is no feedback resistor, only the “integration” capacitance from the MOSFET
CRSS (gate to drain capacitance). At about 25 V/ns, drain switching speed is still fairly high compared with
conventional MOSFETs, while remaining completely in control.
To summarize, dv/dt during turn off is limited either by discharging the gate-drain capacitance (Rg
control) or by the charging rate of the output capacitance (Coss limited).
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
4
Circuit Design and Layout Recommendations
There are a number of recommendations to make with regards to circuit design and layout practices which will
assure a combination of high performance and reliability. They can be recommended as if “in order of
importance”, but realistically all are important, both in contribution toward circuit stability and reliability as well as
overall efficiency and performance. They are not that dissimilar to recommendations made for the introduction of
MOSFETs compared to bipolar transistors, or CoolMOS compared with standard MOSFETs; it is a matter of the
degree of care.
Control dv/dt and di/dt by proper selection of gate resistor
In order to exert full Rg control
on the device maximum turn-off
dv/dt we recommend the
following procedure:
1. Check for highest
peak current in the
application.
2. Choose Rg
accordingly not to
exceed 50V/ns.
200000
Rg= 3.3 ohm
Rg= 6.8 ohm
Rg= 13 ohm
Rg= 33 ohm
Rg= 68 ohm
180000
160000
dv/dt, Turn Off [V/µs]
4.1
140000
120000
100000
80000
60000
40000
20000
3. At normal operation
condition quasi ZVS
condition can be
expected, which
gives best efficiency
results.
0
0
2
4
6
8
10
12
14
16
18
Load Current [A]
Figure 16 dv/dt for different load currents and gate drive resistances
for IPW60R199CP (switching to 400V, Tj=125 °C).
Table 4 gives the Rg values for 50 V/ns and 30 V/ns at rated nominal current for each part as a quick
guideline. Figure 16 also shows the turn-off dv/dt behavior for IPW60R199CP with several Rg values from
3.3 Ohms to 68 Ohms. An Rg value of 30 Ohm looks fairly optimal in order to exert full Rg for high currents
and still keep quasi ZVS condition at lower currents. Keep in mind that the gate resistor scales with device
size and area related capacitance. The value for Rg inversely scales with different MOSFETs. Further
detailed switching characteristics can be found in Appendix.
CoolMOSTM Type
RDSon,max
ID
Rg for dv/dt < 50V/ns
Rg for dv/dt < 30V/ns
IPP60R385CP
385 mΩ
9A
30 Ω
64 Ω
IPP60R299CP
299 mΩ
11 A
30 Ω
62 Ω
IPP60R199CP
199 mΩ
16 A
30 Ω
60 Ω
IPP60R165CP
165 mΩ
21 A
26 Ω
50 Ω
IPP60R125CP
125 mΩ
25 A
19 Ω
37 Ω
IPP60R099CP
99 mΩ
31 A
15 Ω
28 Ω
IPW60R045CP
45 mΩ
60 A
10.5 Ω
17.5 Ω
Table 4 Design guideline showing necessary gate resistance values for reaching dv/dt turn off values
below 50 V/ns and 30 V/ns, respectively.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
4.2
Minimize parasitic gate-drain board capacitance
Particularly care must be spent on the coupling capacitances between gate and drain traces on the PCB. As fast
switching MOSFETs are capable to reach extremely high dv/dt values any coupling of the voltage rise at the drain
into the gate circuit may disturb proper device control via the gate electrode. As the CoolMOSTM CP series
reaches extremely low values of the internal Cgd capacitance (Crss in datasheet), we recommend keeping layout
coupling capacitances below the internal capacitance of the device to exert full device control via the gate circuit.
Figure 17 shows a good example, where the gate and drain traces are either perpendicular to each other or go
into different directions with virtually no overlap or paralleling to each other. A “bad “ layout example is shown as
reference to the good layout in Figure 19.
If possible, use source foils or ground-plane to shield the gate from the drain connection.
4.3
Use gate ferrite beads
We strongly recommend the use of ferrite beads in the gate as close as possible to the gate electrode to
suppress any spikes, which may enter from drain dv/dt into the gate circuit. As the ferrite bead sees a peak pulse
current determined by external Rg and gate drive, it should be chosen for this pulse current. Choose the ferrite
bead small enough in order not to slow down normal gate waveforms but attenuation enough to suppress
potential spikes at peak load current conditions. A suitable example is Murata BLM41PG600SN1, in an 1806
SMD package. It is rated for 6A current and a DCR of 10 mOhms, with about 50-60 Ohms effective attenuation
above 100 Mhz.
4.4
Locate gate drivers and gate turn-off components as close as possible to the gate.
Always locate the gate drive as close as possible to the driven MOSFET and the gate resistor in close proximity
of the gate pin (as an example, see R1 in Figure 17). This prevents it acting as an antenna for capacitively
coupled signals. The controller/IC driver should be capable of providing a strong “low” level drive with voltage as
near to ground as possible- MOS or bipolar/MOS composite output stages work well in that regard, due to low
output saturation voltages. While some drivers may be deemed to have sufficient margin under static or “DC”
conditions, with ground bounce, source inductance drop, etc, the operating margin to assure “off” mode can
quickly disappear.
4.5
Use symmetrical layout for paralleling MOSFETs, and good isolation of Gate drive between FETs
We recommend the use of multi-channel gate drivers in order to have separate channels for each MOSFET.
Physical layout should be as symmetrical as possible, with the low impedance driver located as close as possible
to the MOSFETs and on a symmetric axis.
4.6 How to best make of use of the high performance of CoolMOSTM CP
TM
To summarize, below recommendations are important when designing in CoolMOS CP to reach highest
efficiency with clean waveforms and low EMI stress.
9
Control dv/dt and di/dt by proper selection of gate resistor
9
Minimize parasitic gate-drain capacitance on board
9
Use gate ferrite beads
9
Locate gate drivers and gate turn-off components as close as possible to the gate
9
Use symmetrical layout for paralleling
14 of 32
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Two independent
Totem Pol Drivers
as close as
possible to the
MOSFET!
View Top Layer
Minimized couple
capacitance
between gate and
drain pin!
View Bottom Layer
Heatsink
Heatsink
Separate and short
source inductance to
reference point for gate
drive!
Heatsink is connected to source (GND)!!
Figure 17 Good layout example ensuring clean waveforms when designing in CoolMOSTM CP.
Figure 18 Good layout example showing schematic for PCB layout in Figure 17.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Decoupling
capacitor far away
from gate pin of
the MOSFET & ONLY
One Driver Stage
for two MOSFET
High source inductance
-
GND connection of the
decoupling capacitor C2
far away from the driver
stage
Heatsink
High parasitic
capacitance between
gate and drain!
Figure 19 Bad layout example.
Figure 20 Schematic for bad layout example in Figure 19.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
5
MOSFET Selection for the Application Based on Loss Balance
Final thoughts will be offered on optimizing the SMPS performance and cost through analysis of loss balance. For
any given MOSFET technology there is a figure of merit based upon the balance of resistive losses and dynamic
losses.
Improved MOSFET technologies will offer lower Coss related losses in proportion to Ron. If a specific application
is examined with regards to the RMS conduction loss based on the variable RDS[on] and the switching loss
based on dynamic factors (usually a combination of Coss pumping loss and crossover transition loss) a chip size
with even balance of losses will provide the minimum total loss at the full load operating point. However, the
slopes of the loss factors are not equivalent, and so considering the widest range of operating loads, the best
efficiency and economics may occur working in a mode with higher conduction than switching losses at full load,
especially in the case of redundant configured power supplies that normally operate at less than 1/2 of rated
maximum output.
The analysis problem can be approached from a few different angles. Let’s take as a starting example an
interleaved two transistor forward converter (ITTF) designed for 1 kW output power, with the assumption of about
90% efficiency, which will require an input power of about 1100W. The maximum output current in the switches at
minimum bus voltage has been calculated using:
(6)
where VIn_min is the minimum operating bulk bus voltage, POut_Max is the output power, and Dmax is the
calculated maximum duty cycle (based on transformer turns ratio primary to secondary). Let’s say that as a first
pass the best in class TO220 600V CP CoolMOS™ is chosen for consideration due to its very low RDS[on] for
this package type. Then, the conduction loss can be calculated for an elevated junction temperature RDS[on] of
150 mΩ from
(7)
This looks good, but perhaps too good? What about dynamic losses? As a first cut, the Coss pumping losses can
be estimated from the energy equivalent output capacitance (CO(ER)) (integrated over 0 to 480V) in the
datasheet:
(8)
Notice the imbalance in losses in this preliminary calculation. Switching losses can be further investigated using
Eon and Eoff curves. These curves can be found in Appendix. The principle is the same, multiplying Eon and Eoff
times the switching frequency, and summing the results.
Another more conventional, perhaps simplistic, approach is to estimate the dynamic losses just from the
crossover times (Eqn 9), which may be reasonably valid in the gate control switching region discussed earlier.
(9)
The picture which is clearly emerging, though, is that for a 1 kW, 130 kHz ITTF converter the 60R099 is more
silicon than optimum. A detailed investigation will show that the 60R199 will offer about 15-20% lower losses, and
much better economics.
In Figure 21 the total conduction and capacitive losses are analyzed with RDSon being the variable function.
Switching losses are not taken into account as they do not depend on RDSon. This example is built around an
500W TTF (two transistor forward) stage, 130 kHz and the junction temperature for calculation purposes is
105 °C.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Compared even with other superjunction MOSFETs, the very low dynamic losses of CoolMOS™ CP can match
the overall losses of competitors while having a 60% or higher RDS[on]. This conveys some significant
advantages in chip size, package options, and cost, as well as opportunities to improve performance and thermal
density.
ITTF: one stage with 500 W, 130 kHz, hard sw @ 200 V
4
Power losses [W]
3
conduction losses
capacitive losses CP series
CoolMOS CP series
Competitor A, SJ
Competitor A, conv MOS
Competitor B
Competitor C
Competitor D
2
1
0
0
50
100
150
200
250
300
RDSon [mOhm]
Figure 21 Calculated total power losses as a function of RDSon for one 500W TTF, as an example of
1000W ITTF, with switching frequency= 130 kHz, Tj=105°C.
Power losses [W]
How does this workout in more
20
demanding applications, such
as wide input range power
factor correction with a high
clock frequency to reduce the
15
boost inductor size? In this
case, the performance of the
conduction losses
boost
rectifier
diode
in
10
continuous conduction mode
capacitive losses
PFC is the gating factor- having
CoolMOS CP 600 V series
a direct influence on the turn-on
CoolMOS C3 600 V series
losses
observed
in
the
5
Comp A, SJ, 500 V
MOSFET. By using a thinQ!
Comp B, conv MOSFET, 500 V
2G™ silicon carbide Schottky
diode, a nearly ideal diode is
0
possible, and the switching
0
50
100
150
200
250
300
losses are governed mostly by
RDSon [mOhm]
the MOSFET capabilities. The
results are seen in the graph of
Figure 22 Calculated total Losses as a function of RDSon for an 800W
Figure 22, which shows the
PFC converter, with switching frequency=250 kHz, 110 V input voltage.
possibility of matching power
losses at full load with a
MOSFET of much higher
RDSon. Besides the economic reasons for doing this, the reduction in output capacitance related dynamic losses
with the smaller chip MOSFET will pay back good dividends with improved moderate and low load efficiency,
especially at high line operation.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
6
Examples of Application Benefits with CoolMOSTM CP
With today’s trend of universal input voltage range for world-wide use, a low RDSon becomes a key requirement
in active PFC converters as under low line conditions power losses are at its peak due to maximum current
requirement.
Replacement of several paralleled MOSFETs by fewer components of new CooMOSTM CP series
Reduction of part count will save space on the PCB board and largely facilitate gate driving. Especially versatile
replacements are 2x 190mOhm or 2x 170mOhm by 1x 99mOhm, or 3x 190/170mOhm by 2x 125mOhm. The
design will benefit from a lower energy stored in the output capacitance, lower gate drive power and the higher
switching speed. With the highest thermal resistance being heat sink to ambient the effective increase of thermal
resistance junction to ambient is relatively small. The reduction of number of parts is therefore highly applicable.
Level of Integration
Example 1: 600 W CCM PFC stage, 130 kHz
CoolMOSTM CP
Different power MOSFETs, all TO220
packages, were measured under low-line
condition 90VAC. Highest PFC efficiency was
obtained with one 99 mOhm CoolMOSTM CP
(Figure 23). The reference parts were rated at
500V in order to use lowest available RDSon
in the comparison.
99mOhm max, 600V
CoolMOSTM C3
190mOhm max, 600V
Other SJ MOSFET
250mOhm max, 500V
Standard MOSFET
250mOhm max, 500V
Standard MOSFET
520mOhm max, 500V
93%
94%
93.5 %
Figure 23 Level of integration for TO220 MOSFET devices
in a 600 W CCM PFC stage, 130 kHz, 90VAC input
voltage. Source: ISLE Institute, Germany.
Example 2: 800 W Evaluation server board
95,0
90,0
System efficiency [%]
An 800W Evaluation server board
was designed with 85…265VAC
input and 1U form factor. The PFC
stage uses one TO247 600V
CoolMOSTM CP with 45 mOhm, as
shown in Figure 24. Further
information about the evaluation
board can be found in an
application note [5].
85,0
One TO247 CoolMOSTM CP for 800W PFC stage
80,0
Vin 230 V
Vin 110 V
Vin 85 V
75,0
70,0
0
100
200
300
400
500
600
700
800
900
Output power [W]
Figure 24 System efficiency versus load for different input voltages
of an 800W Evaluation server board.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
For hard-switching applications such as CCM PFC, two-transistor forward (TTF), interleaved TTF, and halfbridge, CoolMOSTM CP is the ideal switch
Example 3: 500W Silverbox using TTF topology
87.5
IPA50R199CP
Silverbox 500W
87.0
199 mOhm
TTF; 400Vdc input
86.5
Efficiency [%]
86.0
250 mOhm
85.5
SPA21N50C3
IPA50R250CP
other SJ MOS
500V/250mOhm
85.0
520 mOhm
84.5
other SJ MOS
500V/250mOhm
IPA50R520CP
84.0
83.5
83.0
other SJ Mos
500V/520mOhm
82.5
Standard MOS
500V/520mOhm
0
100
200
300
400
500
Output Power [W]
Figure 25 DC-DC stage efficiency for a 500W Silverbox (commerciably available), comparing
500V CoolMOSTM CP with other 500V MOSFETs.
As seen in Figure 25 500V CoolMOSTM CP gives lowest efficiency per RDSon class in a TTF stage in a 500W
commerciably available silverbox power supply.
TM
CoolMOS
CP enables higher operating frequencies
Changing from less advanced SJ technologies or conventional MOSFETs to new CoolMOSTM series with identical
RDS,on enables a higher system frequency. The much faster switching speed, lower energy stored in the output
capacitance and lower required gate drive power will enable a higher operation frequency, for example up to
130 kHz or 250 kHz. This will result in smaller passive components and hence a reduction in form factor.
20 of 32
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
7
Product Portfolios
With CoolMOSTM CP series a new naming system for CoolMOSTM products is taken into place, explained in
Figure 26.
I P P 60 R 099 CP
Infineon
Voltage Class divided by 10
Power MOSFETs
R for Rdson
Package code
Rdson in mOhm
P=TO220
W=T0247
A=TO220FullPAK
D=DPAK
I=I2PAK
B=D2PAK
etc
Series Name
CP
Figure 26 Naming system for CoolMOSTM CP products.
TO-252
(D-PAK)
TO-262
(I²PAK)
TO-220FP
TO-220
TO-263
(D2PAK)
IPI60R385CP
IPA60R385CP
IPP60R385CP
IPB60R385CP
0.299
Ω
IPI60R299CP
IPA60R299CP
IPP60R299CP
0.199
Ω
IPI60R199CP
IPA60R199CP
IPP60R199CP
IPB60R199CP
IPW60R199CP
0.165
Ω
IPA60R165CP
IPP60R165CP
IPB60R165CP
IPW60R165CP
0.125
Ω
IPA60R125CP
IPP60R125CP
0.385
Ω
IPD60R385CP
0.099
Ω
IPP60R099CP
0.045
Ω
TO-247
IPW60R385CP
IPW60R299CP
IPW60R125CP
IPB60R099CP
IPW60R099CP
IPW60R045CP
Figure 27 CoolMOSTM CP 600V products
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
TO-251 short
(I-PAK
Short leads)
TO-252
(D-PAK)
TO-262
(I²-PAK)
TO-220FP
TO-220
TO-263
(D2PAK)
TO-247
!
NEW
!
NEW
!
NEW
!
NEW
IPS50R520CP
IPD50R520CP
IPA50R520CP
IPP50R520CP
!
NEW
!
NEW
!
NEW
IPA50R399CP
IPP50R399CP
IPW60R399CP
!
NEW
!
NEW
IPA50R350CP
IPP50R350CP
0.299
Ω
!
NEW
!
NEW
IPA50R299CP
IPP50R299CP
0.250
Ω
!
NEW
!
NEW
IPA50R250CP
IPP50R250CP
0.199
Ω
IPA50R199CP
0.140
Ω
0.520
Ω
0.399
Ω
0.350
Ω
!
NEW
!
NEW
IPD50R399CP
IPI50R399CP
!
NEW
IPI50R350CP
!
NEW
!
NEW
!
NEW
IPB50R299CP
!
NEW
IPB50R250CP
!
NEW
!
NEW
IPW60R199CP
IPP50R199CP
IPB50R199CP
!
NEW
!
NEW
!
NEW
!
NEW
IPA50R140CP
IPP50R140CP
IPB50R140CP
IPW60R140CP
Figure 28 CoolMOSTM CP 500V products
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
8
References
[1]
1997.
T. Fujihira: “Theory of Semiconductor Superjunction Devices”, Jpn.J.Appl.Phys., Vol. 36, pp. 6254-6262,
[2]
A.W. Ludikhuize, "A review of the RESURF technology", Proc. ISPSD 2000, pp. 11-18.
[3]
X. B. Chen and C. Hu, “Optimum doping profile of power MOSFET’s epitaxial Layer.” IEEE Trans.
Electron Devices, vol. ED-29, pp. 985-987, 1982.
[4]
G. Deboy, M. März, J.-P. Stengl, H. Strack, J. Tihanyi, H. Weber, “A new generation of high voltage
MOSFETs breaks the limit of silicon”, pp. 683-685, Proc. IEDM 98, San Francisco, Dec. 1998.
[5]
F. Bjoerk, “800W Evaluation server board”, Application Note, www.infineon.com/CoolMOS
[6]
G. Deboy, F. Dahlquist, T. Reimann and M. Scherf: “Latest generation of Superjunction power MOSFETs
permits the use of hard-switching topologies for high power applications”, Proceedings of PCIM Nürnberg, 2005,
pp. 38-40.
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
Appendix – Typical Dynamic Switching Characteristics of CoolMOSTM CP 600V
IPP60R385CP, Tj = 125 °C, VGS=+13 V / 0 V
0.1
Rg= 6.2 Ohm
Rg= 12 Ohm
Rg= 24 Ohm
Rg= 62 Ohm
Rg= 120 Ohm
0.09
Eon, Turn On [mJ]
0.08
0.07
0.06
Eon
0.05
0.04
0.03
0.02
0.01
0
0
1
2
3
4
5
6
7
8
9
10
7
8
9
10
Load Current [A]
0.12
Rg= 6.2 Ohm
Rg= 12 Ohm
Rg= 24 Ohm
Rg= 62 Ohm
Rg= 120 Ohm
Eoff, Turn Off [mJ]
0.1
0.08
Eoff
0.06
0.04
0.02
0
0
1
2
3
4
5
6
Load Current [A]
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CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
IPP60R385CP, Tj = 125 °C, VGS=+13 V / 0 V
140000
Rg= 6.2 ohm
Rg= 12 ohm
Rg= 24 ohm
Rg= 62 ohm
Rg= 120 ohm
dv/dt, Turn Off [V/µs]
120000
100000
Turn-off
dv/dt
80000
60000
40000
20000
0
0
1
2
3
4
5
6
7
8
9
7
8
9
10
Load Current [A]
3500
Rg= 6.2 ohm
Rg= 12 ohm
Rg=24 ohm
Rg= 62 ohm
Rg= 120 ohm
di/dt, Turn Off [A/µs]
3000
2500
Turn-off
di/dt
2000
1500
1000
500
0
0
1
2
3
4
5
6
Load Current [A]
25 of 32
10
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
IPP60R199CP, Tj = 125 °C, VGS=+13 V / 0 V
0.16
Rg= 3.3 ohm
Rg= 6.8 ohm
Rg= 13 ohm
Rg= 33 ohm
Rg= 68 ohm
0.14
Eon, turn on [ mJ]
0.12
0.1
Eon
0.08
0.06
0.04
0.02
0
0
2
4
6
8
10
12
14
16
18
Load Current [A]
0.2
Rg= 3.3 ohm
Rg= 6.8 ohm
Rg= 13 ohm
Rg= 33 ohm
Rg= 68 ohm
0.18
Eoff, turn off [mJ]
0.16
0.14
0.12
Eoff
0.1
0.08
0.06
0.04
0.02
0
0
2
4
6
8
10
Load Current [A]
26 of 32
12
14
16
18
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
IPP60R199CP, Tj = 125 °C, VGS=+13 V / 0 V
200000
Rg= 3.3 ohm
Rg= 6.8 ohm
Rg= 13 ohm
Rg= 33 ohm
Rg= 68 ohm
180000
dv/dt, Turn Off [V/µs]
160000
140000
120000
Turn-off
dv/dt
100000
80000
60000
40000
20000
0
0
2
4
6
8
10
12
14
16
18
Load Current [A]
5000
Rg= 3.3 ohm
Rg= 6.8 ohm
Rg= 13 ohm
Rg= 33 ohm
Rg= 68 ohm
4500
di/dt, Turn Off [A/µs]
4000
3500
3000
Turn-off
di/dt
2500
2000
1500
1000
500
0
0
2
4
6
8
10
Load Current [A]
27 of 32
12
14
16
18
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
IPP60R099CP, Tj = 125 °C, VGS=+13 V / 0 V
0.35
Rg= 1.8 Ohm
0.3
Eon
Rg= 3.6 Ohm
Eon, Turn On [mJ]
Rg= 7.5 Ohm
0.25
Rg= 18 Ohm
Rg= 36 Ohm
0.2
0.15
0.1
0.05
0
0
5
10
15
20
25
30
35
Load Current [A]
Rg= 3.3 ohm
Rg= 6.8 ohm
0.6
Rg= 1.8 Ohm
Eoff, Turn Off [mJ]
Eoff
Rg= 3.6 Ohm
0.5
Rg= 7.5 Ohm
Rg= 18 Ohm
0.4
Rg= 36 Ohm
0.3
0.2
0.1
0
0
5
10
15
20
Load Current [A]
28 of 32
25
30
35
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
IPP60R099CP, Tj = 125 °C, VGS=+13 V / 0 V
180000
Rg= 1.8 ohm
dv/dt, Turn Off [V/µs]
160000
Turn-Off
dv/dt
Rg= 3.6 ohm
Rg= 7.5 ohm
140000
Rg= 18 ohm
120000
Rg= 36 ohm
100000
80000
60000
40000
20000
0
0
5
10
15
20
25
30
35
Load Current [A]
9000
8000
Rg= 1.8 ohm
di/dt, Turn Off [A/µs]
7000
Rg= 3.6 ohm
Rg=7.5 ohm
6000
Turn-off
di/dt
Rg= 18 ohm
5000
Rg= 36 ohm
4000
3000
2000
1000
0
0
5
10
15
20
Load Current [A]
29 of 32
25
30
35
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
IPW60R045CP, Tj = 125 °C, VGS=+13 V / 0 V
0.8
Rg= 0.9 Ohm
Rg= 1.8 Ohm
Rg= 3.6 Ohm
Rg= 9.1 Ohm
Rg= 18 Ohm
Eon, Turn On [mJ]
0.7
0.6
0.5
Eon
0.4
0.3
0.2
0.1
0
0
10
20
30
40
50
60
70
Load Current [A]
1.4
Rg= 0.9 Ohm
Rg= 1.8 Ohm
Rg= 3.6 Ohm
Rg= 9.1 Ohm
Rg= 18 Ohm
Eoff, Turn Off [mJ]
1.2
1
Eoff
0.8
0.6
0.4
0.2
0
0
10
20
30
40
Load Current [A]
30 of 32
50
60
70
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
IPW60R045CP, Tj = 125 °C, VGS=+13 V / 0 V
200000
Rg= 0.9 ohm
Rg= 1.8 ohm
Rg= 3.6 ohm
Rg= 9.1 ohm
Rg= 18 ohm
180000
dv/dt, Turn Off [V/µs]
160000
140000
120000
Turn-off
dv/dt
100000
80000
60000
40000
20000
0
0
10
20
30
40
50
60
70
Load Current [A]
8000
Rg= 0.9 ohm
Rg= 1.8 ohm
Rg= 3.6 ohm
Rg= 9.1 ohm
Rg= 18 ohm
di/dt, Turn Off [A/µs]
7000
6000
5000
Turn-off
di/dt
4000
3000
2000
1000
0
0
5
10
15
20
Load Current [A]
31 of 32
25
30
35
CoolMOSTM CP
- How to make most beneficial use of the latest
generation of super junction technology devices
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see the address list on the last page or
our webpage at
http://www.infineon.com
CoolMOS and CoolSET are trademarks of Infineon Technologies AG.
Edition 2006-01
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
LEGAL DISCLAIMER
THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION
OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY
DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE
INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY
ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON TECHNOLOGIES HEREBY
DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY
THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body, or to support and/or maintain and
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
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