TI TPA2000D1TPWRQ1

SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
D Qualification in Accordance With
D
D
D
D
D
D 4 mm × 4 mm MicroStarE Junior BGA and
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Modulation Scheme Optimized to Operate
Without a Filter
Extremely Efficient Third Generation 5-V
Class-D Technology:
− Low-Supply Current (No Filter) . . . 4 mA
− Low-Supply Current (Filter) . . . 7.5 mA
− Low-Shutdown Current . . . 0.05 µA
− Low-Noise Floor . . . 40 µVRMS
(No-Weighting Filter)
− Maximum Efficiency Into 8 Ω, 75 − 85 %
− 4 Internal Gain Settings . . . 6 − 23.5 dB
− PSSR . . . −77 dB
D
D
D
D
TSSOP Package Options
2 W Into a 4-Ω Speaker (THD+N<1%)
<0.2% THD+N at 1.5 W, 1 kHz, Into a 4-Ω
Load
Integrated Depop Circuitry
Short-Circuit Protection (Short to Battery,
Ground, and Load)
PW PACKAGE
(TOP VIEW)
INP
INN
SHUTDOWN
GAIN0
GAIN1
PVDD
OUTP
PGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BYPASS
AGND
COSC
ROSC
VDD
PVDD
OUTN
PGND
† Contact Texas Instruments for details. Q100 qualification data
available on request.
description
The TPA2000D1 is a 2-W mono bridge-tied-load (BTL) class-D amplifier designed to drive a speaker with at
least 4-Ω impedance. The amplifier uses Texas Instruments third generation modulation technique, which
results in improved efficiency and SNR. It also allows the device to be connected directly to the speaker without
the use of the LC output filter commonly associated with class-D amplifiers (this results in EMI which must be
shielded at the system level). These features make the device ideal for use in devices where high efficiency is
needed to extend battery run time.
The gain of the amplifier is controlled by two input terminals, GAIN1 and GAIN0. This allows the amplifier to be
configured for a gain of 6, 12, 18, and 23.5 dB. The differential input terminals are high-impedance CMOS inputs
and can be used as summing nodes.
The class-D BTL amplifier includes depop circuitry to reduce the amount of turnon pop at power up and when
cycling SHUTDOWN.
The TPA2000D1 is available in the 16-pin TSSOP and MicroStar Junior BGA packages that drives 2 W of
continuous output power into a 4-Ω load. The TPA2000D1T operates over an ambient temperature range of
−40°C to 105°C.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C
TSSOP (PW)
Tape and Reel TPA2000D1TPWRQ1
20001T
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar is a trademark of Texas Instruments.
Copyright  2002 − 2004, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
functional block diagram
VDD
AGND
VDD
PVDD
Gain
Adjust
INN
+
_
_
Deglitch
Logic
Gate
Drive
OUTN
+
_
+
PGND
+
_
PVDD
+
_
Gain
Adjust
INP
_
Deglitch
Logic
+
Gate
Drive
OUTP
PGND
SHUTDOWN
GAIN1
Gain
GAIN0
2
Biases
and
References
Start-Up
Protection
Logic
Ramp
Generator
COSC
ROSC
BYPASS
Thermal
OC
Detect
VDD ok
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
GQC
PW
A3 − A5,
B2 − B6
C2 − C6
D2 − D4
15
I
Analog ground
BYPASS
A6
16
I
Connect capacitor to ground for BYPASS voltage filtering.
COSC
B7
14
I
Connect capacitor to ground to set oscillation frequency.
GAIN0
C1
4
I
Bit 0 of gain control (TTL logic level)
GAIN1
D1
5
I
Bit 1 of gain control (TTL logic level)
INN
A1
2
I
Negative differential input
INP
A2
1
I
Positive differential input
OUTN
G7
10
O
Negative BTL output
OUTP
G1
7
O
Positive BTL output
PGND
D5, D6
E2 − E6
F2 − F6
G2 − G6
8, 9
I
High-current grounds
PVDD
E1, E7,
F1, F7
6, 11
I
High-current power supplies
ROSC
C7
13
I
Connect resistor to ground to set oscillation frequency.
SHUTDOWN
B1
3
I
Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal, and normal
operation if a TTL logic high is placed on this terminal.
VDD
D7
12
I
Analog power supply
AGND
2
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• DALLAS, TEXAS 75265
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted){
Supply voltage, VDD, PVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5.5 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD +0.3 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table)
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 115°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
{ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
TA ≤ 25°C
774 mW
PACKAGE
PW
DERATING FACTOR
TA = 70°C
495 mW
6.19 mW/°C
TA = 85°C
402 mW
TA = 105°C
279 mW
recommended operating conditions
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Supply voltage, VDD, PVDD
High-level input voltage, VIH
GAIN0, GAIN1, SHUTDOWN
Low-level input voltage, VIL
GAIN0, GAIN1, SHUTDOWN
MIN
MAX
2.7
5.5
2
UNIT
V
V
0.7
V
Switching frequency, fS
200
300
kHz
Operating free-air temperature, TA
−40
105
°C
electrical characteristics at specified free-air temperature, PVDD = 5 V, TA = 25°C (unless otherwise
noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage (measured differentially)
PSRR
Power supply rejection ratio
|IIH|
High-level input current
|IIL|
Low-level input current
IDD
Supply current, no filter (with or without speaker
load)
IDD(SD)
Supply current, shutdown mode
MIN
VI = 0 V,
AV = any gain
PVDD = 4.9 V to 5.1 V
PVDD = 5.5,
PVDD = 5.5,
TYP
MAX
25
−77
mV
dB
1
µA
1
µA
4
7
mA
0.05
28
µA
VI = PVDD
VI = 0 V
GAIN0, GAIN1, SHUTDOWN = 0 V
UNIT
operating characteristics, PVDD = 5 V, TA = 25°C, RL = 4 Ω, gain = 6 dB (unless otherwise noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
PO
THD + N
Output power
THD = 1%,
f = 1 kHz,
Total harmonic distortion plus noise
Supply ripple rejection ratio
PO = 1.5 W,
f = 1 kHz,
f = 20 Hz to 20 kHz
kSVR
SNR
Signal-to-noise ratio
Vn
Output noise voltage (no-noise weighting filter)
Zi
Input impedance
CBYP = 1 µF,
POST OFFICE BOX 655303
CBYP = 1 µF
f = <10 Hz to 22 kHz
• DALLAS, TEXAS 75265
MIN
TYP
2
MAX
UNIT
W
<0.2%
−67
dB
95
dB
40
µV(rms)
>15
kΩ
3
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
electrical characteristics at specified free-air temperature, PVDD = 3.3 V, TA = 25°C (unless
otherwise noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage (measured differentially)
PSRR
Power supply rejection ratio
|IIH|
High-level input current
|IIL|
Low-level input current
IDD
Supply current, no filter (with or without speaker
load)
IDD(SD)
Supply current, shutdown mode
MIN
VI = 0 V,
AV = any gain
PVDD = 3.2 V to 3.4 V
PVDD = 3.3,
PVDD = 3.3,
TYP
MAX
UNIT
25
mV
1
µA
1
µA
4
7
mA
0.05
28
µA
−61
dB
VI = PVDD
VI = 0 V
operating characteristics, PVDD = 3.3 V, TA = 25°C, RL = 4 Ω, gain = 6 dB (unless otherwise noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
MIN
PO
THD + N
Output power
THD = 1%,
f = 1 kHz
Total harmonic distortion plus noise
f = 20 Hz to 20 kHz
kSVR
Supply ripple rejection ratio
PO = 55 mW,
f = 1 kHz,
SNR
Signal-to-noise ratio
Vn
Output noise voltage (no-noise weighting filter)
CBYP= 1 µF,
f = <10 Hz to 22 kHz
Zi
Input impedance
850
CBYP = 1 µF
Table 1. Gain Settings
4
AMPLIFIER GAIN
(dB)
INPUT IMPEDANCE
(kΩ)
TYP
TYP
6
104
1
12
74
0
18
44
1
23.5
24
GAIN0
GAIN1
0
0
0
1
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
MAX
UNIT
mW
<0.2%
−61
dB
93
dB
40
µV(rms)
>15
kΩ
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
η
Efficiency
vs Output power
1
FFT at 1.5-W output power
vs Frequency
2
vs Output power
THD+N
Total harmonic distortion + noise
kSVR
Supply ripple rejection ratio
3, 4, 5
vs Frequency
6, 7
vs Frequency
8
test setup for graphs
The THD+N measurements shown do not use an LC output filter, but do use a 100-Ω 0.047-µF RC low-pass
filter with a cutoff frequency of ~30 kHz before the audio analyzer, so the switching frequency does not dominate
the measurement. This is done to ensure that the THD+N measured is just the audible THD+N. The THD+N
measurements are shown at the highest gain for worst case. The efficiency was measured with no filters and
a 3-Ω, 4-Ω, or 8-Ω resistor in series with a 33-µH inductor as the load.
EFFICIENCY
vs
OUTPUT POWER
100
RL = 8 Ω, 33 µH
RL = 4 Ω, 33 µH
90
80
RL = 3 Ω, 33 µH
Efficiency − %
70
60
50
Class-AB,
RL = 4 Ω
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
PO − Output Power − W
Figure 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
FFT AT 1.5-W OUTPUT POWER
vs
FREQUENCY
+10
VDD = 5 V,
RL = 4 Ω,
f = 1 kHz,
PO = 1.5 W
−10
Power − VdB
−30
−50
−70
−90
−110
−130
−150
0
4k
8k
12 k
f − Frequency − Hz
16 k
20 k
24 k
Figure 2
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
2
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
VDD = 5 V,
Gain = 23.5,
RL = 3 Ω
1
f = 1 kHz
0.2
0.1
f = 20 Hz
0.02
0.01
0.01
10 m
f = 20 kHz
100 m 200 m
1
3
10
2
VDD = 5 V,
Gain = 23.5,
RL = 4 Ω
1
f = 1 kHz
0.2
0.1
f = 20 Hz
0.02
0.01
f = 20 kHz
0.001
10 m
PO − Output Power − W
Figure 3
6
100 m 200 m
PO − Output Power − W
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
3
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VDD = 5 V,
Gain = 23.5,
RL = 8 Ω
2
1
0.2
f = 1 kHz
0.1
f = 20 Hz
0.02
0.01
f = 20 kHz
0.001
10 m
100 m 200 m
1
1
VDD = 5 V,
f = 1 kHz,
RL = 4 Ω
0.2
0.1
PO = 1.5 W
0.02
0.01
PO = 0.75 W
PO = 2 W
0.001
20
3
100 200
Figure 5
2k
10 k
20 k
Figure 6
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
−40
1
VDD = 5 V,
f = 1 kHz,
RL = 8 Ω
K(SVR) − Supply Ripple Rejection Ratio − dB
THD+N − Total Harmonic Distortion Plus Noise − %
1k
f − Frequency − Hz
PO − Output Power − W
0.2
PO = 0.1 W
0.1
0.02
0.01
PO = 1 W
PO = 0.5 W
−45
−50
−55
−60
−65
−70
−75
−80
0.001
20
100 200
1k
2k
10 k 20 k
10
100 200
1k 2k
10 k 20 k
f − Frequency −Hz
f − Frequency − Hz
Figure 7
Figure 8
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• DALLAS, TEXAS 75265
7
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
eliminating the output filter with the TPA2000D1
This section explains why the user can eliminate the output filter with the TPA2000D1.
effect on audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
traditional class-D modulation scheme
The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VDD. Therefore,
the differential pre-filtered output varies between positive and negative VDD, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 9. Even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing
high loss, thus causing a high supply current.
OUTP
OUTN
+5 V
Differential Voltage
Across Load
OV
−5 V
Current
Figure 9. Traditional Class-D Modulation Scheme’s Output Voltage and Current Waveforms Into an
Inductive Load With No Input
TPA2000D1 modulation scheme
The TPA2000D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive voltages. The duty cycle of OUTP is less than 50% and OUTN
is greater than 50% for negative voltages. The voltage across the load sits at 0 V throughout most of the
switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
8
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APPLICATION INFORMATION
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+5 V
0V
−5 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+5 V
0V
Across
Load
−5 V
Current
Figure 10. The TPA2000D1 Output Voltage and Current Waveforms Into an Inductive Load
efficiency: why you must use a filter with the traditional class-D modulation scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VDD and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA2000D1 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VDD instead of 2 × VDD. As the output power increases, the pulses widen making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications, the filter is not needed.
An LC filter with a cut-off frequency less than the class-D switching frequency allows the switching current to
flow through the filter instead of the load. The filter has less resistance than the speaker that results in less power
dissipated, which increases efficiency.
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SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
effects of applying a square wave into a speaker
Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the
waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the
square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching
frequency, however, is not significant because the speaker cone movement is proportional to 1/f2 for
frequencies beyond the audio band. Therefore, the amount of cone movement at the switching frequency is
small. However, damage could occur to the speaker if the voice coil is not designed to handle the additional
power. To size the speaker for added power, the ripple current dissipated in the load needs to be calculated
by subtracting the theoretical supplied power (PSUP THEORETICAL) from the actual supply power (PSUP) at
maximum output power (POUT). The switching power dissipated in the speaker is the inverse of the measured
efficiency (ηMEASURED) minus the theoretical efficiency (ηTHEORETICAL) all multiplied by POUT.
PSPKR = PSUP – PSUP THEORETICAL (at max output power)
(1)
PSPKR = POUT(PSUP / POUT – PSUP THEORETICAL / POUT) (at max output power)
(2)
PSPKR = POUT(1/ηMEASURED – 1/ηTHEORETICAL) (at max output power)
(3)
The maximum efficiency of the TPA2000D1 with an 8-Ω load is 85%. Using Equation 3 with the efficiency at
maximum power (78%), we see that there is an additional 106 mW dissipated in the speaker. The added power
dissipated in the speaker is not an issue as long as it is taken into account when choosing the speaker.
when to use an output filter
Design the TPA2000D1 without the filter if the traces from amplifier to speaker are short. The TPA2000D1
passed FCC and CE radiated emissions with no shielding with speaker wires eight inches long or less. Notebook
PCs and powered speakers where the speaker is in the same enclosure as the amplifier are good applications
for class-D without a filter.
A ferrite bead filter (shown in Figure 11) can often be used if the design is failing radiated emissions without a
filter, and the frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass
FCC and CE because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead,
choose one with high impedance at high frequencies, but low impedance at low frequencies.
Use an output filter if the EMI sensitive circuits are low frequency (<1 MHz) and/or the leads from amplifier to
speaker are long.
The LC output filter is shown in Figure 11.
D L1 = L2 = 22 µH (DCR = 110 mΩ, part number = SCD0703T−220 M−S, manufacturer = GCI)
D C1 = C2 = 1 µF
The ferrite filter is shown in Figure 11, where L is a ferrite bead.
D L1 = L2 = ferrite bead (part number = MPZ1608S221, manufacturer = TDKI)
D C1 = C2 = 1 nF
10
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SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
L1
OUT+
C1
OUT−
L2
C2
Figure 11. Class-D Output Filter
gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA2000D1 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings are controlled
by ratios of resistors, so the actual gain distribution from part-to-part is quite good. However, the input
impedance may shift by 30% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 20 kΩ, which is the absolute minimum input impedance of the TPA2000D1. At the higher gain
settings, the input impedance could increase as high as 115 kΩ.
Table 2. Gain Settings
AMPLIFIER GAIN
(dB)
INPUT IMPEDANCE
(kΩ)
TYP
TYP
6
104
12
74
0
18
44
1
23.5
24
GAIN0
GAIN1
0
0
0
1
1
1
input resistance
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the −3 dB
or cutoff frequency also changes by over six times.
Zf
Ci
Input
Signal
IN
Zi
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SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
The −3-dB frequency can be calculated using Equation 4.
f *3 dB +
1
2p C iǒZ iǓ
(4)
input capacitor, Ci
In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a
high-pass filter with the corner frequency determined in Equation 5.
−3 dB
fc +
(5)
1
2 p Zi Ci
fc
The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
the example where Zi is 20 kΩ and the specification calls for a flat bass response down to 80 Hz. Equation 5
is reconfigured as Equation 6.
Ci +
1
2p Z i f c
(6)
In this example, Ci is 0.1 µF, so one would likely choose a value in the range of 0.1 µF to 1 µF. If the gain is known
and will be constant, use Zi from Table 1 to calculate Ci. A further consideration for this capacitor is the leakage
path from the input source through the input network (Ci) and the feedback network to the load. This leakage
current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high
gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at VDD/2, which is likely higher than the source dc level. Note that it
is important to confirm the capacitor polarity in the application.
Ci must be 10 times smaller than the bypass capacitor to reduce clicking and popping noise from power on/off
and entering and leaving shutdown. After sizing Ci for a given cutoff frequency, size the bypass capacitor to
10 times that of the input capacitor.
Ci ≤ CBYP / 10
12
(7)
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SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
power supply decoupling, CS
The TPA2000D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device VDD lead works best. For
filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near
the audio power amplifier is recommended.
midrail bypass capacitor, CBYP
The midrail bypass capacitor (CBYP) is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and
THD+N.
Bypass capacitor (CBYP) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended
for the best THD and noise performance.
Increasing the bypass capacitor reduces clicking and popping noise from power on/off and entering and leaving
shutdown. To have minimal pop, CBYP should be 10 times larger than Ci.
CBYP ≥ 10 × Ci
(8)
differential input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel.
To use the TPA2000D1 EVM with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA2000D1 with a single-ended
source, ac ground the INN input through a capacitor and apply the audio single to the input. In a single-ended
input application, the INN input should be ac-grounded at the audio source instead of at the device input for best
noise performance.
shutdown modes
The TPA2000D1 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal
should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the
outputs to mute and the amplifier to enter a low-current state, IDD(SD) = 1 µA. SHUTDOWN should never be left
unconnected because amplifier operation would be unpredictable.
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
POST OFFICE BOX 655303
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13
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
switching frequency
The switching frequency is determined using the values of the components connected to ROSC (pin 13) and
COSC (pin 14) and are calculated using Equation 9.
fs +
6.6
ROSC
(9)
COSC
The switching frequency was chosen to be centered on 250 kHz. This frequency represents the optimization
of audio fidelity due to oversampling and the maximization of efficiency by minimizing the switching losses of
the amplifier.
The recommended values are a resistance of 120 kΩ and a capacitance of 220 pF. Using these components
values, the amplifier operates properly by using 5% tolerance resistors and 10% tolerance capacitors. The
tolerance of the components can be changed as long as the switching frequency remains between 200 kHz and
300 kHz. Within this range, the internal circuitry of the device provides stable operation.
TPA2000D1
C2
Audio Input−
C3
1 µF
Audio Input+
1 µF
1 INP
2
BYPASS
INN
AGND
16
15
C7
1 µF
C1
3 SHUTDOWN
COSC
14
Gain Select
4 GAIN0
13 220 pF
Gain Select
5
To System
Controller
6
VDD
C8
10 µF
7
C4
1 µF
8
GAIN1
ROSC
VDD
PVDD
PVDD
OUTP
OUTN
PGND
PGND
R1
120 kΩ
12
C6
1 µF
11
VDD
VDD
OUT−
10
9
C5
1 µF
OUT+
Figure 12. Application Circuit
Table 3. TPA2000D1 Evaluation Bill of Materials
REFERENCE
DESCRIPTION
SIZE
QUANTITY
MANUFACTURER
PART NUMBER
C1
Capacitor, ceramic, 220 pF, ±10%, XICON, 50 V
0805
1
Mouser
140-CC501B221K
C2 − C7
Capacitor, ceramic, 1 µF, +80%/−20%, Y5V, 16 V
0805
6
Murata
GRM40-Y5V105Z16
C8
Capacitor, ceramic, 10 µF, +80%/−20%, Y5V, 16 V
1210
1
Murata
GRM235-Y5V106Z16
R1
Resistor, chip, 120 kΩ, 1/10 W, 5%, XICON
0805
1
Mouser
260−120K
U1
IC, TPA2000D1, audio power amplifier, 2-W, single
channel, class-D
24-pin
TSSOP
1
Texas Instruments
14
POST OFFICE BOX 655303
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TPA2000D1PW
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
low supply voltage pop
The TPA2000D1 pops when coming out of shutdown at low supply voltage (3.3 V and less) when using the
application schematic shown in Figure 12. The pops occur because the common-mode input range is worse
at the lower supply voltages. At low supply voltages, the inputs are not within the common-mode input range
when coming out of shutdown. The outputs develop an offset voltage until the inputs settle within the
common-mode input range, which causes a pop. Figure 13 shows 1-MΩ resistors added to form voltage
dividers. The voltage dividers bias the inputs to VDD/2 that keeps the pop low at turnon and when coming out
of shutdown. The resistors should be 1% tolerance to ensure the offset voltage is not increased.
VDD
1 MW
+
1 MW
Audio In
1 MW
INP
INN
TPA2000D1
−
1 MW
VDD
Figure 13. Voltage Dividers
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15
SGLS137B− SEPTEMBER 2002 − REVISED SEPTEMBER 2004
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
16
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPA2000D1TPWRQ1
ACTIVE
TSSOP
PW
Pins Package Eco Plan (2)
Qty
16
2000
TBD
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-1-235C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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