ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 November 2004 Application Note AN6064 Introduction The Lattice Semiconductor ispClock™5620 In-System-Programmable Analog Circuit allows designers to implement clock distribution networks supporting multiple, synchronized output frequencies using a single integrated circuit. By integrating a Phase-Locked Loop (PLL) along with multiple output dividers, the ispClock5620 can derive up to five separate output frequencies from a single input reference frequency. To facilitate the implementation of widefanout clock trees, the ispClock5620 provides up to 20 single-ended outputs or 10 differential outputs, organized as ten banks of two. Each output bank may be independently programmed to support different logic standards and operating options. Additionally, each single-ended output or differential output may be skew-adjusted to compensate for the effects of propagation delay along the PCB traces used in the distribution network. All configuration data is stored internally in E2CMOS® non-volatile memory. Programming a configuration is accomplished through an industry-standard JTAG IEEE 1149.1 interface. Figure 1. ispPAC-CLK5620-EV1 Evaluation Board ispPAC-CLK5620-EV1 Evaluation Board The ispPAC-CLK5620-EV1 evaluation board (Figure 1) allows the designer to quickly configure and evaluate the ispClock5620 on a fully assembled printed-circuit board. The four-layer board supports a 100-pin TQFP package, a header for user I/O and a JTAG programming cable connector. SMA connectors are installed to provide high-signal www.latticesemi.com 1 an6064_01 ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 Lattice Semiconductor integrity access to selected high-speed I/O signals. JTAG programming signals can be generated by using an ispDOWNLOAD® programming cable connected between the evaluation board and a PC’s parallel (printer) port. All user-programmable features of the ispPAC-CLK5620 can be easily configured using Lattice Semiconductor’s PACDesigner® software. Programming Interface Lattice Semiconductor’s ispDOWNLOAD cable can be used to program the ispClock5620 which is provided on the evaluation board. This cable plugs into a PC-compatible’s parallel port connector, and includes active buffer circuitry inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin 0.100” pitch header connector which plugs directly into a mating connector provided on the ispPAC-CLK5620-EV1 evaluation board. Power Supply Considerations The ispClock5620 operates with analog and digital core power supplies of 3.3V, while each output driver has a dedicated power supply pin which may be driven with supply voltage of 1.5V, 1.8V, 2.5V or 3.3V, depending on the logic standard which it has been configured to drive. To simplify evaluation work, the ispPAC-CLK5620-EV1 board was designed to operate from a single 4.5V-5.5V power supply, which may be brought in through either a pair of banana plugs (J2 and J3), or a standard 5mm power plug (J1 - center tip positive). The evaluation board provides two linear regulators to provide the appropriate operating voltages for the ispClock5620. One of these regulators provides a fixed 3.3V for the analog and core functions, while the other regulator is dipswitch-programmable to provide 1.5V, 1.8V, 2.5V and 3.3V to power the BANK8 and BANK9 output drivers. Input/Output Connections Connectors are provided for key functions and test points on this evaluation board, as shown In Figure 2. Power may be supplied in one of two ways; either through two color coded (RED = +, BLACK = -) banana jacks in the upper right corner of the board or through a 5mm (center pin +) DC power connector (J1), The JTAG programming cable is connected to a keyed header (J4) in the upper right corner of the board. Access to a subset of the ispClock5620’s I/O pins is available at J5, which is a 2x17 row of pads to which one may attach test probes or a ribbon-cable connector. At this point most of the device’s non-RF control pins (except those required for the JTAG programming interface) are accessible. SMA connectors are provided along the left and right edges of the board to support access to key high-speed I/O pins. Pairs of connectors are provided for the BANK8 and BANK9 outputs (J10-J13). Additional pairs of connectors are provided for REFA(+/-) clock reference inputs (J8, J9) and FBKA (+, -) external feedback inputs (J6, J7). On this evaluation board design the REFB(+/-) clock inputs are dedicated to supporting an on-board crystal oscillator. Because this board was designed to maintain high levels of signal integrity at the edge rates at which the ispClock5620 operates, it is strongly suggested that the user do not attempt to access any of the device’s highspeed I/O except through the provided SMA connectors and supporting impedance-controlled printed-circuit traces. 2 ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 Lattice Semiconductor Figure 2. I/O Connections, Controls and Indicators Controls and Indicators A 12-position dipswitch (S2) is provided on the evaluation board (Figure 2) for the purpose of setting device inputs and programming the VCCO power supply for the BANK8 and BANK9 outputs. The following table shows the options controlled by each switch: Table 1. User Configuration Functions Position Function (when ON) 1 PLL_BYPASS 2 PS0 3 PS1 4 GOE 5 SGATE 6 REFSEL 7 OEX 8 OEY 9 OSC DIS 10 11 BANK8 and BANK9 VCCO Programming 12 Each of the switch positions used to control logic inputs (positions 1-8) pulls its respective control signal HIGH when it is turned on. Each of these switch outputs is connected to the device through a 1KΩ resistor. This feature allows external CMOS logic control signals applied to the J5 header connector to over-ride the on-board switch settlings. 3 ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 Lattice Semiconductor Switch position 9 (OSC DIS) is used to control the evaluation board’s on-board clock oscillator. When this switch is set to the OFF position the on-board 100MHz oscillator is active and when it is the ON position it is disabled. Disabling the on-board oscillator is desirable when an external clock source is used as an input reference signal because doing so reduces the jitter measured at the board’s output. Note that if the on-board source is selected (REFSEL switch = ON) the on-board clock must not be disabled. Switch positions 10-12 are used to program the VCCO supply for output banks 8 and 9. When all of these switches are OFF, the default supply VCCO supply is 3.3V. The following table shows the switch configurations needed to develop standard supply voltages: Table 2. VCCO Programming Switch (S2) Configurations S2 Switch Position 10 11 12 VCCO OFF OFF OFF 3.3V ON OFF OFF 1.5V OFF ON OFF 1.8V OFF OFF ON 2.5V A reset switch (S1) is provided on the evaluation board which pulls the RESET input pin HIGH when it is depressed, re-initializing the ispClock5620. After changing profiles or reprogramming the ispClock5620 it is necessary to reset the device to obtain a stable clock output. Several LEDs are also provided on the evaluation board to indicate proper function and as aids to debugging. LED D2 (red) indicates that the on-board 3.3V supply is powered up. LED D3 (yellow) is connected to the ispClock5620’s TDO line, and will briefly flash when downloading, indicating that download data has made it to the device. Finally, when LED D4 (green) is lit, this indicates that the ispClock5620’s PLL is in a ‘locked’ state. Schematics The following three figures comprise the schematics for the ispPAC-CLK5620-EV1 evaluation board. Figure 3 shows the on-board power-conditioning circuitry, Figure 4 shows the high-speed interconnects and on-board oscillator circuitry, while Figure 5 shows all the logic control signals and indicators. Figure 3. On-Board Power Supplies U2 GND BANANA (BLACK) C1 100uF J2 C4 0.1uF TPS77733 GND +5V BANANA (RED) 3 IN 4 IN 1 5 OUT 6 OUT V33 C5 0.1uF C2 10 uF ENb D1 J3 2 J1 5mm Power Jack U3 S2.10 OFF OFF S2.11 OFF OFF S2.12 OFF ON VCCO 3.30 V 2.50 V OFF ON ON OFF OFF OFF 1.80 V 1.50 V TPS77701 1 ENb Output Voltage vs. Switch Settings OUT GND C6 0.1uF 3 IN 4 IN OUT FB 2 5 VCCO 6 R2 178K 1% 7 R1 100K 1% 4 S2.10 R3 300K 1% S2.11 R4 73.2K 1% S2.12 R5 31.6K 1% C7 0.1uF C3 10uF ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 Lattice Semiconductor Figure 4. Oscillator and High-Speed I/O V33 V33 C11 0.1u REFA- J8 39 J9 V33 VCCD REFA+ 47 71 VCCJ REFA+ 38 VCCD 74 C12 0.1u VCCA GNDA REFA- FB1 30 31 C9 0.1u VCCO V33 FBKA+ FB2 FBKAC11 0.1u 6 FBKVTT VCC 1 OSC1 (note 1) EN OUT 32 J6 33 J7 34 J5.24 4 41 5 42 OUT GND 3 40 REFVTT J5.25 S2.9 FBKA+ VCCO9 U1 FBKA- GNDO9 FBKVTT BANK9A BANK9B REFB- R282 100 C13 0.1u 70 69 BANK9A J10 68 BANK9B J11 VCCO REFVTT GNDO8 32 GNDD 33 GNDD 34 GNDD 35 GNDD 36 GNDD 37 GNDD BANK8A 66 C14 0.1u 65 BANK8A J12 64 BANK8B J13 GNDD GNDD FB4 63 93 46 GNDO6 GNDO5 GNDO7 62 58 GNDO4 54 22 GNDO2 GNDO1 GNDO3 18 6 Notes: 1. If OSC1 is LVCMOS type, omit R27,R28 If OSC1 is DPECL type, for external termination install R27,R28 2. Not populated 14 GNDO0 BANK8B 10 R272 100 67 ispClock5620 REFB+ VCCO8 Oscillator DISABLED when closed FB3 J5.3 J5.29 J5.15 J5.17 J5.19 J5.9 J5.11 J5.13 J5.5 J5.7 Figure 5. User Controls and Miscellaneous I/O U1 ispClock5620 V33 92 S2.1 PLL_BYPASS R16 1K S2.2 PS0 R17 1K S2.3 PS1 R18 1K S2.4 GOE R19 1K S2.5 SGATE R20 1K S2.6 REFSEL R21 1K S2.7 OEX R22 1K S2.8 OEY R23 1K 89 88 87 85 43 44 45 R7 1K R8 1K R9 1K R10 1K R11 1K R12 1K R13 1K R14 1K 72 V33 R26 680 V33 GOE Jx.1 VS SGATE REFSEL OEX TDO TDI 73 84 Jx.2 TDO Jx.3 TDI Jx.4 n/c OEY R6 1K 5 RESET R24 680 D2 POWER R25 680 D3 TDO TMS 91 82 LOCK TEST2 TEST1 Jx.6 TMS Jx.7 GND TCK 90 R15 2.2K C8 0.1u PS1 D4 LOCK V33 S1 PS0 Jx.5 plug 86 RESET PLL_BYPASS 83 Jx.8 TCK ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 Lattice Semiconductor PCB Artwork Figure 6. Silk Screen Figure 7. Component Side Copper (Layer 1) 6 ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 Lattice Semiconductor Figure 8. Ground Plane (Layer 2) Figure 9. Power Plane (Layer 3) 7 ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 Lattice Semiconductor Figure 10. Solder-side Copper (Layer 4) 8 ispClock5620 Evaluation Board: ispPAC-CLK5620-EV1 Lattice Semiconductor Component List Reference Designators Quantity Description 1 n/a ispPAC-CLK5620-EV1 Printed Wiring Board 1 C1 100µF 10V tantalum capacitor, Panasonic ECS-T1AD107R 2 C2, C3 10µF 10V tantalum capacitor, Panasonic ECS-T1AX106R 5 C4, C5, C6, C7, C8 0.1µF 16V capacitor SMD0805, Panasonic ECJ-2VB1C104K 6 C9, C10, C11, C12, C13, C14 0.1µF 16V capacitor SMD0603, Panasonic ECJ-1VB1C104K 1 D1 Schottky rectifier, International Rectifier MRBS130LTR 1 D2 Red LED SMD1206, LiteOn LTST-C150KRKT 1 D3 Yellow LED SMD1206, LiteOn LTST-C150KYKT 1 D4 Green LED SMD1206, LiteOn LTST-C150KGKT 4 FB1, FB2, FB3, FB4 SMD0603 Ferrite Bead, Steward MI0603J600R-00 1 J1 DC Power Connector, CUI PJ-102BH 1 J2 Banana Jack Red, SPC Technologies 845-R 1 J3 Banana Jack Black, SPC Technologies 845-B 1 J4 8-Position Single-Row Header, Molex 22-28-4084 1 J5 34-position Dual Row Header (Not Populated), Molex 10-88-1341 8 J6, J7, J8, J9, J10, J11, J12, J13 SMA Connector, Amphenol 901-144-8RFX 1 R1 100k 1% SMD0805 Resistor, Yageo 9C08052A1003FKHFT 1 R2 178k 1% SMD0805 Resistor, Yageo 9C08052A1783FKHFT 1 R3 300k 1% SMD0805 Resistor, Yageo 9C08052A3003FKHFT 1 R4 73.2k 1% SMD0805 Resistor, Yageo 9C08052A7322FKHFT 1 R5 31.6k 1% SMD0805 Resistor, Yageo 9C08052A3162FKHFT 18 R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 1K 5% SMD0805 Resistor, Yageo 9C08052A1001JLHFT R16, R17, R18, R19, R20, R21, R22, R23 3 R24, R25, R26 680Ω 5% SMD0805 Resistor, Yageo 9C08052A6800JLHFT 2 R271, R281 100Ω 1% SMD0603 Resistor, Panasonic ERJ-3EKF1000V 1 S1 Momentary Tactile Switch, Panasonic EVQPAD04M 1 S2 12-position dipswitch, CTS 206-12ST 1 U1 ispClock5620 (ispPAC-CLK5620V-01T100I) 1 U2 3.3V fixed regulator SOIC8, Texas Instruments TPS77733D 1 U3 Adjustable regulator SOIC8, Texas Instruments TPS77701D 2 1 X1 100MHz LVCMOS Oscillator, ECS-3953M-1000-B 4 n/a Rubber Feet, 3M SJ-5003 1. Install only for use with differential PECL oscillator – see note 2. 2. Lower jitter performance may be obtained by using NEL Frequency Controls type SD-A2920/100.00MHz Differential PECL oscillator. If this device is installed, R27, R28 must be populated. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-408-826-6002 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com 9