CAT9554 D

CAT9554, CAT9554A
8-bit I2C and SMBus I/O Port
with Interrupt
Description
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400 kHz I2C Bus Compatible (Note 1)
2.3 V to 5.5 V Operation
Low Stand−by Current
5 V Tolerant I/Os
8 I/O Pins that Default to Inputs at Power−up
High Drive Capability
Individual I/O Configuration
Polarity Inversion Register
Active Low Interrupt Output
Internal Power−on Reset
No Glitch on Power−up
Noise Filter on SDA/SCL Inputs
Cascadable up to 8 Devices
Industrial Temperature Range
16−lead SOIC and TSSOP, and 16−pad TQFN (4 x 4 mm) Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
TQFN−16
HV4 SUFFIX
CASE 510AE
SOIC−16
W SUFFIX
CASE 751BG
TSSOP−16
Y SUFFIX
CASE 948AN
PIN CONNECTIONS
A0
A1
A2
I/O0
I/O1
I/O2
I/O3
VSS
1
VCC
SDA
SCL
INT
I/O7
I/O6
I/O5
I/O4
SOIC (W), TSSOP (Y)
(Top View)
A1
A0
VCC
SDA
Features
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A2
I/O0
I/O1
I/O2
1
SCL
INT
I/O7
I/O6
I/O3
VSS
I/O4
I/O5
The CAT9554 and CAT9554A are CMOS devices that provide 8−bit
parallel input/output port expansion for I2C and SMBus compatible
applications. These I/O expanders provide a simple solution in
applications where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9554/9554A consist of an input port register, an output port
register, a configuration register, a polarity inversion register and an
I2C/SMBus−compatible serial interface.
Any of the eight I/Os can be configured as an input or output by
writing to the configuration register. The system master can invert the
CAT9554/9554A input data by writing to the active−high polarity
inversion register.
The CAT9554/9554A features an active low interrupt output which
indicates to the system master that an input state has changed.
The device’s extended addressing capability allows up to 8 devices
to share the same bus. The CAT9554A is identical to the CAT9554
except the fixed part of the I2C slave address is different. This allows
up to 16 of devices (eight CAT9554 and eight CAT9554A) to be
connected on the same bus.
TQFN 4 x 4 mm (HV4)
(Top View)
ORDERING INFORMATION
• White Goods (dishwashers, washing machines)
• Handheld Devices (cell phones, PDAs, digital cameras)
• Data Communications (routers, hubs and servers)
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
1. All I/Os are set to inputs at RESET.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 6
1
Publication Order Number:
CAT9554/D
CAT9554, CAT9554A
A0
I/O0
A1
I/O1
A2
I/O2
8−BIT
SCL
INPUT
FILTER
SDA
I2C/SMBUS
CONTROL
WRITE pulse
I/O3
INPUT/
OUTPUT
PORTS
I/O4
I/O5
READ pulse
I/O6
I/O7
POWER−ON
RESET
VCC
VSS
VCC
INT
LP FILTER
Note: All I/Os are set to inputs at RESET.
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
SOIC / TSSOP
TQFN
Pin Name
1
15
A0
Address Input 0
Function
2
16
A1
Address Input 1
3
1
A2
Address Input 2
4−7
2−5
I/O0−3
8
6
VSS
9−12
7−10
I/O4−7
13
11
INT
Interrupt Output (open drain)
14
12
SCL
Serial Clock
15
13
SDA
Serial Data
16
14
VCC
Power Supply
Input/Output Port 0 to Input/Output Port 3
Ground
Input/Output Port 4 to Input/Output Port 7
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
VCC with Respect to Ground
−0.5 to +6.5
V
Voltage on Any Pin with Respect to Ground
−0.5 to +5.5
V
DC Current on I/O0 to I/O7
±50
mA
DC Input Current
±20
mA
VCC Supply Current
85
mA
VSS Supply Current
100
mA
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Junction Temperature
+150
°C
Storage Temperature
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
VZAP (Note 2)
ILTH (Notes 2, 3)
Parameter
Reference Test Method
Min
Units
ESD Susceptibility
JEDEC Standard JESD 22
2000
Volts
Latch−up
JEDEC Standard 17
100
mA
2. This parameter is tested initially and after a design or process change that affects the parameter.
3. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC +1 V.
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CAT9554, CAT9554A
Table 4. D.C. OPERATING CHARACTERISTICS (VCC = 2.3 to 5.5 V; TA = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.3
−
5.5
V
SUPPLIES
VCC
Supply voltage
ICC
Supply current
Operating mode; VCC = 5.5 V;
no load; fSCL = 100 kHz
−
104
175
mA
Istbl
Standby current
Standby mode; VCC = 5.5 V; no load;
VI = VSS; fSCL = 0 kHz; I/O = inputs
−
550
700
mA
Istbh
Standby current
Standby mode; VCC = 5.5 V; no load;
VI = VCC; fSCL = 0 kHz; I/O = inputs
−
0.25
1
mA
Power−on reset voltage
No load; VI = VCC or VSS
−
1.5
1.65
V
VPOR
SCL, SDA, INT
VIL (Note 4)
Low level input voltage
−0.5
−
0.3 x VCC
V
VIH (Note 4)
High level input voltage
0.7 x VCC
−
5.5
V
IOL
Low level output current
VOL = 0.4 V
3
−
−
mA
Leakage current
VI = VCC or VSS
−1
−
+1
mA
CI (Note 5)
IL
Input capacitance
VI = VSS
−
−
6
pF
CO (Note 5)
Output capacitance
VO = VSS
−
−
8
pF
A0, A1, A2
VIL (Note 4)
Low level input voltage
−0.5
−
0.8
V
VIH (Note 4)
High level input voltage
2.0
−
5.5
V
ILI
Input leakage current
−1
−
1
mA
VIL
Low level input voltage
−0.5
−
0.8
V
VIH
High level input voltage
2.0
−
5.5
V
IOL
Low level output current
VOL = 0.5 V; VCC = 2.3 V (Note 6)
8
10
−
mA
VOL = 0.7 V; VCC = 2.3 V (Note 6)
10
13
−
mA
VOL = 0.5 V; VCC = 4.5 V (Note 6)
8
17
−
mA
VOL = 0.7 V; VCC = 4.5 V (Note 6)
10
24
−
mA
VOL = 0.5 V; VCC = 3.0 V (Note 6)
8
14
−
mA
VOL = 0.7 V; VCC = 3.0 V (Note 6)
10
19
−
mA
IOH = −8 mA; VCC = 2.3 V (Note 7)
1.8
−
−
V
IOH = −10 mA; VCC = 2.3 V (Note 7)
1.7
−
−
V
IOH = −8 mA; VCC = 3.0 V (Note 7)
2.6
−
−
V
IOH = −10 mA; VCC = 3.0 V (Note 7)
2.5
−
−
V
IOH = −8 mA; VCC = 4.75 V (Note 7)
4.1
−
−
V
IOH = −10 mA; VCC = 4.75 V (Note 7)
4.0
−
−
V
I/Os
VOH
4.
5.
6.
7.
High level output
voltage
IIH
Input leakage current
VCC = 3.6 V; VI = VCC
−
−
1
mA
IIL
Input leakage current
VCC = 5.5 V; VI = VSS
−
−
−100
mA
CI (Note 5)
Input capacitance
−
−
5
pF
CO (Note 5)
Output capacitance
−
−
8
pF
VIL min and VIH max are reference values only and are not tested.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
The total current sunk by all I/Os must be limited to 100 mA and each I/O limited to 25 mA maximum.
The total current sourced by all I/Os must be limited to 85 mA.
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CAT9554, CAT9554A
Table 5. A.C. CHARACTERISTICS (VCC = 2.3 V to 5.5 V; TA = −40°C to +85°C, unless otherwise specified.) (Note 8)
Standard I2C
FSCL
tHD:STA
Min
Parameter
Symbol
Clock Frequency
Max
Fast I2C
Min
100
START Condition Hold Time
Max
Units
400
kHz
4
0.6
ms
tLOW
Low Period of SCL Clock
4.7
1.3
ms
tHIGH
High Period of SCL Clock
4
0.6
ms
4.7
0.6
ms
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
ms
tSU:DAT
Data In Setup Time
250
100
ns
tR (Note 9)
SDA and SCL Rise Time
tF (Note 9)
SDA and SCL Fall Time
tSU:STO
tBUF (Note 9)
300
STOP Condition Setup Time
Bus Free Time Between STOP and START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
Ti (Note 9)
1000
Symbol
ns
300
ns
4
0.6
ms
4.7
1.3
ms
3.5
100
Noise Pulse Filtered at SCL and SDA Inputs
300
0.9
50
100
Parameter
Min
ms
ns
100
ns
Max
Units
200
ns
PORT TIMING
tPV
Output Data Valid
tPS
Input Data Setup Time
100
ns
tPH
Input Data Hold Time
1
ms
INTERRUPT TIMING
tIV
Interrupt Valid
4
ms
tIR
Interrupt Reset
4
ms
8. Test conditions according to “AC Test Conditions” table.
9. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall time
≤ 10 ns
CMOS Input Voltages
0.2 VCC to 0.8 VCC
CMOS Input Reference Voltages
0.3 VCC to 0.7 VCC
TTL Input Voltages
0.4 V to 2.4 V
TTL Input Reference Voltages
0.8 V, 2.0 V
Output Reference Voltages
0.5 VCC
Output Load: SDA, INT
Current Source IOL = 3 mA; CL = 100 pF
Output Load: I/Os
Current Source: IOL/IOH = 10 mA; CL = 50 pF
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CAT9554, CAT9554A
tF
tR
tHIGH
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:STO
tSU:DAT
SDA IN
tBUF
tDH
tAA
SDA OUT
Figure 2. I2C Serial Interface Timing
Pin Description
A0, A1, A2: Device Address Inputs
These inputs are used for extended addressing capability.
The A0, A1, A2 pins should be hardwired to VCC or VSS.
When hardwired, up to eight CAT9554/9554As may be
addressed on a single bus system. The levels on these inputs
are compared with corresponding bits, A2, A1, A0, from the
slave address byte.
SCL: Serial Clock
The serial clock input clocks all data transferred into or out
of the device. The SCL line requires a pull−up resistor if it
is driven by an open drain output.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs. A pull−up resistor must be connected
from SDA line to VCC. The value of the pull−up resistor, RP,
can be calculated based on minimum and maximum values
from Figure 3 and Figure 4 (see Note).
I/O0 to I/O7: Input / Output Ports
Any of these pins may be configured as input or output.
The simplified schematic of I/O0 to I/O7 is shown in
Figure 5. When an I/O is configured as an input, the Q1 and
Q2 output transistors are off creating a high impedance input
with a weak pull−up resistor (typical 100 kW). If the I/O pin
is configured as an output, the push−pull output stage is
enabled. Care should be taken if an external voltage is
applied to an I/O pin configured as an output due to the low
impedance paths that exist between the pin and either VCC
or VSS.
8
2.5
IOL = 3 mA @ VOLmax
2.0
6
RPmax (KW)
RPmin (KW)
Fast Mode I2C Bus /
tr max − 300 ns
7
1.5
1.0
5
4
3
2
0.5
1
0
NOTE:
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
5.2
0
5.6
0
50
100
150
200
250
300
350
VCC (V)
CBUS (pF)
Figure 3. Minimum RP Value vs.
Supply Voltage
Figure 4. Maximum RP Value vs.
Bus Capacitance
400
According to the Fast Mode I2C bus specification, for bus capacitance up to 200 pF, the pull up device can be a resistor. For bus
loads between 200 pF and 400 pF, the pull−up device can be a current source (Imax = 3 mA) or a switched resistor circuit.
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CAT9554, CAT9554A
INT: Interrupt Output
state or the input port register is read. Changing an I/O from
an output to an input may cause a false interrupt if the state
of the pin does not match the contents of the input port
register.
The open−drain interrupt output is activated when one of
the port pins configured as an input changes state (differs
from the corresponding input port register bit state). The
interrupt is deactivated when the input returns to its previous
Data from
Shift Register
Data from
Shift Register
Output Port
Register Data
Configuration
Register
VCC
Q
D
FF
Write
Configuration
Pulse
CK
Q1
Q
100 kW
Q
D
FF
Write Pulse
CK
I/O0 to I/O7
Q
Output Port
Register
Q2
Input Port
Register
Q
D
LATCH
Read Pulse
Data from
Shift Register
CK
Q
D
Q
FF
Write
Polarity
Register
CK
Q
Polarity
Inversion Register
Figure 5. Simplified Schematic of I/O0 to I/O7
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VSS
Input Port
Register Data
To INT
Polarity
Register Data
CAT9554, CAT9554A
Functional Description
The CAT9554 and CAT9554A general purpose input/
output (GPIO) peripherals provide up to eight I/O ports,
controlled through an I2C compatible serial interface.
The CAT9554/9554A support the I2C Bus data
transmission protocol. This I2C Bus protocol defines any
device that sends data to the bus to be a transmitter and any
device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
The CAT9554/9554A operate as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls which
mode is activated.
START and STOP Conditions
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT9554/9554A monitors the
SDA and SCL lines and will not respond until this condition
is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9554/9554A for
a read or write operation. The four most significant bits of
the slave address are fixed as binary 0100 for the CAT9554
(Figure 7) and as 0111 for the CAT9554A (Figure 8). The
CAT9554/9554A uses the next three bits as address bits.
The address bits A2, A1 and A0 are used to select which
device is accessed from maximum eight devices on the same
bus. These bits must compare to their hardwired input pins.
The 8th bit following the 7−bit slave address is the R/W bit
that specifies whether a read or write operation is to be
performed. When this bit is set to “1”, a read operation is
initiated, and when set to “0”, a write operation is selected.
Following the START condition and the slave address
byte, the CAT9554/9554A monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT9554/
9554A then performs a read or a write operation depending
on the state of the R/W bit.
I2C Bus Protocol
The features of the I2C bus protocol are defined as follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition
(Figure 6).
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 6. START/STOP Condition
SLAVE ADDRESS
0
1
0
FIXED
0
A2
SLAVE ADDRESS
A1
A0
R/W
0
PROGRAMMABLE
HARDWARE
SELECTABLE
1
1
FIXED
Figure 7. CAT9554 Slave Address
1
A2
A1
A0
R/W
PROGRAMMABLE
HARDWARE
SELECTABLE
Figure 8. CAT9554A Slave Address
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CAT9554, CAT9554A
Acknowledge
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine which
register will be written or read.
The input port register is a read only port. It reflects the
incoming logic levels of the I/O pins, regardless of whether
the pin is defined as an input or an output by the
configuration register. Writes to the input port register are
ignored.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data. The SDA line
remains stable LOW during the HIGH period of the
acknowledge related clock pulse (Figure 6).
The CAT9554/9554A responds with an acknowledge
after receiving a START condition and its slave address. If
the device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT9554/9554A begins a READ mode it
transmits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this
acknowledge, the CAT9554/9554A will continue to
transmit data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a STOP
condition. The master must then issue a STOP condition to
return the CAT9554/9554A to the standby power mode and
place the device in a known state.
Table 8. REGISTER 0 – INPUT PORT REGISTER
bit
I7
I6
I5
I4
I3
I2
I1
I0
default
1
1
1
1
1
1
1
1
Table 9. REGISTER 1 – OUTPUT PORT REGISTER
bit
O7
O6
O5
O4
O3
O2
O1
O0
default
1
1
1
1
1
1
1
1
Table 10. REGISTER 2 –
POLARITY INVERSION REGISTER
Registers and Bus Transactions
The CAT9554/9554A consist of an input port register, an
output port register, a polarity inversion register and a
configuration register. Table 7 shows the register address
table. Tables 8 to 11 list Register 0 through Register 3
information.
bit
N7
N6
N5
N4
N3
N2
N1
N0
default
0
0
0
0
0
0
0
0
Table 11. REGISTER 3 – CONFIGURATION REGISTER
bit
C7
C6
C5
C4
C3
C2
C1
C0
default
1
1
1
1
1
1
1
1
Table 7. REGISTER COMMAND BYTE
Command
(hex)
Protocol
Function
0x00
Read byte
Input port register
0x01
Read/write byte
Output port register
0x02
Read/write byte
Polarity inversion register
0x03
Read/write byte
Configuration register
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP
ACK DELAY
Figure 9. Acknowledge Timing
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CAT9554, CAT9554A
corresponding port pin as an input with a high impedance
output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At
power−up, the I/Os are configured as inputs with a weak
pull−up resistor to VCC.
Data is transmitted to the CAT9554/9554A registers using
the write mode shown in Figure 10 and Figure 11.
The CAT9554/9554A registers are read according to the
timing diagrams shown in Figure 12 and Figure 13. Once a
command byte has been sent, the register which was
addressed will continue to be accessed by reads until a new
command byte will be sent.
The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Bit values in this register have no effect on I/O pins
defined as inputs. Reads from the output port register reflect
the value that is in the flip−flop controlling the output, not
the actual I/O pin value.
The polarity inversion register allows the user to invert the
polarity of the input port register data. If a bit in this register
is set (“1”) the corresponding input port data is inverted. If
a bit in the polarity inversion register is cleared (“0”), the
original input port polarity is retained.
The configuration register sets the directions of the ports.
Set the bit in the configuration register to enable the
SCL
1
2
3
4
5
6
7
S
0
1
9
R/W
slave address
SDA
8
0
0 A2 A1 A0 0
start condition
acknowledge
from slave
command byte
A
0
0
0
0
0
0
data to port
0
A
1
DATA 1
acknowledge from slave
A P
acknowledge from slave
WRITE TO
PORT
stop
condition
DATA 1 VALID
DATA OUT FROM PORT
tpv
Figure 10. Write to Output Port Register
SCL
1
2
3
4
5
6
slave address
SDA
S
0
1
7
8
9
R/W
0
0 A2 A1 A0 0
start condition
acknowledge
from slave
command byte
A
0
0
0
0
0
0
data to register
1 1/0
acknowledge from slave
A
DATA 1
acknowledge from slave
WRITE TO
REGISTER
Figure 11. Write to Configuration or Polarity Inversion Register
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A P
stop
condition
CAT9554, CAT9554A
Power−On Reset Operation
When the power supply is applied to VCC pin, an internal
power−on reset pulse holds the CAT9554/9554A in a reset
state until VCC reaches VPOR level. At this point, the reset
slave address
S 0
1
0
condition is released and the internal state machine and the
CAT9554/9554A registers are initialized to their default
state.
R/W
0 A2 A1 A0 0
slave address
A
COMMAND BYTE
A S
0
acknowledge from slave
acknowledge from slave
1
0
R/W
acknowledge from master
data from register
DATA
0 A2 A1 A0 1 A
acknowledge from slave
A
first byte
At this moment master−transmitter becomes
master−receiver and slave−receiver
becomes slave−transmitter
no acknowledge
from master
data from register
DATA
NA P
last byte
Figure 12. Read from Register
SCL
1
2
3
4
5
6
slave address
SDA
S
0
1
7
8
9
data from port
R/W
0
0 A2 A1 A0 1
start condition
acknowledge
from slave
DATA 1
A
data from port
A
acknowledge
from master
DATA 4
no acknowledge
from master
READ FROM
PORT
DATA INTO
PORT
DATA 1
DATA 2
DATA 3
tPH
tPS
INT
tIV
tIR
Figure 13. Read Input Port Register
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DATA 4
NA P
stop
condition
CAT9554, CAT9554A
PACKAGE DIMENSIONS
SOIC−16, 150 mils
CASE 751BG−01
ISSUE O
SYMBOL
E1
E
MIN
NOM
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
D
9.80
9.90
10.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
0.25
1.27 BSC
e
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
PIN#1 IDENTIFICATION
TOP VIEW
D
h
q
A
e
b
A1
c
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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11
CAT9554, CAT9554A
PACKAGE DIMENSIONS
TQFN16, 4x4
CASE 510AE−01
ISSUE A
A
D
DETAIL A
E2
E
PIN#1 ID
PIN#1 INDEX AREA
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
BOTTOM VIEW
e
b
0.20 REF
b
0.25
0.30
0.35
D
3.90
4.00
4.10
D2
2.00
−−−
2.25
E
3.90
4.00
4.10
E2
2.00
−−−
2.25
e
L
D2
A1
L
DETAIL A
0.65 BSC
0.45
−−−
A
0.65
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-220.
A1
A3
FRONT VIEW
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12
CAT9554, CAT9554A
PACKAGE DIMENSIONS
TSSOP16, 4.4x5
CASE 948AN−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.10
A1
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
c
0.13
0.20
D
4.90
5.10
E
6.30
6.50
E1
4.30
4.50
e
0.65 BSC
L
1.00 REF
L1
0.45
0.75
θ
0º
8º
e
PIN#1
IDENTIFICATION
TOP VIEW
D
A2
A
c
θ1
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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13
L
CAT9554, CAT9554A
Example of Ordering Information (Note 12)
Prefix
Device #
Suffix
CAT
9554
W
Company ID
(Optional)
Product Number
9554
9554A
Package
W: SOIC
Y: TSSOP
HV4: TQFN
−G
T2
Lead Finish
G: NiPdAu
Blank: Matte−Tin
Tape & Reel (Note 14)
T: Tape & Reel
2: 2,000 / Reel
I
Temperature Range
I = Industrial (−40°C to +85°C)
Table 12. ORDERING INFORMATION
Part Number
CAT9554WI−G
CAT9554WI−GT2
Package
Lead Finish
SOIC
NiPdAu
SOIC
NiPdAu
CAT9554YI−G
TSSOP
NiPdAu
CAT9554YI−GT2
TSSOP
NiPdAu
CAT9554HV4I−G
TQFN
NiPdAu
CAT9554HV4I−GT2
TQFN
NiPdAu
CAT9554AWI−G
SOIC
NiPdAu
CAT9554AWI−GT2
SOIC
NiPdAu
CAT9554AYI−G
TSSOP
NiPdAu
CAT9554AYI−GT2
TSSOP
NiPdAu
CAT9554AHV4I−G
TQFN
NiPdAu
CAT9554AHV4I−GT2
TQFN
NiPdAu
10. All packages are RoHS−compliant (Lead−free, Halogen−free).
11. The standard lead finish is NiPdAu.
12. The device used in the above example is a CAT9554WI−GT2 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel).
13. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
14. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
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14
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CAT9554/D
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