CAT5261 D

CAT5261
Dual Digital
Potentiometer (POT)
with 256 Taps
and SPI Interface
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Description
The CAT5261 is two digital POTs integrated with control logic and
8 bytes of NVRAM memory. Each digital POT consists of a series of
resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 8-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 8-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the potentiometers
is automatically loaded into its respective wiper control register.
The CAT5261 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications. It is available in the
−40C to 85C industrial operating temperature range and offered in a
24-lead SOIC and TSSOP package.
Features
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Two Linear-taper Digital Potentiometers
256 Resistor Taps per Potentiometer
End to End Resistance 50 kW or 100 kW
Potentiometer Control and Memory Access via SPI Interface
Low Wiper Resistance, Typically 100 W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and 24-lead TSSOP
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
 Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 8
1
TSSOP−24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
SO
HOLD
1
A0
SCK
NC
NC
NC
NC
NC
NC
NC
VCC
CAT5261
NC
GND
RL0
RW1
RH0
RH1
RW0
RL1
CS
A1
WP
SI
SOIC−24 (W)
TSSOP−24 (Y)
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Publication Order Number:
CAT5261/D
CAT5261
MARKING DIAGRAMS
(SOIC−24)
(TSSOP−24)
L3B
CAT5261WT
−RRYMXXXX
RLB
CAT5261YI
3YMXXX
R = Resistance
1 = 2.5 KW
2 = 10 KW
4 = 50 KW
5 = 100 KW
L = Assembly Location
B = Product Revision (Fixed as “B”)
CAT5261Y = Device Code
I = Temperature Range (I = Industrial)
3 = Lead Finish − Matte-Tin
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
L = Assembly Location
3 = Lead Finish − Matte-Tin
B = Product Revision (Fixed as “B”)
CAT = Fixed as “CAT”
5261W = Device Code
T = Temperature Range (I = Industrial)
− = Dash
RR = Resistance
25 = 2.5 KW
10 = 10 KW
50 = 50 KW
00 = 100 KW
Y = Production Year (Last Digit)
M = Production Month (1-9, O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
RH0
CS
SCK
SI
SO
RH1
WIPER
CONTROL
REGISTERS
SPI BUS
INTERFACE
RW0
RW1
WP
A0
A1
HOLD
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0
Figure 1. Functional Diagram
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RL1
CAT5261
PIN DESCRIPTIONS
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5261.
RH, RL: Resistor End Points
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
RW: Wiper
The RW pins are equivalent to the wiper terminal of a
mechanical potentiometer.
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT5261 and
CS high disables the CAT5261. CS high takes the SO output
pin to high impedance and forces the devices into a Standby
mode (unless an internal write operation is underway). The
CAT5261 draws ZERO current in the Standby mode. A high
to low transition on CS is required prior to any sequence
being initiated. A low to high transition on CS after a valid
write sequence is what initiates an internal write cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will allow
normal read/write operations when held high. When WP is
tied low, all non-volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT5261 while in the middle of a serial sequence without
having to retransmit entire sequence at a later time. To pause,
HOLD must be brought low while SCK is low. The SO pin
is in a high impedance state during the time the part is
paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to VCC or
tied to VCC through a resistor.
WP: Write Protect Input
The WP pin when tied low prevents non-volatile writes to
the device (change of wiper control register is allowed) and
when tied high or left floating normal read/write operations
are allowed.
Table 1. PIN DESCRIPTIONS
Pin #
Name
Function
1
SO
Serial Data Output
2
A0
Device Address, LSB
3
NC
No Connect
4
NC
No Connect
5
NC
No Connect
6
NC
No Connect
7
VCC
Supply Voltage
8
RL0
Low Reference Terminal for
Potentiometer 0
9
RH0
High Reference Terminal for
Potentiometer 0
10
RW0
Wiper Terminal for Potentiometer 0
11
CS
Chip Select
12
WP
Write Protection
13
SI
Serial Input
14
A1
Device Address
15
RL1
Low Reference Terminal for
Potentiometer 1
16
RH1
High Reference Terminal for
Potentiometer 1
17
RW1
Wiper Terminal for Potentiometer 1
18
GND
Ground
19
NC
No Connect
20
NC
No Connect
21
NC
No Connect
22
NC
No Connect
23
SCK
24
HOLD
Bus Serial Clock
Hold
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5261. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5261. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5261. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
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CAT5261
SERIAL BUS PROTOCOL
8-bit instruction register. The instruction set and the
operation codes are detailed in the Instruction Set Table 13
on page 9.
The CAT5261 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface (SPI)
helps the CAT5261 to interface directly with many of
today’s popular microcontrollers. The CAT5261 contains an
DEVICE OPERATION
The CAT5261 is two resistor arrays integrated with an SPI
serial interface logic, two 8-bit wiper control registers and
eight 8-bit, non-volatile memory data registers. Each
resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL). RH and RL are symmetrical and
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
terminals (RW) by a After the device is selected with CS
going low the first byte will be received. The part is accessed
via the SI pin, with data being clocked in on the rising edge
of SCK. The first byte contains one of the six op-codes that
define the operation to be performed.
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time and
is determined by the value of the wiper control register. Data
can be read or written to the wiper control registers or the
non-volatile memory data registers via the SPI bus.
Additional instructions allows data to be transferred
between the wiper control registers and each respective
potentiometer’s non-volatile data registers. Also, the device
can be instructed to operate in an “increment/decrement”
mode.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Temperature Under Bias
−55 to +125
C
Storage Temperature
−65 to +150
C
−2.0 to +VCC + 2.0
V
−0.2 to +7.0
V
Package Power Dissipation Capability (TA = 25C)
1.0
W
Lead Soldering Temperature (10 s)
300
C
Wiper Current
6
mA
Voltage on Any Pin with Respect to Ground (Note 1)
VCC with Respect to Ground
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters
Ratings
Units
VCC
+2.5 to +6.0
V
Industrial Temperature
−40 to +85
C
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CAT5261
Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
RPOT
Potentiometer Resistance (−00)
100
kW
RPOT
Potentiometer Resistance (−50)
50
kW
Potentiometer Resistance Tolerance
RPOT Matching
Power Rating
25C, each pot
20
%
1
%
50
mW
3
mA
IW
Wiper Current
RW
Wiper Resistance
IW = 3 mA @ VCC = 3 V
200
300
W
RW
Wiper Resistance
IW = 3 mA @ VCC = 5 V
100
150
W
VTERM
VN
Voltage on any RH or RL Pin
0
Noise
VCC
(Note 3)
V
nVHz
Resolution
0.4
%
Absolute Linearity (Note 4)
Rw(n)(actual)−R(n)(expected)
(Note 7)
1
LSB
(Note 6)
Relative Linearity (Note 5)
Rw(n+1)−[Rw(n)+LSB]
(Note 7)
0.2
LSB
(Note 6)
TCRPOT
Temperature Coefficient of RPOT
(Note 3)
TCRATIO
Ratiometric Temp. Coefficient
(Note 3)
CH/CL/CW
Potentiometer Capacitances
(Note 3)
10/10/25
pF
RPOT = 50 kW (Note 3)
0.4
MHz
fc
Frequency Response
ppm/C
300
20
ppm/C
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = RTOT / 255 or (RH − RL) / 255, single pot
7. n = 0, 1, 2, ..., 255
Table 5. D.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICC1
Power Supply Current
fSCL = 400 kHz, SDA = Open
VCC = 6 V, Inputs = GNDs
1
mA
ICC2
Power Supply Current
fSCK = 400 kHz, SDA Open
5
mA
VIN = GND or VCC, SDA = Open
1
mA
VIN = GND to VCC
10
mA
VOUT = GND to VCC
10
mA
Non-volatile WRITE
VCC = 6 V, Input = GND
ISB
Standby Current (VCC = 5 V)
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
−1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
0.4
V
VOL1
Output Low Voltage (VCC = 3 V)
VOH1
Output High Voltage
IOL = 3 mA
IOH = −1.6 mA
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VCC – 0.8
V
CAT5261
Table 6. PIN CAPACITANCE (Note 8) (TA = 25C, f = 1.0 MHz, VCC = 5 V, unless otherwise specified.)
Test
Symbol
COUT (Note 8)
CIN (Note 8)
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD, A0, A1)
Conditions
Max
Units
VOUT = 0 V
8
pF
VIN = 0 V
6
pF
Max
Units
Table 7. A.C. CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tWH
SCK High Time
125
ns
tWL
SCK Low Time
125
ns
fSCK
Clock Frequency
DC
3
MHz
HOLD to Output Low Z
50
ns
tRI (Note 8)
Input Rise Time
2
ms
tFI (Note 8)
Input Fall Time
2
tLZ
tHD
HOLD Setup Time
tCD
HOLD Hold Time
tV
CL = 50 pF
ns
100
ns
Output Valid from Clock Low
tHO
Output Hold Time
tDIS
Output Disable Time
ms
100
200
0
ns
ns
250
ns
100
ns
tHZ
HOLD to Output High Z
tCS
CS High Time
2
ns
tCSS
CS Setup Time
250
ns
tCSH
CS Hold Time
250
ns
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER UP TIMING (Notes 9, 10)
Parameter
Symbol
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Min
Max
Units
Wiper Response Time After Power Supply Stable
5
10
ms
Wiper Response Time After Instruction Issued
5
10
ms
Max
Units
5
ms
Table 9. WIPER TIMING
Symbol
tWRPO
tWRL
Parameter
Table 10. WRITE CYCLE LIMITS
Symbol
tWR
Parameter
Write Cycle Time
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CAT5261
Table 11. RELIABILITY CHARACTERISTICS
Symbol
NEND (Note 11)
Parameter
Reference Test Method
Min
Max
Units
Endurance
MIL−STD−883, Test Method 1033
1,000,000
Cycles/Byte
TDR (Note 11)
Data Retention
MIL−STD−883, Test Method 1008
100
Years
VZAP (Note 11)
ESD Susceptibility
MIL−STD−883, Test Method 3015
2000
V
ILTH (Note 11)
Latch-up
JEDEC Standard 17
100
mA
9. This parameter is tested initially and after a design or process change that affects the parameter.
10. tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
11. This parameter is tested initially and after a design or process change that affects the parameter.
tCS
VIH
CS
VIL
tCSH
tCSS
SCK
VIH
tWH
VIL
SI
tH
tSU
VIH
tWL
VALID IN
VIL
tRI
tFI
tV
VOH
SO
tHO
tDIS
HI−Z
HI−Z
VOL
Figure 2. Synchronous Data Timing
NOTE:
Dashed Line = mode (1, 1)
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
HIGH IMPEDANCE
tLZ
Figure 3. HOLD Timing
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CAT5261
INSTRUCTION AND REGISTER DESCRIPTION
Device Type/Address Byte
Instruction Byte
The first byte sent to the CAT5261 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5261 are fixed at
0101[B] (refer to Figure 4).
The two least significant bits in the slave address byte, A1
− A0, are the internal slave address and must match the
physical device address which is defined by the state of the
A1 − A0 input pins for the CAT5261 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent by the
master executes the instruction. The A1 − A0 inputs can be
actively driven by CMOS input signals or tied to VCC or
VSS. The remaining two bits in the device address byte must
be set to 0.
The next byte sent to the CAT5261 contains the
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I3 − I0.
The R1 and R0 bits point to one of the four data registers of
each associated potentiometer. The least two significant bits
point to one of two Wiper Control Registers. The format is
shown in Figure 5.
Table 12. DATA REGISTER SELECTION
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
Device Type
Identifier
ID3
0
Slave Address
ID2
ID1
1
0
ID0
A3
A2
A1
A0
1
(MSB)
(LSB)
Figure 4. Identification Byte Format
Instruction
Opcode
I3
I2
Data Register
Selection
I1
I0
R1
R0
(MSB)
WCR/Pot Selection
P1
P0
(LSB)
Figure 5. Instruction Byte Format
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
Data Registers (DR)
The CAT5261 contains two 8-bit Wiper Control
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 256 switches
along its resistor array. The contents of the WCR can be
altered in four ways: it may be written by the host via Write
Wiper Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction; it can be
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register zero
(DR0) upon power-up.
The Wiper Control Register is a volatile register that loses
its contents when the CAT5261 is powered-down. Although
the register is automatically loaded with the value in DR0
upon power-up, this may be different from the value present
at power-down.
Each potentiometer has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Control Register. Any
data changes in one of the Data Registers is a non-volatile
operation and will take a maximum of 5 ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be used
as standard memory locations for system parameters or user
preference data.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS input goes HIGH after a
write sequence is received. The status of the internal write
cycle can be monitored by issuing a Read Status command
to read the Write in Process (WIP) bit.
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CAT5261
Instructions
Five of the ten instructions are three bytes in length. These
instructions are:
 Read Wiper Control Register – read the current
wiper position of the selected potentiometer in the
WCR
 Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer



Read Data Register – read the contents of the
selected Data Register
Write Data Register – write a new value to the
selected Data Register
Read Status – Read the status of the WIP bit which
when set to “1” signifies a write cycle is in progress.
Table 13. INSTRUCTION SET
Instruction Set
I3
I2
I1
I0
R1
R0
WCR1/
P1
WCR0/
P0
Read Wiper Control
Register
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Control Register
pointed to by P1−P0
Write Wiper Control
Register
1
0
1
0
0
0
1/0
1/0
Write new value to the Wiper Control Register
pointed to by P1−P0
Read Data Register
1
0
1
1
1/0
1/0
1/0
1/0
Read the contents of the Data Register pointed
to by P1−P0 and R1−R0
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
Write new value to the Data Register pointed to
by P1−P0 and R1−R0
XFR Data Register to
Wiper Control
Register
1
1
0
1
1/0
1/0
1/0
1/0
Transfer the contents of the Data Register
pointed to by P1−P0 and R1−R0 to its
associated Wiper Control Register
XFR Wiper Control
Register to Data
Register
1
1
1
0
1/0
1/0
1/0
1/0
Transfer the contents of the Wiper Control
Register pointed to by P1−P0 to the Data
Register pointed to by R1−R0
Global XFR Data
Registers to Wiper
Control Registers
0
0
0
1
1/0
1/0
0
0
Transfer the contents of the Data Registers
pointed to by R1−R0 of all four pots to their
respective Wiper Control Registers
Global XFR Wiper
Control Registers to
Data Register
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1−R0 of all four pots
Increment/Decrement
Wiper Control Register
0
0
1
0
0
0
1/0
1/0
Enable Increment/decrement of the Control
Latch pointed to by P1−P0
Read Status (WIP bit)
0
1
0
1
0
0
0
1
Instruction
NOTE:
Operation
Read WIP bit to check internal write cycle status
1/0 = data is one or zero
The basic sequence of the three byte instructions is
illustrated in Figure 7. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by tWRL.
A transfer from the WCR (current wiper position), to a Data
Register is a write to non-volatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the potentiometers and one of its associated
registers; or the transfer can occur between both
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 6. These instructions
transfer data between the host/processor and the CAT5261;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:




XFR Data Register to Wiper Control Register −
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register −
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
Global XFR Data Register to Wiper Control
Register − This transfers the contents of all specified
Data Registers to the associated Wiper Control
Registers.
Global XFR Wiper Counter Register to Data
Register − This transfers the contents of all Wiper
Control Registers to the specified associated Data
Registers.
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CAT5261
Increment/Decrement Command
the host. For each SCK clock pulse (tHIGH) while SI is
HIGH, the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCK clock
pulse while SI is LOW, the selected wiper will move one
resistor segment towards the RL terminal.
See Instructions format for more detail.
The final command is Increment/Decrement (Figures 8
and 9). The Increment/Decrement command is different
from the other commands. Once the command is issued the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0 A3 A2 A1 A0
Internal
Address
Device ID
I3
I2
I1
I0 R1 R0 P1 P0
Instruction
Opcode
Register Pot/WCR
Address Address
Figure 6. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0 A3 A2 A1 A0
Internal
Address
Device ID
I3
I2
I1
I0 R1 R0 P1 P0 D7 D6 D5 D4 D3 D2 D1 D0
Instruction
Opcode
Data Pot/WCR
Register Address
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 7. Three-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0 A3 A2 A1 A0 I3
Device ID
Internal
Address
I2
I1
I0
Instruction
Opcode
R1 R0 P1 P0
I
N
Data Pot/WCR C
Register Address 1
Address
I
N
C
2
Figure 8. Increment/Decrement Instruction Sequence
INC/DEC
Command
Issued
tWRL
SCK
SI
RW
Voltage Out
Figure 9. Increment/Decrement Timing Limits
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10
I
N
C
n
D
E
C
1
D
E
C
n
CAT5261
INSTRUCTION FORMAT
Table 14. READ WIPER CONTROL REGISTER (WCR)
DEVICE ADDRESSES
CS
0
1
0
1
0
0
INSTRUCTION
A
1
A
0
1
0
0
1
0
DATA
0
P
1
P
0
7
6
5
4
3
2
1
0
2
1
0
2
1
0
2
1
0
2
0
1
0
W
I
P
CS
Table 15. WRITE WIPER CONTROL REGISTER (WCR)
DEVICE ADDRESSES
CS
0
1
0
1
0
0
INSTRUCTION
A
1
A
0
1
0
1
0
0
DATA
0
P
1
P
0
7
6
5
4
3
CS
Table 16. READ DATA REGISTER (DR)
DEVICE ADDRESSES
CS
0
1
0
1
0
0
INSTRUCTION
A
1
A
0
1
0
1
1
R
1
DATA
R
0
P
1
P
0
7
6
5
4
3
CS
Table 17. WRITE DATA REGISTER (DR)
DEVICE ADDRESSES
CS
0
1
0
1
0
0
INSTRUCTION
A
1
A
0
1
1
0
0
R
1
DATA
R
0
P
1
P
0
7
6
5
4
3
CS
High Voltage
Write Cycle
Table 18. READ STATUS (WIP)
DEVICE ADDRESSES
CS
0
1
0
1
0
0
INSTRUCTION
A
1
A
0
0
1
0
1
0
DATA
0
0
1
7
0
6
0
5
0
4
0
3
0
CS
Table 19. GLOBAL TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)
DEVICE ADDRESSES
CS
0
1
0
1
0
0
INSTRUCTION
A
1
A
0
0
0
0
1
R
1
R
0
0
0
CS
Table 20. GLOBAL TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)
DEVICE ADDRESSES
CS
0
1
0
1
0
0
INSTRUCTION
A
1
A
0
1
0
0
0
R
1
R
0
0
0
P
1
P
0
CS
High Voltage
Write Cycle
CS
High Voltage
Write Cycle
Table 21. TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)
DEVICE ADDRESSES
CS
0
1
0
1
0
0
INSTRUCTION
A
1
A
0
1
1
1
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11
0
R
1
R
0
CAT5261
Table 22. TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)
DEVICE ADDRESSES
0
CS
1
0
1
0
INSTRUCTION
0
A
1
A
0
1
1
0
1
R
1
R
0
P
1
P
0
CS
Table 23. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)
DEVICE ADDRESSES
0
CS
NOTE:
1
0
1
0
0
INSTRUCTION
A
1
A
0
0
0
1
0
0
0
DATA
P
1
P
0
I/D
I/D
...
I/D
I/D
CS
Any write or transfer to the Non−volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Table 24. ORDERING INFORMATION
Orderable Part Number
Resistance (kW)
CAT5261WI−50−T1
50
CAT5261WI−00−T1
100
CAT5261YI−50−T2
50
CAT5261YI−00−T2
100
CAT5261WI50
50
CAT5261WI00
100
CAT5261YI50
50
CAT5261YI00
100
Lead Finish
Package
SOIC
TSSOP
Matte-Tin
SOIC
TSSOP
Shipping†
1000 / Tape & Reel
1000 / Tape & Reel
2000 / Tape & Reel
2000 / Tape & Reel
31 Units / Tube
31 Units / Tube
62 Units / Tube
62 Units / Tube
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
12. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com.
13. All packages are RoHS-compliant (Pb-Free, Halogen-Free).
14. The standard lead finish is Matte-Tin.
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CAT5261
PACKAGE DIMENSIONS
SOIC−24, 300 mils
CASE 751BK
ISSUE O
E1
SYMBOL
MIN
A
2.35
2.65
A1
0.10
0.30
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
15.20
15.40
E
10.11
10.51
E1
7.34
7.60
E
e
PIN#1 IDENTIFICATION
MAX
1.27 BSC
e
b
NOM
h
0.25
0.75
L
0.40
1.27
θ
0º
8º
θ1
5º
15º
TOP VIEW
h
D
A2
A
A1
SIDE VIEW
h
q1
q
q1
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
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c
CAT5261
PACKAGE DIMENSIONS
TSSOP24, 4.4x7.8
CASE 948AR
ISSUE A
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.80
7.90
E
6.25
6.40
6.55
E1
4.30
4.40
4.50
e
L
0.65 BSC
0.50
L1
θ
0.60
0.70
1.00 REF
0º
8º
e
TOP VIEW
D
c
A2
A θ1
L
A1
SIDE VIEW
END VIEW
L1
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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For additional information, please contact your local
Sales Representative
CAT5261/D
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