P2042A LCD Panel EMI Reduction IC Product Description The P2042A is a versatile spread spectrum frequency modulator designed specifically for digital flat panel applications. The P2042A reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The P2042A allows significant system cost savings by reducing the number of circuit board layers, ferrite beads, shielding, and other passive components that are traditionally required to pass EMI regulations. The P2042A uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital method. The P2042A modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. Applications The P2042A is targeted towards digital flat panel applications for notebook PCs, palm−size PCs, office automation equipments, and LCD monitors. Features • FCC Approved Method of EMI Attenuation • Provides up to 15 dB of EMI Suppression • Generates a Low EMI Spread Spectrum Clock of the Input www.onsemi.com MARKING DIAGRAM 8 AAM YWW AG TSSOP−8 T SUFFIX CASE 948J 1 AAM = Specific Device Code Y = Year WW= Work Week A = Assembly Location G = Pb−Free Package PIN CONFIGURATION 1 CLKIN VDD CP0 SR0 CP1 ModOUT VSS SSON# (Top View) Frequency • Input/Output Frequency Range: 30 MHz to 110 MHz • Optimized for 32.5 MHz, 54 MHz, 65 MHz and 108 MHz Pixel Clock Frequencies ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. • Internal Loop Filter Minimizes External Components and Board • • • • • • • • Space Eight Selectable High Spread Ranges up to ±2% SSON# Control Pin for Spread Spectrum Enable and Disable Options Low Cycle−to−Cycle Jitter 3.3 V ± 0.3 V Operating Range Low Power CMOS Design Supports Most Mobile Graphic Accelerator and LCD Timing Controller Specifications Available in 8−pin TSSOP Package These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2015 June, 2015 − Rev. 6 1 Publication Order Number: P2042A/D P2042A VDD SR0 CP1 CP0 SSON# PLL Modulation CLKIN Frequency Divider Loop Filter Phase Detector Feedback Divider VCO Output Divider ModOUT Figure 1. Block Diagram VSS PIN CONFIGURATION 1 CLKIN VDD CP0 SR0 CP1 ModOUT VSS SSON# (Top View) Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 CLKIN I External reference frequency input. Connect to externally generated reference signal. 2 CP0 I Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor. Refer to Modulation Selection Table. 3 CP1 I Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor. Refer to Modulation Selection Table. 4 VSS P Ground to entire chip. Connect to system ground. 5 SSON# I Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull−low resistor. 6 ModOUT O Spread spectrum clock output. 7 SR0 I Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor. Refer to Modulation Selection Table. 8 VDD P Power supply for the entire chip www.onsemi.com 2 P2042A Table 2. MODULATION SELECTION Spreading Range (+%) CP0 CP1 SR0 32.5 MHz 54 MHz 65 MHz 81 MHz 108 MHz 0 0 0 1.75 1.53 1.41 1.27 1.10 0 0 1 1.89 1.70 1.55 1.40 1.20 0 1 0 1.39 1.20 1.10 1.00 0.90 0 1 1 2.10 1.85 1.70 1.55 1.35 1 0 0 0.74 0.60 0.57 0.52 0.45 1 0 1 1.10 0.93 0.86 0.77 0.68 1 1 0 0.32 0.30 0.28 0.26 0.23 1 1 1 0.58 0.50 0.45 0.40 0.36 Spread Spectrum Selection Modulation Rate (KHz) (FIN /40) * 62.89 KHz 768) flat panel operating at 65 MHz (FIN) clock speed. A spreading selection of CP0 = 0, CP1 = 1 and SR0 = 0 provides a percentage deviation of ±1.00% from FIN. This results in the frequency on ModOUT being swept from 65.65 to 64.35 MHz at a modulation rate of 102.19 KHz. Refer to Modulation Selection Table 2. The example in the following illustration is a common EMI reduction method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic accelerator manufacturers. The Modulation Selection Table 2 defines the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1). For example, P2042A is designed for high−resolution, flat panel applications and is able to support an XGA (1024 x +3.3 V 65 MHz from graphics accelerator 1 CLKIN VDD 8 2 CP0 SR0 7 3 CP1 ModOUT 6 4 VSS SSON# 5 P2042A 0.1 mF Modulated 65 MHz signal with ±1.00% deviation and modulation rate of 102.19 KHz. This signal is connected back to the spread spectrum input pin (SSIN) of the graphics accelerator. Digital control for the SS enable or disable. Figure 2. Application Schematic for Mobile LCD Graphics Controllers www.onsemi.com 3 P2042A Table 3. ABSOLUTE MAXIMUM RATINGS Symbol VDD, VIN TSTG Parameter Rating Unit Voltage on any pin with respect to Ground −0.5 to +4.6 V Storage Temperature Range −65 to +125 °C 0 to +85 °C °C TA Operating Temperature Range Tsol Wave Solder 265 TJ Junction Temperature 150 °C qJC Thermal Resistance (Junction−to−Case) 125 °C/W TDV Static Discharge Voltage (As per JEDEC STD22− A114−B) 2 KV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 4. DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +85°C) Symbol Max Unit VIL Input low voltage Parameter VSS−0.3 Min Typ 0.8 V VIH Input high voltage 2.0 VDD+0.3 V IIL Input low current (pull−up resistor on inputs CP0, CP1 and SR0) −50 mA IIH Input high current (pull−down resistor on input SSON#) 50 mA VOL Output low voltage (VDD = 3.3 V, IOL = 8 mA) 0.4 V VOH Output high voltage (VDD = 3.3 V, IOL = 8 mA) IDD Static supply current standby mode (CLKIN pulled LOW) ICC Dynamic supply current (3.3 V and 10 pF loading) 6.0 VDD Operating voltage 3.0 tON Power−up time (first locked cycle after power up) ZOUT 2.5 Clock output impedance V 300 mA 15 22 mA 3.3 3.6 V 3.0 ms W 35 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 5. AC ELECTRICAL CHARACTERISTICS (TA = 0°C to +85°C) Symbol Min Typ Max Unit Input frequency 30 74 110 MHz Output frequency 30 74 110 MHz tLH (Note 1) Output rise time (measured at 0.8 V to 2.0 V) 1.1 1.5 2.0 ns tHL (Note 1) Output fall time (measured at 2.0 V to 0.8 V) 0.8 1.2 1.8 ns ±250 ±200 ps 55 % fIN fOUT Parameter tJC Jitter (cycle−to−cycle) tD Output duty cycle <50 MHz ≥50 MHz 45 50 1. tLH and tHL are measured into a capacitive load of 10 pF. Table 6. ORDERING INFORMATION Part Number Marking Temperature Package Shipping† P2042AF−08TR AAM 0°C to +85°C TSSOP−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 4 P2042A PACKAGE DIMENSIONS TSSOP8 CASE 948J ISSUE A 8x 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. K REF 0.10 (0.004) S M T U S V S K 2X L/2 ÇÇÇ ÉÉ ÇÇÇ ÉÉ K1 8 5 J J1 B −U− L PIN 1 IDENT. SECTION N−N 4 1 N 0.25 (0.010) 0.15 (0.006) T U S A −V− M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D G SEE DETAIL E H DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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