P3P623S00 D

P3P623S00B,
P3P623S00E
Product Preview
Timing-Safet Peak EMI
Reduction IC
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Functional Description
P3P623S00B/E is a versatile, 3.3 V Zero−delay buffer designed to
distribute Timing−Safe clocks with Peak EMI reduction. P3P623S00B
is an eight−pin version, accepts one reference input and drives out one
low−skew Timing−Safe clock. P3P623S00E accepts one reference
input and drives out eight low−skew Timing−Safe clocks.
P3P623S00B/E has an SS% that selects 2 different Deviation and
associated Input−Output Skew (TSKEW). Refer to the Spread
Spectrum Control and Input−Output Skew table for details.
P3P623S00E has a CLKOUT for adjusting the Input−Output clock
delay, depending upon the value of capacitor connected at this pin to
GND.
P3P623S00B/E operates from a 3.3 V supply and is available in two
different packages, as shown in the ordering information table.
Application
P3P623S00B/E is targeted for use in Displays and memory interface
systems.
8
1
SOIC−8 NB
CASE 751
TSSOP−16
CASE 948AN
PIN CONFIGURATION
CLKIN
1
NC
2
8
NC
7
VDD
3
6
CLKOUT
4
5
SSON
CLKIN
1
16
CLKOUT
CLKOUT1
2
15
CLKOUT7
VDD
3
14
CLKOUT6
SS%
4
13
VDD
P3P623S00B
General Features
•
•
•
•
•
•
•
•
•
SS%
Clock Distribution with Timing−Safe Peak EMI Reduction
Input Frequency Range: 20 MHz − 50 MHz
2 Different Spread Selection Options
Spread Spectrum can be Turned ON/OFF
External Input−Output Delay Control Option
Supply Voltage: 3.3 V ± 0.3 V
P3P623S00B: 8 Pin SOIC
P3P623S00E: 16 Pin TSSOP
The First True Drop−in Solution
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. P3
1
GND
P3P623S00E
GND
5
12
GND
CLKOUT2
6
11
CLKOUT5
CLKOUT3
7
10
CLKOUT4
DLY_CTRL 8
9
SSON
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Publication Order Number:
P3P623S00/D
P3P623S00B, P3P623S00E
VDD
DLY_CTRL
CLKIN
SS%
PLL
CLKOUT(s)*
(Timing−Safe)
*For P3P623S00E − 8 CLKOUTS
SSON
GND
Figure 1. General Block Diagram
Spread Spectrum Frequency Generation
center modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation.
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The P3P623S00B/E uses
the center modulation spread spectrum technique in which
the modulated output frequency varies above and below the
reference frequency with a specified modulation rate. With
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero input−output
delay.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
Table 1. PIN DESCRIPTION FOR P3P623S00B
1.
2.
3.
4.
Pin #
Pin Name
Type
Description
1
CLKIN (Note 1)
Input
2
NC
3
SS% (Note 3)
Input
4
GND
Power
5
SSON (Note 3)
Input
6
CLKOUT (Note 2)
Output
Buffered clock output (Note 4)
7
VDD
Power
3.3 V supply
8
NC
External reference Clock input, 5 V tolerant input
No Connect
Spread Spectrum Selection. Has an internal pull up resistor
Ground
Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum is
enabled and when LOW, it turns off the spread spectrum. Has an internal pull up resistor
No Connect
Weak pull down
Weak pull−down on all outputs
Weak pull−up on these inputs
Buffered clock output is Timing−Safe
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2
P3P623S00B, P3P623S00E
Table 2. PIN DESCRIPTION FOR P3P623S00E
1.
2.
3.
4.
Pin #
Pin Name
Type
Description
1
CLKIN (Note 1)
Input
2
CLKOUT1 (Note 2)
Output
Buffered clock output (Note 4)
3
VDD
Power
3.3 V supply
4
SS% (Note 3)
Input
5
GND
Power
Ground
6
CLKOUT2 (Note 2)
Output
Buffered clock output (Note 4)
7
CLKOUT3 (Note 2)
Output
Buffered clock output (Note 4)
8
DLY_CTRL
Output
External Input−Output Delay control
9
SSON (Note 3)
Input
10
CLKOUT4 (Note 2)
Output
Buffered clock output (Note 4)
11
CLKOUT5 (Note 2)
Output
Buffered clock output (Note 4)
12
GND
Power
Ground
13
VDD
Power
3.3 V supply
14
CLKOUT6 (Note 2)
Output
Buffered clock output (Note 4)
15
CLKOUT7 (Note 2)
Output
Buffered clock output (Note 4)
16
CLKOUT (Note 2)
Output
Buffered clock output (Note 4)
External reference Clock input, 5 V tolerant input
Spread Spectrum Selection. Refer to the Spread Spectrum Control and Input−Output Skew
Table. Has an internal pull up resistor.
Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum is
enabled and when LOW, it turns off the spread spectrum. Has an internal pull up resistor.
Weak pull down
Weak pull−down on all outputs
Weak pull−up on these inputs
Buffered clock output is Timing−Safe
Table 3. SPREAD SPECTRUM CONTROL AND INPUT−OUTPUT SKEW
Device
Input Frequency
P3P623S00B/E
32 MHz
SS %
Deviation
Input−Output Skew
(+TSKEW)
0
±0.25%
0.125
1
±0.50%
0.25
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Supply Voltage to Ground Potential
VIN
DC Input Voltage (CLKIN)
TSTG
Rating
Unit
−0.5 to +4.6
V
−0.5 to +7
Storage temperature
−65 to +125
°C
°C
Ts
Max. Soldering Temperature (10 sec)
260
TJ
Junction Temperature
150
°C
2
KV
TDV
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
P3P623S00B, P3P623S00E
Table 5. OPERATING CONDITIONS
Parameter
Description
Min
Max
Unit
Operating Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
−40
+85
°C
CL
Load Capacitance
30
pF
CIN
Input Capacitance
7
pF
Max
Units
0.8
V
VDD
Table 6. ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
VIL
Input Low Voltage (Note 5)
VIH
Input High Voltage (Note 5)
IIL
Input LOW Current
VIN = 0 V
50
mA
IIH
Input HIGH Current
VIN = VDD
100
mA
0.4
V
2.0
VOL
Output LOW Voltage (Note 6)
IOL = 8 mA
VOH
Output HIGH Voltage (Note 6)
IOH = −8 mA
IDD
Supply Current
Unloaded outputs
ZO
Output Impedance
V
2.4
V
27
mA
W
23
5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Table 7. SWITCHING CHARACTERISTICS
Parameter
Test Conditions
Input Frequency
Min
Typ
Max
Units
20
50
MHz
50
MHz
60
%
Output Frequency
30 pF load
20
Duty Cycle (Notes 7, 8) = (t2/ t1) x 100
Measured at VDD/2
40
Output Rise Time (Notes 7, 8)
Measured between 0.8 V and 2.0 V
2.5
nS
Output Fall Time (Notes 7, 8)
Measured between 2.0 V and 0.8 V
2.5
nS
Output−to−Output Skew (Notes 7, 8)
All outputs equally loaded with SSOFF
250
pS
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge (Note 8)
Measured at VDD/2 with SSOFF
±350
pS
Device−to−Device Skew (Note 8)
Measured at VDD/2 on the CLKOUT
pins of the device
700
pS
Cycle−to−Cycle Jitter (Notes 7, 8)
Loaded outputs
±250
pS
PLL Lock Time (Note 8)
Stable power supply, valid clock presented on CLKIN pin
1.0
mS
7. All parameters specified with 30 pF loaded outputs.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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4
50
P3P623S00B, P3P623S00E
Switching Waveforms
t1
t2
VDD/2
VDD/2
VDD/2
OUTPUT
Figure 2. Duty Cycle Timing
2V
2V
OUTPUT
0.8 V
0.8 V
t3
t4
Figure 3. All Outputs Rise/Fall Time
VDD/2
OUTPUT
VDD/2
OUTPUT
t5
Figure 4. Output−Output Skew
VDD/2
INPUT
VDD/2
OUTPUT
t6
Figure 5. Input−Output Propagation Delay
VDD/2
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2
t7
Figure 6. Device−Device Skew
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5
P3P623S00B, P3P623S00E
Input
Timing−Safe
Output
+3.3V
VDD
TSKEW −
TSKEW+
0.1uF
OUTPUT
+3.3V
LOAD
VDD
One clock cycle
N=1
GND
TSKEW represents input−output skew
0.1uF
when spread spectrum is ON
For example, TSKEW = ±0.125 for an
Input clock 32 MHz, translates in to
(1/32 MHz)*0.125 = 3.90 nS
Figure 7. Input−Output Skew
Figure 8. Test Circuit
Input
Input
CLKOUT with SSOFF
Timing−Safe CLKOUT
Figure 9. Typical Example of Timing−Safe Waveform
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6
CLKOUT
P3P623S00B, P3P623S00E
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
P3P623S00B, P3P623S00E
PACKAGE DIMENSIONS
TSSOP16, 4.4x5
CASE 948AN
ISSUE O
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.10
A1
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
c
0.13
0.20
D
4.90
5.10
E
6.30
6.50
E1
4.30
4.50
e
0.65 BSC
L
1.00 REF
L1
0.45
0.75
θ
0º
8º
e
PIN#1
IDENTIFICATION
TOP VIEW
D
A2
A
c
θ1
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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8
L
P3P623S00B, P3P623S00E
Table 8. ORDERING INFORMATION
Part Number
Marking
Package Type
Temperature
P3P623S00BG−08SR
ADO
8−pin 150−mil SOIC − TAPE & REEL, Green
0°C to +70°C
P3P623S00BG−08TR
ADO
8−pin 4.4 mm TSSOP − TAPE & REEL, Green
0°C to +70°C
P3I623S00BG−08TR
ADP
8−pin 4.4 mm TSSOP − TAPE & REEL, Green
−40°C to +85°C
P3P623S00EG−16TR
P623
S00E
16−Pin TSSOP − TAPE & REEL, Green
0°C to +70°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
TIMING SAFE is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
P3P623S00/D