PCS3PS550A General Purpose Peak EMI Reduction IC Product Description The PCS3PS550A is a versatile 2.3 V to 3.6 V, Timing−Safe™, spectrum frequency modulator designed specifically for a wide range of clock frequencies. The PCS3PS550A reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of all clock dependent signals. The PCS3PS550A allows significant system cost savings by reducing the number of circuit board layers ferrite beads, shielding that are traditionally required to pass EMI regulations. MARKING DIAGRAMS 1 1 WDFN8 CASE 511AQ Features • • • • • • • • www.onsemi.com LVCMOS Peak EMI reduction IC Input Clock Frequency: 18 MHz − 40 MHz Output Clock Frequency: 18 MHz − 40 MHz Eight different selectable Spread options Power Down option for power save Supply Voltage: 2.3 V − 3.6 V 8−pin WDFN , 2 mm x 2 mm (TDFN) Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications • The PCS3PS550A is targeted towards consumer electronic applications. CAMG G CA = Specific Device Code M = Date Code G = Pb−Free Device PIN CONFIGURATION CLKIN 1 SR2 2 8 VDD 7 SR0 PCS3PS550A PD# 3 6 SR1 VSS 4 5 ModOUT ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2015 September, 2015 − Rev. 2 1 Publication Order Number: PCS3PS550A/D PCS3PS550A SR0 SR1 VDD SR2 ModOUT CLKIN PLL PD# VSS Figure 1. Block Diagram PCS3PS550A accepts an input from an external reference clock and locks to a 1x modulated clock output. SR0, SR1 and SR2 pins enable selecting one of the eight different frequency deviations (Refer Frequency Deviation Selection table). PCS3PS550A also features power down option for power save. PCS3PS550A operates over a supply voltage range of 2.3 V to 3.6 V. PCS3PS550A is available in an 8 Pin WDFN, (2 mm x 2 mm) Package. PCS3PS550A modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 CLKIN I External reference clock input. 2 SR2 I Digital logic input used to select Spreading Range. There is NO default state. Refer Frequency Deviation Selection Table. 3 PD# I Power−down control pin. Powers down the entire chip. There is NO default state. Pull low to enable power−down mode. Connect to VDD to disable Power Down. Output Clock will be LOW when power down is enabled 4 VSS P Ground connection. 5 ModOUT O Spread Spectrum Clock Output. 6 SR1 I Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor. Refer Modulation Selection Table. 7 SR0 I Digital logic input used to select Spreading Range. There is NO default state. Refer Frequency Deviation Selection Table. 8 VDD P Power supply for the entire chip www.onsemi.com 2 PCS3PS550A Table 2. FREQUENCY DEVIATION SELECTION TABLE SR2 SR1 SR0 Spreading Range ($%) (@ 24 MHz) 0 0 0 1 0 0 1 2.5 0 1 0 1.25 0 1 1 1.5 1 0 0 0.4 1 0 1 0.75 1 1 0 1.75 1 1 1 2 Table 3. OPERATING CONDITIONS Symbol VDD Parameter Min Max Unit Supply Voltage with respect to VSS 2.3 3.6 V −20 TA Operating temperature +85 °C CL Load Capacitance 15 pF CIN Input Capacitance 7 pF Table 4. ABSOLUTE MAXIMUM RATING Symbol Rating Unit Voltage on any input pin with respect to VSS −0.5 to +4.6 V Storage temperature −65 to +125 °C TA Operating temperature −40 to +85 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 kV VDD, VIN TSTG TDV Parameter Static Discharge Voltage (As per JEDEC STD22−A114−B) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 3 PCS3PS550A Table 5. DC ELECTRICAL CHARACTERISTICS Symbol Parameter VDD Supply Voltage with respect to VSS VIH Input high voltage VIL Input low voltage IIH Min Typ Max Unit 2.3 2.8 3.6 V 0.65 * VDD V 0.3 * VDD V Input high current (SR1 control pin) 50 mA IIL Input low current (SR1 control pin) 50 mA VOH Output high voltage (IOH = −8 mA) VOL Output low voltage (IOL = 8 mA) ICC Static supply current (PD# pulled to VSS) IDD Dynamic supply current (Unloaded Output @ 24 MHz) 6 Output impedance 40 ZOUT 0.75 * VDD V 0.2 * VDD V 1 mA 9 mA W Table 6. AC ELECTRICAL CHARACTERISTICS Symbol CLKIN ModOUT tLH (Note 1) tHL (Note 1) Parameter Min Typ Max Unit Input Clock frequency 18 24 40 MHz Output Clock frequency 18 24 40 MHz ns Output rise time (Measured between 20% to 80%) Unloaded Output 0.8 1.2 CL = 15 pF 2.4 3 Output fall time (Measured between 80% to 20%) Unloaded Output 0.6 1 CL = 15 pF 1.9 2.8 $175 $250 ps 50 55 % 3 ms $5 % tJC (Note 1) Jitter (cycle to cycle) Unloaded Output tD (Note 1) Output duty cycle tON (Note 1) fdvar 45 PLL lock Time (Stable power supply, valid clock presented on CLKIN pin, PD# toggled from Low to High) $2.5 Frequency Deviation Variation across PVT 1. Parameter is guaranteed by design and characterization. Not 100% tested in production www.onsemi.com 4 ns PCS3PS550A VDDIN R C1 0.1mF C2 2.2mF 8 M Clock VDD 1 CLKIN PCS3PS550A Rs ModOUT VDD SR2, SR1, SR0 0 W* Frequency Deviation Selection Control 0 W* ModOUT Clock 5 VDD 2,6,7 SR2/SR1/SR0 0 W* PD# 3 0 W* VSS Power Down Control 4 NOTE: Refer Pin Description table for Functionality details. *Choose the 0 Ohms resistor either to VDD or to VSS based on the logic state to be set for the control signal Figure 2. Typical Application Schematic PCB Layout Recommendation For optimum device performance, following guidelines are recommended. • Dedicated VDD and VSS (GND) planes. • The device must be isolated from system power supply noise. A 0.1mF and a 2.2 mF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible. All the VDD pins should have decoupling capacitors. • In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers. A typical layout is shown in the figure As short as possible R As short as possible CLKIN VDD SR2 SR0 PD# SR1 GND VSS Modout Figure 3. www.onsemi.com 5 Rs PCS3PS550A ORDERING INFORMATION Part Number PCS3PS550AG−08CR Top Marking Temperature Package Type Shipping† CA −20°C to +85°C 8L− WDFN (TDFN) (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. www.onsemi.com 6 PCS3PS550A PACKAGE DIMENSIONS WDFN8 2x2, 0.5P CASE 511AQ ISSUE A D PIN ONE REFERENCE 2X A B L1 ÍÍÍ ÍÍÍ ÍÍÍ DETAIL A E OPTIONAL CONSTRUCTIONS 0.10 C 2X 0.10 C DIM A A1 A3 b D E e L L1 ÉÉ ÉÉ TOP VIEW EXPOSED Cu A3 DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. L L MOLD CMPD MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.50 0.60 --0.15 DETAIL B A 8X 0.05 C OPTIONAL CONSTRUCTION A1 C SIDE VIEW RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 7X DETAIL A 1 0.78 8X 4 PACKAGE OUTLINE L 2.30 0.88 8 5 8X e/2 e b 0.10 C A 0.05 C 1 8X B 0.35 NOTE 3 0.50 PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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