NIS5452 Series +5 Volt Electronic Fuse The NIS5452 series is a cost effective, resettable fuse. It is designed to buffer the load device from excessive input voltage which can damage sensitive circuits. It also includes an overvoltage clamp circuit that limits the output voltage during transients but does not shut the unit down, thereby allowing the load circuit to continue operation. www.onsemi.com Features • • • • • • 5 AMP, 5 VOLT ELECTRONIC FUSE Integrated Power Device 33 mW Typical Internal Charge Pump Internal Undervoltage Lockout Circuit Internal Overvoltage Clamp These are Pb−Free Devices and are RoHS Compliant WDFN10 CASE 522AA Typical Applications • Mother Board • Hard Drives • Fan Drives MARKING DIAGRAM Pin 1−5 6 7 8 9 10 11 (flag) 1 XXX AYWG G Function SOURCE NC ILIMIT Enable/Fault dv/dt GND VCC XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENTS Src Src Src Src Src GND dv/dt En/Flt ILIM NC (Top View) ORDERING INFORMATION Features Marking Package Shipping† NIS5452MT1TXG Thermal Latching Vclamp = 5.85 V, ILIM = 2.1 A @ 18 W 52 WDFN10 (Pb−Free) 3000 / Tape & Reel NIS5452MT1TWG Thermal Latching Vclamp = 5.85 V, ILIM = 2.1 A @ 18 W 52W WDFN10 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. 3 1 Publication Order Number: NIS5452/D NIS5452 Series VIN Enable Charge Pump Enable/Fault VOUT Current Limit Thermal Shutdown Voltage Clamp ILIMIT dv/dt Control dV/dt UVLO GND Figure 1. Block Diagram FUNCTIONAL PIN DESCRIPTION Pin Function 1−5 Source Description This pin is the source of the internal power FET and the output terminal of the fuse. 7 ILimit A resistor between this pin and the source pin sets the overload and short circuit current limit levels. 8 Enable/Fault The enable/fault pin is a tri−state, bidirectional interface. It can be used to enable or disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that the device is in thermal shutdown. It can also be connected to another device in this family to cause a simultaneous shutdown during thermal events. 9 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal capacitor that allows it to ramp up over a period of 1.4 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional time delay is not required, this pin should be left open. 10 Ground 11 (belly pad) VCC Negative input voltage to the device. This is used as the internal reference for the IC. Positive input voltage to the device. MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage, operating, steady−state (VCC to GND, Note 1) VIN −0.6 to 14 V Thermal Resistance, Junction−to−Air 0.1 in2 copper (Note 2) 0.5 in2 copper (Note 2) JESD51−7 4−layer board qJA Thermal Resistance, Junction−to−Lead (Pin 1) qJL 49 °C/W Thermal Resistance, Junction−to−Case qJC 20 °C/W Pmax 2.5 W TJ −40 to 150 °C Nonoperating Temperature Range TJ −55 to 155 °C Lead Temperature, Soldering (10 Sec) TL 260 °C Total Power Dissipation @ TA = 25°C (operating) Operating Temperature Range (Notes 3 and 4) °C/W 154 93 50 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the device. 2. 1 oz copper, double−sided FR4. 3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the maximum ratings for extended periods of time. 4. Exceeding TJ will thermally destroy the FET. See AND9042/D. www.onsemi.com 2 NIS5452 Series ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 5.0 V, Cin = 2.2 mF, CL = 70 mF, dv/dt pin open, TA = 25°C unless otherwise noted.) Symbol Characteristics Min Typ Max Unit 33 60 50 mW 200 mV POWER FET Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load) (Note 9) ON Resistance (Note 5) TJ = 140°C (Note 6) Tdly RDS(on) ms 200 25 Off State Output Voltage (VCC = 8 Vdc, VGS = 0 Vdc, RL = 100 kW) (Note 9) Voff 10 Output Capacitance (VDS = 5 VDC, VGS = 0 VDC, RL = R) Cout 230 pF ID 4.2 5.0 2.3 A Continuous Current (TA = 25°C, 0.5 in2 pad) (Note 6) (TA = 25°C, JESD51−7 4−layer board) (TA = 80°C, minimum copper) THERMAL LATCH Shutdown Temperature (Note 6) TSD Thermal Hysteresis (Decrease in die temperature for turn on, does not apply to latching parts) THyst 150 175 200 °C °C 45 UNDER/OVERVOLTAGE PROTECTION VOUT Maximum (VCC = 8 V) NIS5452 Vout−clamp 5.5 5.85 6.25 V Undervoltage Lockout (Turn on, Voltage Going High) VUVLO 2.2 2.5 2.8 V UVLO Hysteresis (Note 9) VHyst 0.145 V CURRENT LIMIT Kelvin Short Circuit Current Limit (Note 7) NIS5452 (RLimit = 18 W) ILIM Direct Short Circuit Current Limit (Note 7) NIS5452 (RLimit = 18 W) ILIM 2.0 A Direct Overload Current Limit (Note 7) NIS5452 (RLimit = 18 W) ILIM 7.2 A 1.6 2.1 2.8 A dv/dt CIRCUIT Output Voltage Ramp Time (Enable to VOUT = 4.7 V) (Note 9) tslew Maximum Capacitor Voltage Vmax 0.70 1.4 2.4 ms VCC V ENABLE/FAULT Logic Level Low (Output Disabled) Vin−low 0.35 0.58 0.81 V Logic Level Mid (Thermal Fault, Output Disabled) Vin−mid 0.82 1.4 1.95 V Logic Level High (Output Enabled) (Note 9) Vin−high 1.96 2.2 2.50 V High State Maximum Voltage Vin−max 2.51 3.3 5.2 V −12 −20 mA Logic Low Sink Current (Venable = 0 V) Iin−low Logic High Leakage Current for External Switch (Venable = 3.3 V) Iin−leak 1.0 mA Fan 3.0 Units 750 mA Maximum Fanout for Fault Signal (Total number of chips that can be connected to this pin for simultaneous shutdown) TOTAL DEVICE Bias Current (Operational) (Note 9) IBias 400 Bias Current (Shutdown) (Note 9) IBias 100 Minimum Operating Voltage (Notes 6 and 8) Vmin mA 2.8 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse test: Pulse width 300 ms, duty cycle 2%. 6. Verified by design. 7. Refer to explanation of short circuit and overload conditions in application note AND8140/D. 8. Device will shut down prior to reaching this level based on actual UVLO trip point. 9. Guaranteed by characterization or design. www.onsemi.com 3 NIS5452 Series 11 +5V 5 VOUT 4 VIN NIS5452 3 2 1 I Limit 7 R LIMIT LOAD 8 Enable Enable/Fault GND 10 dV /dt 9 GND Figure 2. Application Circuit with Direct Current Sensing 10 ILIM(OL) (A) 100 ILIM(OL) −40°C 10 125°C 25°C ILIM(SC) 1 1 5 10 15 20 25 5 30 10 15 20 25 RLIMIT (W) RLIMIT (W) Figure 3. Current Limit vs. RLimit for Direct Sensing Figure 4. Overload Current Limit vs. RLimit for Direct Sensing and Ambient Temperature 100 ILIM(SC) (A) ILIM (A) 100 10 −40°C 125°C 1 5 10 15 20 25 30 RLIMIT (W) Figure 5. Short Circuit Current Limit vs. RLimit for Direct Sensing and Ambient Temperature www.onsemi.com 4 30 NIS5452 Series 11 +5V 5 VOUT 4 VIN NIS5452 3 2 1 I Limit 7 R LIMIT LOAD 8 Enable/Fault dV /dt 9 GND 10 Enable GND Figure 6. Application Circuit with Kelvin Current Sensing ILIM(OL) (A) 100 ILIM(OL) 10 −40°C 10 125°C 25°C ILIM(SC) 1 1 5 10 15 20 25 30 5 10 15 20 25 RLIMIT (W) RLIMIT (W) Figure 7. Current Limit vs. RLimit for Kelvin Sensing Figure 8. Overload Current Limit vs. RLimit for Kelvin Sensing and Ambient Temperature 10 ILIM(SC) (A) ILIM (A) 100 −40°C 125°C 1 5 10 15 20 25 30 KELVIN RLIMIT (W) Figure 9. Short Circuit Current Limit vs. RLimit for Kelvin Sensing and Ambient Temperature www.onsemi.com 5 30 NIS5452 Series +5V 11 VIN 5 V OUT 4 3 2 1 + 12 V 11 NIS5452 I Limit V IN 10 VOUT 9 8 7 6 NIS5232 7 I Limit R LIMIT LOAD Enable 8 Enable/Fault GND 10 4 R LIMIT LOAD 3 dV /dt 9 Enable/Fault GND 1 dV /dt 2 GND Figure 10. Common Thermal Shutdown APPLICATION INFORMATION Basic Operation Current Limit This device is a self−protected, resettable, electronic fuse. It contains circuits to monitor the input voltage, output voltage, output current and die temperature. On application of the input voltage, the device will apply the input voltage to the load based on the restrictions of the controlling circuits. The dv/dt of the output voltage will be controlled by the internal dv/dt circuit. The output voltage will slew from 0 V to the rated output voltage in 1.4 ms, unless additional capacitance is added to the dv/dt pin. The device will remain on as long as the temperature does not exceed the 175°C limit that is programmed into the chip. The current limit circuit does not shut down the part but will reduce the conductivity of the FET to maintain a constant current at the internally set current limit level. The input overvoltage clamp also does not shutdown the part, but will limit the output voltage to the Vout−clamp value in the event that the input exceeds that level. An internal charge pump provides bias for the gate voltage of the internal n−channel power FET and also for the current limit circuit. The remainder of the control circuitry operates between the input voltage (VCC) and ground. The current limit circuit uses a SENSEFET along with a reference and amplifier to control the peak current in the device. The SENSEFET allows for a small fraction of the load current to be measured, which has the advantage of reducing the losses in the sense resistor as well as increasing the value and decreasing the power rating of the sense resistor. Sense resistors are typically in the tens of ohms range with power ratings of several milliwatts making them very inexpensive chip resistors. The current limit circuit has two limiting values, one for overload events which are defined as the mode of operation in which the gate is high and the FET is fully enhanced. The short circuit mode of operation occurs when the device is actively limiting the current and the gate is at an intermediate level. For a more detailed description of this circuit please refer to application note AND8140. There are two methods of biasing the current limit circuit for this device. They are shown in the two application figures. Direct current sensing connects the sense resistor between the current limit pin and the load. This method includes the bond wire resistance in the current limit circuit. This resistance has an impact on the current limit levels for a given resistor and may vary slightly depending on the impedance between the sense resistor and the source pins. The on resistance of the device will be slightly lower in this configuration since all five source pins are connected in parallel and therefore, the effective bond wire resistance is one fifth of the resistance for any given pin. The other method is Kelvin sensing. This method uses one of the source pins as the connection for the current sense resistor. This connection senses the voltage on the die and therefore any bond wire resistance and external impedance on the board have no effect on the current limit levels. In this configuration the on resistance is slightly increased relative to the direct sense method since only four of the source pins are used for power. Application Information It is recommended to connect an input decoupling capacitor and an output filtering capacitor to the device to attenuate the power supply noise and the possible voltage spikes caused by inductive loads. The values of these capacitors depend on the characteristics of the power supply and the inductance observed by the device at its input and output, however, minimum values of 1 mF for the input capacitor and 22 mF for the output capacitor are recommended for most applications. Power Limit Refer to Application Note AND9042/D for ILIMSE limitations. www.onsemi.com 6 NIS5452 Series Overvoltage Clamp Enable/Fault The overvoltage clamp consists of an amplifier and reference. It monitors the output voltage and if the input voltage exceeds the specified Vout maximum for the device, the gate drive of the main FET is reduced to limit the output. This is intended to allow operation through transients while protecting the load. If an overvoltage condition exists for many seconds, the device may overheat due to the voltage drop across the FET combined with the load current. In this event, the thermal protection circuit would shut down the device. The Enable/Fault Pin is a multi−function, bidirectional pin that can control the output of the chip as well as send information to other devices regarding the state of the chip. When this pin is low, the output of the fuse will be turned off. When this pin is high the output of the fuse will be turned−on. If a thermal fault occurs, this pin will be pulled low to an intermediate level by an internal circuit. To use as a simple enable pin, an open drain or open collector device should be connected to this pin. Due to its tri−state operation, it should not be connected to any type of logic with an internal pullup device. If the chip shuts down due to the die temperature reaching its thermal limit, this pin will be pulled down to an intermediate level. This signal can be monitored by an external circuit to communicate that a thermal shutdown has occurred. If this pin is tied to another device in this family (NIS5232), a thermal shutdown of one device will cause both devices to disable their outputs. Both devices will turn on once the fault is removed for the auto−retry devices. For the latching thermal device, the outputs will be enabled after the enable pin has been pulled to ground with an external switch and then allowed to go high or after the input power has been recycled. For the auto retry devices, both devices will restart as soon as the die temperature of the device in shutdown has been reduced to the lower thermal limit. The thermal options are listed in the ordering table. Undervoltage Lockout The undervoltage lockout circuit uses a comparator with hysteresis to monitor the input voltage. If the input voltage drops below the specified level, the output switch will be switched to a high impedance state. dv/dt Circuit The dv/dt circuit brings the output voltage up under a linear, controlled rate regardless of the load impedance characteristics. An internal ramp generator creates a linear ramp, and a control circuit forces the output voltage to follow that ramp, scaled by a factor. The default ramp time is approximately 1.4 ms. This can be modified by adding an external capacitor at the dv/dt pin. This pin includes an internal current source of approximately 1 mA. Since the current level is very low, it is important to use a ceramic cap or other low leakage capacitor. Aluminum electrolytic capacitors are not recommended for this circuit. The ramp time from 0 to the nominal output voltage can be determined by the following equation, where t is in seconds: Thermal Protection The NIS545x includes an internal temperature sensing circuit that senses the temperature on the die of the power FET. If the temperature reaches 175°C, the device will shut down, and remove power from the load. Output power can be restored by either recycling the input power or toggling the enable pin. Power will automatically be reapplied to the load for auto−retry devices once the die temperature has been reduced by 45°C. The thermal limit has been set high intentionally, to increase the trip time during high power transient events. It is not recommended to operate this device above 150°C for extended periods of time. t 0−5 + 1.25 E6 @ C ext Where: C is in Farads t is in Seconds Any time that the unit shuts down due to a fault, enable shut−down, or recycling of input power, the timing capacitor will be discharged and the output voltage will ramp from 0 at turn on. www.onsemi.com 7 NIS5452 Series FAULT/ENABLE SIGNAL 3.3V DEVICE OPERATIONAL 1.95V THERMAL SHUTDOWN 0.82V SHUTDOWN, THERMAL RESET GND Figure 11. Enable/Fault Signal Levels 3.3 V Startup Blanking 12 mA 2.2 V En/Fault Enable SD + − 1.4 V 0.58 V SD Thermal Shutdown − + Thermal Reset Thermal SD Figure 12. Enable/Fault Simplified Circuit www.onsemi.com 8 NIS5452 Series PACKAGE DIMENSIONS WDFN10, 3x3, 0.5P CASE 522AA ISSUE A D PIN ONE REFERENCE 0.15 C 2X ÍÍÍ ÍÍÍ ÍÍÍ 0.15 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B A E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW A3 0.10 C 10X A 0.08 C C 1.75 0.35 2.6016 L e 1 5 2.1746 E2 K 2.45 SOLDERING FOOTPRINT* SEATING PLANE D2 10X 0.18 MILLIMETERS NOM MAX 0.75 0.80 0.03 0.05 0.20 REF 0.24 0.30 3.00 BSC 2.50 2.55 3.00 BSC 1.80 1.85 0.50 BSC 0.19 TYP 0.40 0.45 A1 SIDE VIEW 10X MIN 0.70 0.00 10 6 b 10X 10X 0.10 C A BOTTOM VIEW 1.8508 3.3048 0.05 C 0.5651 B 10X 0.3008 NOTE 3 0.5000 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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