ENA1220 D

Ordering number : ENA1220A
LC87F1D64A
CMOS IC
FROM 64K byte, RAM 4K byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
with Full-Speed USB
Overview
The LC87F1D64A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
62.5ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard
programmable), 4096-byte RAM, an on-chip debugger, a sophisticated 16-bit timers/counters (may be divided into 8bit timers), 16-bit timers/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, two synchronous SIO interface
(with automatic block transmit/ receive function), an asynchronous/synchronous SIO interface, a UART interface
(full duplex), a Full-Speed USB interface (function controller), 12-channel 12-bit A/D converter with 12-/8-bit
resolution selector, two 12-bit PWM channels, a system clock frequency divider, an infrared remote control receiver
circuit, and a 30-source 10-vector address interrupt feature.
Features
Flash ROM
• Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source.
• Block-erasable in 128 byte units
• Writes data in 2-byte units
• 65536 × 8 bits
RAM
• 4096 × 9 bits
Minimum Bus Cycle
• 62.5ns (CF=16MHz)
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.03
22212HKIM 20120202-S00004 No.A1220-1/29
LC87F1D64A
Minimum Instruction Cycle Time
• 188ns (CF=16MHz)
Ports
• I/O ports
Ports whose I/O direction can be designated in 1 bit units 28 (P10 to P17, P20 to P27, P30 to P34,
P70 to P73, PWM0, PWM1, XT2)
Ports whose I/O direction can be designated in 4 bit units 8 (P00 to P07)
• USB ports
2 (D+, D-)
• Dedicated oscillator ports
2 (CF1, CF2)
• Input-only port (also used for oscillation)
1 (XT1)
• Reset pins
1 (RES)
• Power pins
6 (VSS1 to 3, VDD1 to 3)
Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
× 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
SIO
• SIO0: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 512/3 tCYC
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO4: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units, suspension and resumption
of data transmission possible in 1 byte or 2 bytes units)
4) Auto-start-on-falling-edge function
5) Clock polarity selectable
6) CRC16 calculator circuit built in
No.A1220-2/29
LC87F1D64A
Full Duplex UART
• UART1
1) Data length: 7/8/9 bits selectable
2) Stop bits: 1 bit (2 bits in continuous transmission mode)
3) Baud rate: 16/3 to 8192/3 tCYC
• UART2
1) Data length: 7/8/9 bits selectable
2) Stop bits: 1 bit (2 bits in continuous transmission mode)
3) Baud rate: 16/3 to 8192/3 tCYC
AD Converter: 12 bits × 12 channels
• 12/8 bits AD converter resolution selectable
PWM: Multifrequency 12-bit PWM × 2 channels
Infrared Remote Control Receiver Circuit
1) Noise reduction function
(noise filter time constant: Approx. 120μs, when the 32.768kHz crystal oscillator is selected as the reference
voltage source.)
2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding
3) X’tal HOLD mode release function
USB Interface (function controller)
• Compliant with USB 2.0 Full-Speed
• Supports a maximum of 4 user-defined endpoints.
EP0
Endpoint
EP1
EP2
EP3
EP4
Transfer
Control

-
-
-
-
Type
Bulk
-




Interrupt
-




Isochronous
Max. payload
-




64
64
64
64
64
Watchdog Timer
• External RC watchdog timer
1) Interrupt and reset signals selectable
• Internal counter watchdog timer
1) Generates an internal reset signal on overflow occurring in a timer that runs on a dedicated low-speed RC
oscillator clock (30kHz).
2) Three operating modes are selectable: continues counting, stops counting, or retains count when the CPU
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
No.A1220-3/29
LC87F1D64A
Interrupts
• 30 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/USB bus active/remote control receiver
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/USB bus reset/USB suspend/UART1 receive/UART2 receive
8
0003BH
H or L
SIO1/USB endpoint/USB-SOF/SIO4/UART1 transmit/UART2 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/PWM0/PWM1
• Priority Level: X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels (the stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal):
For system clock (1MHz)
• Low-speed RC oscillation circuit (internal): For watchdog timer (30kHz)
• CF oscillation circuit:
For system clock
• Crystal oscillation circuit:
For system clock, time-of-day clock
• PLL circuit (internal):
For USB interface (see Fig.5)
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) Reset generated by watchdog timer
(3) Interrupt generation
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation.
2) There are five ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Reset generated by watchdog timer
(3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4, and INT5 pins
* The INT0 and INT1 pins must be configured only for level detection.
(4) Having an interrupt source established at port 0
(5) Having an bus active interrupt source established in the USB interface circuit
Continued on next page.
No.A1220-4/29
LC87F1D64A
Continued from preceding page.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and the infrared remote control receiver circuit.
1) The PLL base clock generator, CF and RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are seven ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Reset generated by watchdog timer
(3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4, and INT5 pins
* The INT0 and INT1 pins must be configured only for level detection.
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
(6) Having an bus active interrupt source established in the USB interface circuit
(7) Having an interrupt source established in the infrared remote control receiver circuit
Package Form
• SQFP48(7×7): Lead-/Halogen-free type
Development Tools
• On-chip debugger: TCB87 type B + LC87F1D64A
Flash ROM Programming Boards
Package
Programming boards
SQFP48(7×7)
W87F55256SQ
Flash ROM Programmer
Maker
Model
Flash Support Group, Inc.
Single
(FSG)
Programmer
Flash Support Group, Inc.
(FSG)
+
Our company
Device
AF9709/AF9709B/AF9709C
Rev.03.06 or later
LC87F1D64A
(Including Ando Electric Co., Ltd. models)
AF9101/AF9103 (main body)
In-circuit
Programmer
(FSG models)
SIB87 (Inter Face Driver)
(Note 2)
(Our company model)
(Note 1)
Our company
Supported version
AF9708
Single/Gang
SKK/SKK Type B
Programmer
(SANYO FWS)
1.04 or later
In-circuit/Gang
SKK-DBG Type B
Chip Data Version
Programmer
(SANYO FWS)
2.15 or later
Application Version
LC87F1D64
Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87)
together can give a PC-less, standalone on-board-programming capabilities.
Note2: It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or Our company for the information.
No.A1220-5/29
LC87F1D64A
Package Dimensions
unit : mm (typ)
3163B
36
0.5
9.0
7.0
25
24
48
13
7.0
9.0
37
1
12
0.5
0.15
0.18
(1.5)
0.1
1.7max
(0.75)
SANYO : SQFP48(7X7)
36
35
34
33
32
31
30
29
28
27
26
25
P27/INT5/DPUP2
P26/INT5/URX2
P25/INT5/UTX2
P24/INT5/SCK4
P23/INT4/SI4/WR
P22/INT4/SO4/RD
P21/INT4/URX1
P20/INT4/UTX1
P07/AN7/T7O
P06/AN6/T6O
P05/AN5/CKO
P04/AN4
Pin Assignment
LC87F1D64A
24
23
22
21
20
19
18
17
16
15
14
13
P03/AN3
P02/AN2
P01/AN1
P00/AN0
VSS2
VDD2
PWM0
PWM1
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
P73/INT3/T0IN/RMIN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
DD+
VDD3
VSS3
P34/UFILT
P33
P32/DBGP2
P31/DBGP1
P30/DBGP0
P70/INT0/T0LCP/AN8/DPUP
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
Top view
SQFP48(7×7) “Lead-/ Halogen-free Type”
No.A1220-6/29
LC87F1D64A
SQFP48
1
NAME
SQFP48
NAME
P73/INT3/T0IN/RMIN
25
P04/AN4
2
RES
26
P05/AN5/CKO
3
XT1/AN10
27
P06/AN6/T6O
4
XT2/AN11
28
P07/AN7/T7O
5
VSS1
29
P20/INT4/UTX1
6
CF1
30
P21/INT4/URX1
7
CF2
31
P22/INT4/SO4/RD
8
VDD1
32
P23/INT4/SI4/WR
9
P10/SO0
33
P24/INT5/SCK4
10
P11/SI0/SB0
34
P25/INT5/UTX2
11
P12/SCK0
35
P26/INT5/URX2
12
P13/SO1
36
P27/INT5/DPUP2
13
P14/SI1/SB1
37
D-
14
P15/SCK1
38
D+
15
P16/T1PWML
39
VDD3
16
P17/T1PWMH/BUZ
40
VSS3
17
PWM1
41
P34/UFILT
18
PWM0
42
P33
19
VDD2
43
P32/DBGP2
20
VSS2
44
P31/DBGP1
21
P00/AN0
45
P30/DBGP0
22
P01/AN1
46
P70/INT0/T0LCP/AN8/DPUP
23
P02/AN2
47
P71/INT1/T0HCP/AN9
24
P03/AN3
48
P72/INT2/T0IN
No.A1220-7/29
LC87F1D64A
System Block Diagram
Interrupt control
Standby control
CF
USB PLL
RC
Clock
generator
X’tal
PLA
IR
FROM
PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
SIO4
Port 1
C register
Timer 0
Port 2
ALU
Timer 1
Port 3
Timer 6
Port 7
Timer 7
INT0 to 5
Noise rejection filter
Base timer
UART1
PWM0
UART2
Stack pointer
PWM1
ADC
Watchdog timer
USB interface
Infrared remote
control receiver circuit
On-chip debugger
PSW
RAR
RAM
No.A1220-8/29
LC87F1D64A
Pin Description
Pin Name
VSS1,
VSS2,
I/O
Description
Option
-
-power supply pin
No
-
+power supply pin
No
VDD3
-
USB reference voltage pin
Yes
Port 0
I/O
• 8-bit I/O port
Yes
VSS3
VDD1,
VDD2
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pins functions
AD converter input port: AN0 to AN7 (P00 to P07)
P05: System Clock Output
P06: Timer 6 toggle outputs
P07: Timer 7 toggle outputs
Port 1
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/beeper output
Port 2
P20 to P27
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P20: UART1 transmit
P21: UART1 receive
P22: SIO4 date I/O/parallel interface RD output
P23: SIO4 date I/O/parallel interface WR output
P24: SIO4 clock I/O
P25: UART2 transmit
P26: UART2 receive
P27: D+ 1.5kΩ pull-up resistor connect pin
Interrupt acknowledge type
Rising
Falling
INT4
enable
enable
INT5
enable
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
Falling
Continued on next page.
No.A1220-9/29
LC87F1D64A
Continued from preceding page.
Pin Name
Port 3
I/O
I/O
Description
Option
• 5-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30 to P34
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P34: USB interface PLL filter pin (see Fig.5)
On-chip debugger pins: DBGP0 to DBGP2 (P30 to P32)
Port 7
I/O
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/
D+ 1.5kΩ pull-up resistor connect pin
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
infrared remote control receiver input
AD converter input port: AN8(P70), AN9(P71)
Interrupt acknowledge type
PWM0
I/O
PWM1
D-
Rising &
Rising
Falling
INT0
enable
enable
disable
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
Falling
• PWM0 and PWM1 output port
H level
L level
enable
enable
No
• General-purpose input port
I/O
• USB data I/O pin D-
No
• General-purpose I/O port
D+
I/O
• USB data I/O pin D+
No
• General-purpose I/O port
RES
Input
XT1
Input
Reset pin
No
• 32.768kHz crystal oscillator input pin
No
• Pin functions
General-purpose input port
AD converter input port: AN10
XT2
I/O
Must be connected to VDD1 if not to be used.
32.768kHz crystal oscillator output pin
No
• Pin functions
General-purpose I/O port
AD converter input port: AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A1220-10/29
LC87F1D64A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option Selected
in Units of
P00 to P07
1 bit
P10 to P17
1 bit
Option Type
1
P20 to P27
Output Type
Pull-up Resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
Programmable
P30 to P34
P70
-
No
Nch-open drain
P71 to P73
-
No
CMOS
Programmable
PWM0, PWM1
-
No
CMOS
No
D+, D-
-
No
CMOS
No
XT1
-
No
Input only
No
XT2
-
No
32.768kHz crystal oscillator output
No
(N channel open drain when in generalpurpose output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
User Option Table
Option Name
Option to be Applied on
P00 to P07
Flash-ROM
Version

Option Selected in Units of
Option Selection
CMOS
1 bit
Nch-open drain
P10 to P17

CMOS
1 bit
Nch-open drain
Port output type
P20 to P27

CMOS
1 bit
Nch-open drain
P30 to P34

CMOS
1 bit
Nch-open drain
Program start
address
-
00000h
0FE00h
USB Regulator
USB Regulator
USB Regulator

(at HOLD mode)
USB Regulator
(at HALT mode)
USE

-

-

-
NONUSE
USE
NONUSE
USE
NONUSE
No.A1220-11/29
LC87F1D64A
Power Pin Treatment
Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of
output ports is supplied by their backup capacitors.
LSI
Power
supply
For backup
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode.
LSI
For backup
Power
supply
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.A1220-12/29
LC87F1D64A
USB Reference Power Option
When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the
reference voltage for USB port output is generated. The active/inactive state of reference voltage circuit can be
switched by the option select. The procedure for marking the option selection is described below.
(1)
Option select
(2)
(3)
(4)
NONUSE
USB Regulator
USE
USE
USE
USB Regulator at HOLD mode
USE
NONUSE
NONUSE
NONUSE
USB Regulator at HALT mode
USE
NONUSE
USE
NONUSE
inactive
Reference voltage circuit
Normal state
active
active
active
state
HOLD mode
active
inactive
inactive
inactive
HALT mode
active
inactive
active
inactive
• When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is
equal to VDD1.
• Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increase by approximately 100μA compared with
when the reference voltage circuit is inactive.
Example 1: VDD1=VDD2=3.3V
• Inactivating the reference voltage circuit (selection (4)).
• Connecting VDD3 to VDD1 and VDD2.
LSI
P70/P27
Power supply
3.3V
1.5kΩ
VDD1
D+
To USB connector
27 to 33Ω
2.2μF
*1
VDD2
D-
VDD3
UFILT
5pF
0Ω
*1: It is necessary to adjust
the value with the IC
mounted on the board.
VSS1 VSS2 VSS3
2.2μF
Example 2: VDD1=VDD2=5.0V
• Activating the reference voltage circuit (selection (1)).
• Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS.
LSI
P70/P27
1.5kΩ
Power supply
5V
VDD1
D+
To USB connector
27 to 33Ω
DVDD2
5pF
VDD3
2.2μF
UFILT
0Ω
0.1µF
VSS1 VSS2 VSS3
2.2μF
No.A1220-13/29
LC87F1D64A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Maximum supply
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
XT1, CF1
Input/output
VIO(1)
Ports 0, 1, 2, 3, 7
VDD1=VDD2=VDD3
voltage
voltage
Peak output
PWM0, PWM1, XT2
IOPH(1)
Ports 0, 1, 2
current
min
typ
max
unit
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
V
• When CMOS output
type is selected
-10
• Per 1 applicable pin
IOPH(2)
PWM0, PWM1
Per 1 applicable pin
IOPH(3)
Port 3
• When CMOS output
P71 to P73
type is selected
-20
-5
High level output current
• Per 1 applicable pin
Average
IOMH(1)
Ports 0, 1, 2
output
type is selected
current
(Note 1-1)
• When CMOS output
-7.5
• Per 1 applicable pin
IOMH(2)
PWM0, PWM1
Per 1 applicable pin
IOMH(3)
Port 3
• When CMOS output
P71 to P73
type is selected
-15
-3
• Per 1 applicable pin
Total output
ΣIOAH(1)
Ports 0, 2
Total of all applicable pins
current
ΣIOAH(2)
Port 1
Total of all applicable pins
PWM0, PWM1
ΣIOAH(3)
Ports 0, 1, 2
Total of all applicable pins
PWM0, PWM1
ΣIOAH(4)
Port 3
Total of all applicable pins
P71 to P73
Peak output
ΣIOAH(5)
D+, D-
Total of all applicable pins
IOPL(1)
P02 to P07
Per 1 applicable pin
current
-25
-25
-45
mA
-10
-25
20
Ports 1, 2
Low level output current
PWM0, PWM1
Average
IOPL(2)
P00, P01
Per 1 applicable pin
30
IOPL(3)
Ports 3, 7, XT2
Per 1 applicable pin
10
IOML(1)
P02 to P07
Per 1 applicable pin
output
Ports 1, 2
current
PWM0, PWM1
(Note 1-1)
15
IOML(2)
P00, P01
Per 1 applicable pin
20
IOML(3)
Ports 3, 7, XT2
Per 1 applicable pin
7.5
Total output
ΣIOAL(1)
Ports 0, 2
Total of all applicable pins
45
current
ΣIOAL(2)
Port 1
Total of all applicable pins
45
PWM0, PWM1
ΣIOAL(3)
Ports 0, 1, 2
Total of all applicable pins
80
PWM0, PWM1
Allowable power
ΣIOAL(4)
Ports 3, 7, XT2
Total of all applicable pins
15
ΣIOAL(5)
D+, D-
Total of all applicable pins
25
Pd max
SQFP48(7×7)
Ta=-30 to +70°C
190
Dissipation
Operating ambient
Topr
Temperature
Storage ambient
Tstg
temperature
-30
+70
-55
+125
mW
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1220-14/29
LC87F1D64A
Allowable Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Operating
VDD(1)
VDD1=VDD2=VDD3
0.183μs≤tCYC≤200μs
supply voltage
0.183μs≤tCYC≤0.383μs
(Note 2-1)
USB circuit active
0.367μs≤tCYC≤200μs Except
for onboard programming
Memory
VHD
VDD1=VDD2=VDD3
sustaining
min
typ
max
unit
3.0
5.5
3.0
5.5
2.7
5.5
2.0
5.5
0.3VDD
VDD
RAM and register contents
sustained in HOLD mode.
supply voltage
High level
VIH(1)
input voltage
Ports 0, 1, 2, 3
P71 to P73
P70 port input/
2.7 to 5.5
interrupt side
+0.7
PWM0, PWM1
VIH(2)
V
Port 70 watchdog
timer side
Low level
VIH(3)
XT1, XT2, CF1, RES
VIL(1)
Ports 1, 2, 3
input voltage
P71 to P73
VIL(2)
P70 port input/
interrupt side
VIL(3)
Port 0
PWM0, PWM1
VIL(4)
VIL(5)
Port 70 watchdog
timer side
VIL(6)
Instruction
XT1, XT2, CF1, RES
tCYC
cycle time
USB circuit active
(Note 2-2)
Except for onboard
programming
External
FEXCF(1)
CF1
system clock
2.7 to 5.5
0.9VDD
VDD
2.7 to 5.5
0.75VDD
4.0 to 5.5
VSS
VDD
0.1VDD
+0.4
2.7 to 4.0
VSS
0.2VDD
4.0 to 5.5
VSS
2.7 to 4.0
VSS
2.7 to 5.5
VSS
2.7 to 5.5
VSS
3.0 to 5.5
0.183
200
3.0 to 5.5
0.183
0.383
2.7 to 5.5
0.367
200
3.0 to 5.5
0.1
16
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
0.25VDD
μs
• CF2 pin open
• System clock frequency
frequency
division ratio=1/1
• External system clock duty
=50±5%
MHz
• CF2 pin open
• System clock frequency
division ratio=1/1
2.7 to 5.5
0.1
8
• External system clock duty
=50±5%
Oscillation
FmCF(1)
CF1, CF2
frequency
range
16MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
(Note 2-3)
8MHz ceramic oscillation
See Fig. 1.
FmRC
Internal RC oscillation
FmSLRC
Internal low-speed RC
oscillation
FsX’tal
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
3.0 to 5.5
16
2.7 to 5.5
8
MHz
2.7 to 5.5
0.3
1.0
2.0
2.7 to 5.5
15
30
60
kHz
2.7 to 5.5
32.768
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A1220-15/29
LC87F1D64A
Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
IIH(2)
Ports 0, 1, 2, 3
Output disabled
Port 7
Pull-up resistor off
RES
PWM0, PWM1
VIN=VDD
(Including output Tr's off
D+, D-
leakage current)
XT1, XT2
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3
Output disabled
Port 7
Pull-up resistor off
RES
PWM0, PWM1
VIN=VSS
(Including output Tr's off
D+, D-
leakage current)
current
IIL(2)
XT1, XT2
typ
For input port specification
VIN=VSS
1
2.7 to 5.5
1
2.7 to 5.5
15
2.7 to 5.5
-1
2.7 to 5.5
-1
CF1
VIN=VSS
2.7 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2, 3
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
P71 to P73
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.7 to 5.5
VDD-0.4
VOH(4)
PWM0, PWM1
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(5)
P05 (CK0 when
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
IOH=-1mA
2.7 to 5.5
VDD-0.4
VOH(6)
using system clock
output function)
P00, P01
unit
2.7 to 5.5
IIL(3)
VOH(3)
max
For input port specification
VIN=VDD
Low level input
min
Low level output
VOL(1)
IOL=30mA
4.5 to 5.5
1.5
voltage
VOL(2)
IOL=5mA
3.0 to 5.5
0.4
VOL(3)
IOL=2.5mA
2.7 to 5.5
0.4
VOL(4)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
VOL(5)
PWM0, PWM1
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
VOH=0.9VDD
VOL(6)
VOL(7)
XT2
Ports 3, 7
VOL(8)
Pull-up resistance
μA
V
Rpu(1)
Ports 0, 1, 2, 3
4.5 to 5.5
15
35
80
Rpu(2)
Port 7
2.7 to 5.5
18
50
150
Hysteresis voltage
VHYS
RES
Ports 1, 2, 3, 7
2.7 to 5.5
0.1VDD
V
Pin capacitance
CP
All pins
2.7 to 5.5
10
pF
kΩ
For pins other than that
under test:
VIN=VSS
f=1MHz
Ta=25°C
No.A1220-16/29
LC87F1D64A
Serial I/O Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
See Fig.8.
typ
max
unit
2
1
pulse width
High level
min
tSCKH(1)
1
pulse width
tSCKHA(1a)
• Continuous data transmission/
reception mode
• USB nor SIO4 are not in use
4
simultaneous.
Input clock
• See Fig.8.
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data
2.7 to 5.5
tCYC
transmission/reception mode
• USB is in use simultaneous.
• SIO4 is not in use
7
simultaneous.
• See Fig.8.
• (Note 4-1-2)
tSCKHA(1c)
• Continuous data transmission/
reception mode
• USB and SIO4 are in use
9
simultaneous.
Serial clock
• See Fig.8.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig.8.
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
tSCKHA(2a)
• Continuous data transmission/
reception mode
tSCKH(2)
• USB nor SIO4 are not in use
+2tCYC
Output clock
simultaneous.
• CMOS output selected
tSCKH(2)
+(10/3)
tCYC
• See Fig.8.
tSCKHA(2b)
• Continuous data transmission/
2.7 to 5.5
reception mode
• USB is in use simultaneous.
• SIO4 is not in use
simultaneous.
tSCKH(2)
+2tCYC
tSCKH(2)
+(19/3)
tCYC
tCYC
• CMOS output selected
• See Fig.8.
tSCKHA(2c)
• Continuous data transmission/
reception mode
• USB and SIO4 are in use
simultaneous.
• CMOS output selected
tSCKH(2)
+2tCYC
tSCKH(2)
+(25/3)
tCYC
• See Fig.8.
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Continued on next page.
No.A1220-17/29
LC87F1D64A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Serial input
Data setup time
SB0(P11),
SI0(P11)
typ
max
unit
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
2.7 to 5.5
0.03
• See Fig.8.
Data hold time
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
(1/3)tCYC
2.7 to 5.5
+0.05
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
Output clock
Input clock
Output delay
Serial output
tsDI(1)
min
μs
1tCYC
2.7 to 5.5
+0.05
(Note 4-1-3)
(1/3)tCYC
2.7 to 5.5
+0.05
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig.8.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
See Fig.8.
2.7 to 5.5
pulse width
High level
Frequency
SCK1(P15)
• CMOS output selected
2
1/2
2.7 to 5.5
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
2.7 to 5.5
0.03
2.7 to 5.5
0.03
SIOCLK.
Data hold time
Output delay time
• See Fig.8.
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
Serial output
unit
1
tSCKL(4)
pulse width
High level
max
1
• See Fig.8.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
Input clock
VDD[V]
• Must be specified with
μs
respect to falling edge of
SIOCLK.
• Must be specified as the time
to the beginning of output state
2.7 to 5.5
(1/3)tCYC
+0.05
change in open drain output
mode.
• See Fig.8.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A1220-18/29
LC87F1D64A
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter
Symbol
Frequency
tSCK(5)
Low level
tSCKL(5)
Specification
Pin/
Conditions
Remarks
SCK4(P24)
VDD[V]
See Fig.8.
tSCKHA(5a)
Input clock
tSCKH(5)
pulse width
Serial clock
tSCK(6)
tSCKL(6)
SCK4(P24)
• USB nor continuous data
transmission/reception mode
Of SIO0 are not in use
simultaneous.
• See Fig.8.
• (Note 4-3-2)
• USB is in use simultaneous.
• Continuous data transmission/
reception mode of SIO0 is not
in use simultaneous.
• See Fig.8.
• (Note 4-3-2)
• USB and continuous data
transmission/ reception
mode of SIO0 are in use
simultaneous.
• See Fig.8.
• (Note 4-3-2)
• CMOS output selected
• See Fig.8.
4
2.7 to 5.5
tCYC
7
10
4/3
1/2
pulse width
High level
tSCK
tSCKH(6)
1/2
pulse width
Output clock
(Note 4-3-3)
tSCKHA(6a)
tSCKHA(6b)
tSCKHA(6c)
Serial input
Data setup time
SO4(P22),
SI4(P23)
Data hold time
• USB nor continuous data
transmission/reception mode
of SIO0 are not in use
simultaneous.
• CMOS output selected
• See Fig.8.
• USB is in use simultaneous.
• Continuous data transmission/
reception mode of SIO0 is not
in use simultaneous.
• CMOS output selected
• See Fig.8.
• USB and continuous data
transmission/reception
mode of SIO0 are in use
simultaneous.
• CMOS output selected
• See Fig.8.
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig.8.
tSCKH(6)
tSCKH(6)
+(5/3)
+(10/3)
tCYC
tCYC
tSCKH(6)
tSCKH(6)
+(5/3)
+(19/3)
tCYC
tCYC
tSCKH(6)
tSCKH(6)
+(5/3)
+(28/3)
tCYC
tCYC
2.7 to 5.5
2.7 to 5.5
tdD0(5)
tCYC
0.03
μs
thDI(3)
2.7 to 5.5
Output delay time
Serial output
tsDI(3)
unit
1
tSCKHA(5c)
Low level
max
1
tSCKHA(5b)
Frequency
typ
2
pulse width
High level
min
SO4(P22),
SI4(P23)
• Must be specified with respect
to rising edge of SIOCLK.
• Must be specified as the time
to the beginning of output
state change in open drain
output mode.
• See Fig.8.
2.7 to 5.5
0.03
(1/3)tCYC
+0.05
μs
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-3-3: When using the serial clock output, make sure that the load at the SCK4 (P24) pin meets the following
conditions:
Clock rise time tSCKR < 0.037μs (see Figure 11.) at Ta=+25°C, VDD=3.3V
No.A1220-19/29
LC87F1D64A
Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High/low level
tP1H(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tP1L(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
INT2(P72),
enabled.
min
typ
2.7 to 5.5
1
2.7 to 5.5
2
2.7 to 5.5
64
2.7 to 5.5
256
2.7 to 5.5
4
2.7 to 5.5
200
max
unit
INT4(P20 to P23),
INT5(P24 to P27)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
constant is 1/1
enabled.
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
constant is 1/32
enabled.
tPIH(4)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
constant is 1/128
tPIL(5)
RMIN(P73)
enabled.
Recognized by the infrared remote
control receiver circuit as a signal
tPIL(6)
RES
tCYC
Resetting is enabled.
RMCK
(Note 5-1)
μs
Note 5-1: Represents the period of the reference clock (1 tCYC to 128 tCYC or the source frequency of the subclock)
for the infrared remote control receiver circuit.
No.A1220-20/29
LC87F1D64A
AD Converter Characteristics at Ta= -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
<12-bits AD Converter Mode>
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute accuracy
ET
AN7(P07)
Conversion time
TCAD
3.0 to 5.5
(Note 6-1)
AN8(P70)
AN9(P71)
typ
max
unit
12
bit
±16
3.0 to 5.5
See conversion time calculation
4.0 to 5.5
32
115
formulas. (Note 6-2)
3.0 to 5.5
64
115
3.0 to 5.5
50
115
3.0 to 5.5
VSS
VDD
AN10(XT1)
AD division ratio=1/16
AN11(XT2)
Analog input
min
VAIN
voltage range
Analog port input
IAINH
VAIN=VDD
3.0 to 5.5
current
IAINL
VAIN=VSS
3.0 to 5.5
1
-1
LSB
μs
V
μA
<8-bits AD Converter Mode>
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute accuracy
ET
AN7(P07)
Conversion time
TCAD
3.0 to 5.5
AN8(P70)
AN9(P71)
AN10(XT1)
typ
max
unit
8
bit
±1.5
(Note 6-1)
3.0 to 5.5
See conversion time calculation
4.0 to 5.5
20
90
formulas. (Note 6-2)
3.0 to 5.5
40
90
3.0 to 5.5
31
90
3.0 to 5.5
VSS
VDD
AD division ratio=1/16
AN11(XT2)
Analog input
min
VAIN
voltage range
Analog port input
IAINH
VAIN=VDD
3.0 to 5.5
current
IAINL
VAIN=VSS
3.0 to 5.5
1
-1
LSB
μs
V
μA
<Conversion time calculation formulas>
12-bits AD Converter Mode: TCAD (Conversion time) = ((52/(AD division ratio))+2) × (1/3) × tCYC
8-bits AD Converter Mode: TCAD (Conversion time) = ((32/(AD division ratio))+2) × (1/3) × tCYC
<Recommended Operating Conditions>
External
Supply Voltage
System Clock
oscillator
Range
Division
FmCF[MHz]
VDD[V]
3.0 to 5.5
(SYSDIV)
16
1/1
Cycle Time
tCYC [ns]
187.5
AD Frequency
Conversion Time (TCAD)[μs]
Division Ratio
(ADDIV)
1/16
12-bit AD
8-bit AD
52.125
32.125
4.0 to 5.5
1/1
250
1/8
34.8
21.5
3.0 to 5.5
1/1
250
1/16
69.5
42.8
4.0 to 5.5
1/1
375
1/8
52.25
32.25
3.0 to 5.5
1/1
375
1/16
104.25
64.25
12
8
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A1220-21/29
LC87F1D64A
Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal mode
Symbol
Conditions
VDD[V]
• FmCF=12MHz ceramic oscillation mode
consumption
VDD1
=VDD2
current
=VDD3
• System clock set to 12MHz side
(Note 7-1)
IDDOP(1)
Specification
Pin/
Remarks
• FsX’tal=32.768kHz crystal oscillation mode
min
typ
max
4.5 to 5.5
9.9
25
3.0 to 3.6
5.7
14
4.5 to 5.5
12
30
3.0 to 3.6
6.8
17
4.5 to 5.5
14
35
3.0 to 3.6
7.7
19
unit
• Internal PLL oscillation stopped
IDDOP(2)
• Internal RC oscillation stopped
• USB circuit stopped
• 1/1 frequency division ration
IDDOP(3)
• FmCF=16MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 16MHz side
• Internal PLL oscillation stopped
IDDOP(4)
• Internal RC oscillation stopped
• USB circuit stopped
• 1/1 frequency division ration
IDDOP(5)
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode
IDDOP(6)
• Internal RC oscillation stopped
• USB circuit active
• 1/1 frequency division ration
IDDOP(7)
mA
• FmCF=16MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
4.5 to 5.5
16
40
3.0 to 3.6
8.8
22
4.5 to 5.5
6.8
16
3.0 to 3.6
4.1
9.7
• 1/2 frequency division ration
2.7 to 3.0
3.5
7.9
• FmCF=16MHz ceramic oscillation mode
4.5 to 5.5
8.2
20
3.0 to 3.6
4.7
12
• System clock set to 16MHz side
• Internal PLL oscillation mode
IDDOP(8)
• Internal RC oscillation stopped
• USB circuit active
• 1/1 frequency division ration
IDDOP(9)
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(10)
• System clock set to 6MHz side
• Internal RC oscillation stopped
IDDOP(11)
IDDOP(12)
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(13)
• System clock set to 8MHz side
• Internal RC oscillation stopped
IDDOP(14)
• 1/2 frequency division ration
2.7 to 3.0
4.0
9.2
IDDOP(15)
• FmCF=0MHz (oscillation stopped)
4.5 to 5.5
0.73
3.5
IDDOP(16)
• FsX’tal=32.768kHz crystal oscillation mode
3.0 to 3.6
0.43
1.9
• 1/2 frequency division ration
2.7 to 3.0
0.37
1.5
• FmCF=0MHz (oscillation stopped)
4.5 to 5.5
45
174
3.0 to 3.6
18
86
2.7 to 3.0
14
63
4.5 to 5.5
4.9
12
• System clock set to internal RC oscillation
IDDOP(17)
IDDOP(18)
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(19)
• System clock set to 32.768kHz side
IDDOP(20)
• 1/2 frequency division ration
HALT mode
IDDHALT(1)
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FsX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
• FmCF=12MHz ceramic oscillation mode
• System clock set to 12MHz side
IDDHALT(2)
μA
• Internal RC oscillation stopped
mA
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• USB circuit stopped
3.0 to 3.6
2.6
6.3
• 1/1 frequency division ration
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A1220-22/29
LC87F1D64A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(3)
Specification
Pin/
Conditions
Remarks
VDD[V]
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FsX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
• FmCF=16MHz ceramic oscillation mode
min
typ
max
4.5 to 5.5
5.7
14
3.0 to 3.6
3.1
7.6
4.5 to 5.5
8.9
23
3.0 to 3.6
4.6
12
4.5 to 5.5
9.7
24
unit
• System clock set to 16MHz side
• Internal PLL oscillation stopped
IDDHALT(4)
• Internal RC oscillation stopped
• USB circuit stopped
• 1/1 frequency division ration
IDDHALT(5)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode
IDDHALT(6)
• Internal RC oscillation stopped
• USB circuit active
• 1/1 frequency division ration
IDDHALT(7)
• HALT mode
• FmCF=16MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 16MHz side
• Internal PLL oscillation mode
IDDHALT(8)
• Internal RC oscillation stopped
mA
3.0 to 3.6
5.0
13
4.5 to 5.5
3.0
7.2
3.0 to 3.6
1.6
3.8
2.7 to 3.0
1.3
2.9
4.5 to 5.5
3.5
8.6
3.0 to 3.6
1.9
4.6
2.7 to 3.0
1.5
3.5
4.5 to 5.5
0.41
2.0
3.0 to 3.6
0.20
0.93
2.7 to 3.0
0.16
0.69
4.5 to 5.5
32
134
3.0 to 3.6
8.8
60
2.7 to 3.0
6.0
40
HOLD mode
4.5 to 5.5
0.08
30
• CF1=VDD or open (External clock mode)
3.0 to 3.6
0.03
18
2.7 to 3.0
0.02
15
• USB circuit active
• 1/1 frequency division ration
IDDHALT(9)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDHALT(10)
• System clock set to 6MHz side
• Internal RC oscillation stopped
IDDHALT(11)
• 1/2 frequency division ration
IDDHALT(12)
• HALT mode
• FmCF=16MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDHALT(13)
• System clock set to 8MHz side
• Internal RC oscillation stopped
IDDHALT(14)
• 1/2 frequency division ration
IDDHALT(15)
• HALT mode
• FmCF=0MHz (oscillation stopped)
IDDHALT(16)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
IDDHALT(17)
• 1/2 frequency division ration
IDDHALT(18)
• HALT mode
• FmCF=0MHz (oscillation stopped)
• FsX'tal=32.768kHz crystal oscillation mode
IDDHALT(19)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
IDDHALT(20)
• 1/2 frequency division ration
HOLD mode
IDDHOLD(1)
consumption
IDDHOLD(2)
current
VDD1
IDDHOLD(3)
IDDHOLD(4)
HOLD mode
4.5 to 5.5
2.9
38
IDDHOLD(5)
• Internal counter watchdog timer operation
3.0 to 3.6
1.4
23
2.7 to 3.0
1.2
20
Timer HOLD mode
4.5 to 5.5
27
118
• CF1=VDD or open (External clock mode)
3.0 to 3.6
6.1
51
2.7 to 3.0
3.8
34
μA
mode (internal low-speed RC oscillation
IDDHOLD(6)
circuit operation)
• CF1=VDD or open (External clock mode)
Timer HOLD
IDDHOLD(7)
mode
IDDHOLD(8)
consumption
current
IDDHOLD(9)
VDD1
• FsX’tal=32.768kHz crystal oscillation mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A1220-23/29
LC87F1D64A
USB Characteristics and Timing at Ta = 0°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Conditions
min
typ
max
unit
High level output
VOH(USB)
• 15kΩ±5% to GND
2.8
3.6
V
Low level output
VOL(USB)
• 1.5kΩ±5% to 3.6 V
0.0
0.3
V
Output signal crossover voltage
VCRS
1.3
2.0
Differential input sensitivity
VDI
Differential input common mode range
VCM
0.8
High level input
VIH(USB)
2.0
Low level input
VIL(USB)
USB data rise time
tR
• |(D+)-(D-)|
0.2
• RS=27 to 33Ω, CL=50pF
• VDD3=3.0 to 3.6V
USB data fall time
tF
• RS=27 to 33Ω, CL=50pF
• VDD3=3.0 to 3.6V
V
V
2.5
V
V
0.8
V
4
20
ns
4
20
ns
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2= VSS3 =0V
Specification
Parameter
Symbol
Pin
Conditions
VDD1
• Excluding power dissipation in the
VDD[V]
Onboard
IDDFW(1)
programming
microcontroller block
3.0 to 5.5
min
typ
max
unit
5
10
mA
20
30
ms
40
60
μs
current
Programming
tFW(1)
• Erase operation
time
tFW(2)
• Write operation
3.0 to 5.5
No.A1220-24/29
LC87F1D64A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator at Ta = 0°C to +70°C
Nominal
Vendor
Frequency
Name
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[V]
[ms]
[ms]
Remarks
8MHz
MURATA
CSTCE8M00G15L**-R0
(33)
(33)
680
2.7 to 5.5
0.1
0.5
C1 and C2
12MHz
MURATA
CSTCE12M0G15L**-R0
(33)
(33)
470
3.0 to 5.5
0.1
0.5
integrated
16MHz
MURATA
CSTCE16M0V13L**-R0
(15)
(15)
330
3.0 to 5.5
0.05
0.25
SMD type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the
following cases (see Figure 4):
• Till the oscillation gets stabilized after VDD goes above the operating voltage lower limit.
• Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed
• Till the oscillation gets stabilized after the HOLD mode is reset.
• Till the oscillation gets stabilized after the X'tal HOLD mode is reset with CFSTOP (OCR register, bit 0) set to 0
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
32.768kHz
EPSON
TOYOCOM
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
OPEN
560k
2.7 to 5.0
1.1
3.0
Remarks
Applicable
MC-306
CL value=12.5pF
SMD type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the
following cases (see Figure 4):
• Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed
• Till the oscillation gets stabilized after the HOLD mode is reset with EXTOSC (OCR register, bit 6) set to 1
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
Rd1
C1
CF
C2
XT2
Rf
Rd2
C3
C4
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
No.A1220-25/29
LC87F1D64A
0.5VDD
Figure 3 AC Timing Measurement Point
VDD
Operating VDD lower limit
Power supply
GND
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Execute oscillation enable instruction.
Operating mode
Unpredictable
Instruction execution
Reset
Reset Time and Oscillation Stabilization Time
HOLD release signal valid
HOLD release signal
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
* When oscillation is enabled
before entry into HOLD mode
XT1, XT2
Operating mode
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
No.A1220-26/29
LC87F1D64A
P34/UFILT
When using the internal PLL circuit to generate
the 48MHz clock for USB , it is necessary to
connect a filter circuit such as that shown to the
left to the P34/UFILT pin.
Rd
0Ω
+
-
Cd
2.2μF
Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit
VD3OEN/
VD3OEN2
P70/
P27
Note:
It’s necessary to adjust the Circuit Constant of the
USB Port Peripheral Circuit each mounting board.
Make the D+ Pull-up resistors available to control
on/off according to the Vbus.
1.5kΩ
D+
27 to 33Ω
5pF
D27 to 33Ω
5pF
Figure 6 USB Port Peripheral Circuit
VDD
RRES
RES
CRES
Note:
Determine the value of CRES and RRES so
that the reset signal is present for a period of
200µs after the supply voltage goes beyond the
lower limit of the IC's operating voltage.
Figure 7 Reset Circuit
No.A1220-27/29
LC87F1D64A
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer period
(SIO0, 4 only)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer period
(SIO0, 4 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 8 Serial I/O Waveforms
tPIL
tPIH
Figure 9 Pulse Input Timing Signal Waveform
Voh
tr
D+
tr
90%
90%
Vcrs
10%
Vol
10%
D-
Figure 10 USB Data Signal Timing and Voltage Level
No.A1220-28/29
LC87F1D64A
VIH(1) min=0.3VDD+0.7V
tSCKR
tSCKR:
Defined as the time period from the time the
state of the output starts changing till the time it
reaches the value of VIH(1).
Figure 11 Serial Clock Output Timing Signal Waveform
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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PS No.A1220-29/29
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