ENA0782 D

Ordering number : ENA0782A
LC87F2416A
CMOS LSI
8-bit Microcontroller
http://onsemi.com
16K-byte Flash ROM / 512-byte RAM / 36-pin
Overview
The LC87F2416A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 16K-byte Flash ROM
(On-board-programmable), 512-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be
divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two
8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous
SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO
interface, a UART interface (full duplex), two 12-bit PWM channels, a 12-bit/8-bit 10-channel AD converter, a
system clock frequency divider, an internal reset and a 20-source 10-vector interrupt feature.
Features
„Flash ROM
• Capable of On-board-programming with wide range (2.2 to 5.5V) of voltage source.
• Block-erasable in 128 byte units
• 16384 × 8 bits (LC87F2416A)
„RAM
• 512 × 9 bits (LC87F2416A)
„Minimum bus cycle time
• 83.3ns (12MHz at VDD = 2.7V to 5.5V)
• 100ns (10MHz at VDD = 2.2V to 5.5V)
• 250ns (4MHz at VDD = 1.8V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
QFP36
„Minimum instruction cycle time
• 250ns (12MHz at VDD = 2.7V to 5.5V)
• 300ns (10MHz at VDD = 2.2V to 5.5V)
• 750ns (4MHz at VDD = 1.8V to 5.5V)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 28 of this data sheet.
Semiconductor Components Industries, LLC, 2014
August, 2014
82114HKPC 20070319-S00003 No.A0782-1/28
LC87F2416A
„Ports
• Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1 bit units
Ports I/O direction can be designated in 4 bit units
• Dedicated oscillator ports/input ports
• Reset pin
• Power pins
16 (P1n, P20, P21, P30, P31, P70 to P73)
8 (P0n)
2 (CF1/XT1,
CF2/XT2)
____
1 ( RES)
3 (VSS1, VSS2, VDD1)
„Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an
8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter (with
toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the
lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes
3) Base timer does not operate when selecting CF Oscillation circuit.
„High-speed clock counter
1) Capable of counting clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Capable of generating real-time output.
„SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.A0782-2/28
LC87F2416A
„UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
„AD converter: 12 bits/8 bits × 10 channels
• 12 bits/8 bits AD converter resolution selectable
„PWM: Multifrequency 12-bit PWM × 2 channels
„Remote control receiver circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
„Clock output function
• Capable of outputting selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock.
• Capable of outputting oscillation clock of sub clock.
„Watchdog timer
• External RC watchdog timer
• Interrupt and reset signals selectable
„Interrupts
• 20 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7/PWM4, PWM5
10
0004BH
H or L
Port 0
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
„Subroutine stack levels: 256levels (the stack is allocated in RAM.)
No.A0782-3/28
LC87F2416A
„High-speed multiplication/division instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
„Oscillation circuits
• RC oscillation circuit (internal)
: For system clock
• Frequency variable RC oscillation circuit (internal) : For system clock
• CF oscillation circuit
: For system clock, with internal Rf
• Crystal oscillation circuit
: For low-speed system clock, with internal Rf
1) CF and crystal oscillation circuit have a shared terminal, and it is software selectable.
2) When reset, CF and Crystal oscillators stop operation. After reset is released, CF oscillator starts operation.
„System clock divider function
• Capable of running with low current consumption.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
„Internal reset function
• Power-On-Reset (POR) function
1) POR resets the system when the power supply voltage is applied.
2) POR release level is selectable from 5 levels (1.55V, 1.72V, 2.00V, 2.37V, 2.65V) by option.
• Low Voltage Detection reset (LVD) function
1) LVD used with POR resets the system when the supply voltage is applied and when it is lowered.
2) LVD function is selectable from enable/disable and the reset level is selectable from 3 levels (1.90V, 2.25V,
2.50V) by option.
„Standby function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, and INT4 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, and INT4 pins to the specified level
(3) Having an interrupt source established at port
(4) Having an interrupt source established in the base timer circuit
Note: X'tal HOLD mode can be used only when crystal oscillation is selected.
No.A0782-4/28
LC87F2416A
„Onchip-Debugger
• Supports software debugging with the IC mounted on the target board.
• For a small pin package, two-channel Onchip-Debugger port ((DBGP0(P0), DBGP1(P1)) are equipped.
„Flash data security
• Protects from illegal access to data in flash memory.
Note: Flash data security cannot guarantee perfect security.
„Package form
• QFP36 (7 × 7): Lead-free type
„Development tools
• Onchip Debugger : TCB87 TypeB + LC87F2416A
„Flash ROM programming boards
Package
Programming boards
QFP36 (7×7)
W87F24Q
■Flash ROM programmer
Maker
Model
Single
AF9708/AF9709/AF9709B
Device
Revision : After 02.60
LC87F2416A
(including product of Ando Electric Co.,Ltd)
Flash Support
AF9723 (Main body)
Group, Inc.
(including product of Ando Electric Co.,Ltd)
Gang
Supported version (Note)
AF9833 (Unit)
(including product of Ando Electric Co.,Ltd)
Our Company
SKK Type-B( SANYOFWS)
Application Version : 1.03 or later
Chip Data Version : 2.03 or later
LC87F2416A
For information about AF series, please contact the following:
Flash Support Group, Inc.
TEL: 053-459-1030
E-mail: [email protected]
„Same package and pin assignment as mask ROM version.
1) LC872400 series options can be set by using flash ROM data. Thus the board used for mass production can be used
for debugging and evaluation without modifications.
2) If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM
version.
No.A0782-5/28
LC87F2416A
Package Dimensions
unit : mm
LQFP36 7x7 / QFP36
CASE 561AV
ISSUE A
0.5±0.2
9.0±0.2
9.0±0.2
36
7.0±0.1
7.0±0.1
1 2
0.65
0.3±0.1
(1.5)
0~10°
0.1±0.1
1.7 MAX
(0.9)
0.15±0.05
0.13
0.10
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
8.40
XXXXXXXX
YDD
8.40
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
XXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
0.65
0.43
1.00
*This information is generic. Please refer to
device data sheet for actual part marking.
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
No.A0782-6/28
LC87F2416A
27
26
25
24
23
22
21
20
19
P03/AN3
P02/AN2
P01/AN1
P00/AN0
VSS2
N.C.
P31/PWM5/INT5/T1IN
P30/PWM4/INT5/T1IN
P21/URX/INT4/T1IN
Pin Assignment
28
29
30
31
32
33
34
35
36
LC87F2416A
18
17
16
15
14
13
12
11
10
P20/UTX/INT4/T1IN
P17/T1PWMH/BUZ
P16/T1PWML
N.C.
N.C.
P15/SCK1/DBGP10
P14/SI1/SB1/DBGP11
P13/SO1/DBGP12
P12/SCK0
P73/INT3/T0IN
RES
I.C.
VSS1
CF1/XT1
CF2/XT2
VDD1
P10/SO0
P11/SI0/SB0
1
2
3
4
5
6
7
8
9
P04/AN4
P05/AN5/CKO/DBGP00
P06/AN6/T6O/DBGP01
P07/AN7/T7O/DBGP02
N.C.
N.C.
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
Top view
QFP36(7 × 7) “Lead-free Type”
QFP36
NAME
QFP36
NAME
1
P73/INT3/T0IN
19
P21/URX/INT4/T1IN
2
RES
20
P30/PWM4/INT5/T1IN
3
I.C.
21
P31/PWM5/INT5/T1IN
4
VSS1
22
N.C.
5
CF1/XT1
23
VSS2
6
CF2/XT2
24
P00/AN0
7
VDD1
25
P01/AN1
8
P10/SO0
26
P02/AN2
9
P11/SI0/SB0
27
P03/AN3
10
P12/SCK0
28
P04/AN4
11
P13/SO1/DBGP12
29
P05/AN5/CKO/DBGP00
12
P14/SI1/SB1/DBGP11
30
P06/AN6/T6O/DBGP01
13
P15/SCK1/DBGP10
31
P07/AN7/T7O/DBGP02
14
N.C.
32
N.C.
15
N.C.
33
N.C.
16
P16/T1PWML
34
P70/INT0/T0LCP/AN8
17
P17/T1PWMH/BUZ
35
P71/INT1/T0HCP/AN9
18
P20/UTX/INT4/T1IN
36
P72/INT2/T0IN
Note: The I.C. (Internally-Connected) and N.C. (Non-Connection) terminal must be kept open.
No.A0782-7/28
LC87F2416A
System Block Diagram
Interrupt control
IR
PLA
Flash ROM
Standby control
X'tal
RC
Clock
generator
CF/
PC
MRC
RES
Reset circuit
(LVD/POR)
Reset control
WDT
ACC
B register
C register
SIO0
Bus interface
SIO1
Port 0
Timer 0
Port 1
Timer 1
Port 2
Timer 6
Port 3
Timer 7
Port 7
Base timer
ADC
PWM4
INT0-2
INT3 (Noise filter)
PWM5
Port 2 INT4
UART1
Port 3 INT5
ALU
PSW
RAR
RAM
Stack pointer
On-chip-debugger
No.A0782-8/28
LC87F2416A
Pin Function Chart
Pin Name
VSS1, VSS2
I/O
-
VDD1
-
Port 0
I/O
Description
Option
-power supply pins
No
+power supply pin
No
• 8-bit I/O port
Yes
• I/O specifiable in 4 bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4 bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
P00 (AN0) to P07 (AN7): AD converter input
P05 (DBGP00) to P07 (DBGP02): On-chip-debugger 0 port
Port 1
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1 bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1 bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
P15 (DBGP10) to P13 (DBGP12): On-chip-debugger 1 port
Port 2
I/O
• 2-bit I/O port
Yes
• I/O specifiable in 1 bit units
P20 to P21
• Pull-up resistors can be turned on and off in 1 bit units.
• Pin functions
P20: UART transmit
P21: UART receive
P20 to P21: INT4 input/HOLD reset input/timer 1 event input
/timer 0L capture input/timer 0H capture input
Interrupt acknowledge type
INT4
Port 3
P30 to P31
I/O
Rising
Falling
○
○
Rising &
Falling
○
H level
L level
×
×
• 2-bit I/O port
Yes
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
• Pin functions
P30:PWM4 output
P31:PWM5 output
P30 to P31: INT5 input/HOLD reset input/timer 1 event input
/timer 0L capture input/timer 0H capture input
Interrupt acknowledge type
INT5
Rising
Falling
○
○
Rising &
Falling
○
H level
L level
×
×
Continued on next page.
No.A0782-9/28
LC87F2416A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
• 4-bit I/O port
No
• I/O specifiable in 1 bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1 bit units.
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input
/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input
/timer 0L capture input
P73: INT3 input (with noise filter)/timer 0 event input
/timer 0H capture input
P70 (AN8), P71 (AN9): AD converter input
Interrupt acknowledge type
INT0
INT1
INT2
INT3
RES
CF1/XT1
I/O
Input
Rising
Falling
○
○
○
○
○
○
○
○
Rising &
Falling
×
×
○
○
H level
L level
○
○
×
×
○
○
×
×
Reset Input pin and Internal reset output pin
No
• Ceramic resonator or 32.768kHz crystal oscillator input pin
No
• Pin function
General-purpose input port
Must be set for General-purpose input port and connected to VSS1 if not to be used.
CF2/XT2
I/O
• Ceramic resonator or 32.768kHz crystal oscillator output pin
No
• Pin function
General-purpose input port
Must be set for General-purpose input port and connected to VSS1 if not to be used.
No.A0782-10/28
LC87F2416A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
P10 to P17
Option selected in
units of
1 bit
1 bit
Option type
Output type
Pull-up resistor
1
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
CMOS
Programmable
Programmable
P20 to P21
1 bit
1
2
Nch-open drain
P30 to P31
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
Note1: Programmable pull-up resistors and selection of low-impedance-pull-up/high-impedance-pull-up for port 0 are
controlled on lower four bits and upper four bits (P00 to P03, P04 to P07).
Note: VSS1 and VSS2 should connect to each other and they should also be grounded.
Onchip Debugger pin connection requirements
Refer to the separate documents, "RD87 Onchip Debugger Installation Manual" and "LC87200series pin connection
requirements Manual", for the requirements on Onchip Debugger pin connections.
No.A0782-11/28
LC87F2416A
1. Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = 0V
Parameter
Maximum supply
Symbol
Pin/Remarks
VDD MAX
VDD1
Input voltage
VI
CF1
Input/output
VIO
Ports 0, 1, 2, 3
Conditions
voltage
voltage
Peak output
Port 7
IOPH(1)
Ports 0, 1, 2, 3
High level output current
current
Mean output
CMOS output select
Per 1 applicable pin
IOPH(2)
Ports P71 to P73
Per 1 applicable pin
IOMH(1)
Ports 0, 1, 2, 3
CMOS output select
current
Per 1 applicable pin
VDD[V]
min.
+6.5
-0.3
-
VDD+0.3
-0.3
-
VDD+0.3
-7.5
Ports P71 to P73
Per 1 applicable pin
Ports P71 to P73
Total of all applicable pins
-10
current
ΣIOAH(2)
Ports P10 to P14
Total of all applicable pins
-20
Ports P15 to P17
Total of all applicable pins
Peak output
IOPL(1)
current
Mean output
Ports P02 to P07
Per 1 applicable pin
-3
-20
-25
20
Ports 1, 2, 3
mA
IOPL(2)
Ports P00, P01
Per 1 applicable pin
30
IOPL(3)
Port 7
Per 1 applicable pin
10
Ports P02 to P07
Per 1 applicable pin
IOML(1)
current
(Note 1-1)
Total of all applicable pins
15
Ports 1, 2, 3
IOML(2)
Ports P00, P01
Per 1 applicable pin
20
7.5
IOML(3)
Port 7
Per 1 applicable pin
Total output
ΣIOAL(1)
Port 7
Total of all applicable pins
15
current
ΣIOAL(2)
Ports 0
Total of all applicable pins
40
ΣIOAL(3)
Ports P10 to P14
Total of all applicable pins
ΣIOAL(4)
Ports 1, 2, 3
Total of all applicable pins
40
ΣIOAL(5)
Ports 0, 1, 2, 3
Total of all applicable pins
70
Pd max(1)
QFP36
Ta=-40 to +85°C
Power dissipation
35
120
Package only
Pd max(2)
V
-5
ΣIOAH(1)
Ports 0, 1, 2, 3
unit
-10
IOMH(2)
ΣIOAH(4)
max.
-
Total output
ΣIOAH(3)
typ.
-0.3
(Note 1-1)
Ports 0, 2, 3
Low level output current
Specification
Ta=-40 to +85°C
mW
Package with thermal
275
resistance board
(Note 1-2)
Operating ambient
Topg
temperature
Storage ambient
temperature
Tstg
-40
-
+85
-55
-
+125
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
No.A0782-12/28
LC87F2416A
2. Allowable Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Conditions
Specification
VDD[V]
min.
typ.
max.
unit
Operating
VDD(1)
0.245μs ≤ tCYC ≤ 200μs
2.7
5.5
supply voltage
VDD(2)
0.294μs ≤ tCYC ≤ 200μs
2.2
5.5
VDD(3)
0.735μs ≤ tCYC ≤ 200μs
1.8
5.5
(Note 2-1)
Memory
VHD
VDD1
VDD1
sustaining
RAM and register contents
1.6
sustained in HOLD mode.
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2, 3
P71 to P73
1.8 to 5.5
P70 port input
0.3VDD
VDD
+0.7
/interrupt side
VIH(2)
VIH(3)
Ports 0
1.8 to 5.5
Port 70 watchdog
timer ____
side
VIH(4)
Low level input
VIL(1)
voltage
CF1, RES
Ports 1, 2, 3
P71 to P73
P70 port input
/interrupt side
VIL(2)
Ports 0
VIL(3)
Port 70 watchdog
VIL(4)
timer side
____
CF1, RES
0.3VDD
VDD
+0.7
1.8 to 5.5
0.9VDD
VDD
1.8 to 5.5
0.75VDD
VDD
4.0 to 5.5
VSS
1.8 to 4.0
VSS
4.0 to 5.5
VSS
1.8 to 4.0
VSS
1.8 to 5.5
VSS
1.8 to 5.5
VSS
0.25VDD
0.1VDD
+0.4
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
Instruction cycle
tCYC
2.7 to 5.5
0.245
200
time
(Note 2-2)
2.2 to 5.5
0.294
200
1.8 to 5.5
0.735
200
2.7 to 5.5
0.1
12
1.8 to 5.5
0.1
4
3.0 to 5.5
0.2
24.4
2.0 to 5.5
0.1
8
(Note 2-1)
External system
FEXCF
CF1
clock frequency
• CF2 pin open
V
μs
• System clock frequency
division ratio = 1/1
• External system clock duty
= 50±5%
• CF2 pin open
• System clock frequency
division ratio = 1/2
• External system clock duty
= 50±5%
Oscillation
FmCF(1)
CF1, CF2
frequency range
(Note 2-3)
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
10MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
4MHz ceramic oscillation
See Fig. 1.
FmRC
Internal RC oscillation
FmMRC
Frequency variable RC
oscillation source oscillation
FsX’tal(1)
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
MHz
2.7 to 5.5
12
2.2 to 5.5
10
1.8 to 5.5
4
1.8 to 5.5
0.3
1.0
2.7 to 5.5
16
1.8 to 5.5
32.768
2.0
kHz
Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
No.A0782-13/28
LC87F2416A
3. Electrical Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V
Parameter
High level input
Symbol
IIH(1)
current
Pin/Remarks
Conditions
Ports 0, 1, 2, 3
Output disabled
Ports 7
____
RES
Pull-up resistor off
VIN=VDD
(Including output Tr's off
Specification
VDD[V]
min.
typ.
max.
unit
1.8 to 5.5
1
1.8 to 5.5
15
leakage current)
IIH(2)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3
Output disabled
Ports 7
____
RES
Pull-up resistor off
IIL(2)
CF1
VIN=VSS
1.8 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
P71 to P73
IOH=-0.35mA
2.7 to 5.5
VDD-0.4
VDD-0.4
Low level input
current
VIN=VSS
(Including output Tr's off
μA
1.8 to 5.5
-1
leakage current)
VOH(3)
IOH=-0.15mA
1.8 to 5.5
VOH(4)
Port 3
IOH=-6mA
4.5 to 5.5
VDD-1
VOH(5)
(Note 3-1)
IOH=-1.4mA
2.7 to 5.5
VDD-0.4
IOH=-0.8mA
1.8 to 5.5
VDD-0.4
IOL=10mA
4.5 to 5.5
1.5
IOL=1.4mA
2.7 to 5.5
0.4
VOH(6)
Low level output
VOL(1)
voltage
VOL(2)
Ports 0, 1, 2, 3
VOL(3)
VOL(4)
Port 7
VOL(5)
VOL(6)
Pull-up resistance
IOL=0.8mA
1.8 to 5.5
0.4
IOL=1.4mA
2.7 to 5.5
0.4
IOL=0.8mA
1.8 to 5.5
0.4
IOL=25mA
4.5 to 5.5
1.5
VOL(7)
IOL=4mA
2.7 to 5.5
0.4
VOL(8)
IOL=2mA
1.8 to 5.5
0.4
VOH=0.9VDD
When Port 0 selected
4.5 to 5.5
15
35
80
1.8 to 4.5
18
50
230
1.8 to 5.5
100
210
400
P00, P01
Rpu(1)
Ports 0, 1, 2, 3
Rpu(2)
Port 7
low-impedance pull-up.
Hysteresis voltage
Pin capacitance
Rpu(3)
Ports 0
VHYS(1)
VHYS(2)
Ports
____ 1, 2, 3, 7,
RES
CP
All pins
High-impedance pull-up.
2.7 to 5.5
0.1VDD
1.8 to 2.7
0.07VDD
1.8 to 5.5
10
V
kΩ
V
For pins other than that under
test:
VIN=VSS
f=1MHz
pF
Ta=25°C
Note 3-1: High level output current on port 3 flows as 4 to 6 times as that of mask ROM version (LC872416A/12A/08A).
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A0782-14/28
LC87F2416A
4. Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V
4-1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pin/Remarks
SCK0(P12)
Conditions
Specification
VDD[V]
Input clock
tSCKH(1)
pulse width
tSCKHA(1)
typ.
max.
unit
2
• See Fig. 5.
1
pulse width
High level
min.
1
• Continuous data
1.8 to 5.5
tCYC
transmission/reception
mode
4
Serial clock
• See Fig. 5.
(Note 4-1-2)
Frequency
tSCK(2)
Low level
tSCKL(2)
SCK0(P12)
4/3
• CMOS output selected
• See Fig. 5.
1/2
Output clock
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
tSCKHA(2)
• Continuous data
1.8 to 5.5
transmission/reception
tSCKH(2)
mode
+2tCYC
• CMOS output selected
tSCKH(2)
+(10/3)
tCYC
tCYC
• See Fig. 5.
Serial input
Data setup time
SB0(P11),
SI0(P11)
• Must be specified with
Data hold time
• See Fig. 5.
thDI(1)
0.05
respect to rising edge of
SIOCLK.
1.8 to 5.5
0.05
Input clock
Output delay
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
transmission/reception
mode
+0.08
μs
(Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
(Note 4-1-3)
Output clock
Serial output
tsDI(1)
tdD0(3)
1tCYC
1.8 to 5.5
+0.08
(Note 4-1-3)
(1/3)tCYC
+0.08
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 5.
No.A0782-15/28
LC87F2416A
4-2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pin/Remarks
SCK1(P15)
Conditions
VDD[V]
min.
Frequency
Low level
1
SCK1(P15)
2
• CMOS output selected
• See Fig. 5.
tSCKL(4)
1/2
1.8 to 5.5
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• See Fig. 5.
thDI(2)
0.05
respect to rising edge of
1.8 to 5.5
0.05
Output delay time
tdD0(4)
SO1(P13),
SB1(P14)
Serial output
• Must be specified with
SIOCLK.
Data hold time
unit
tCYC
tSCKH(3)
pulse width
High level
max.
1
1.8 to 5.5
tSCK(4)
typ.
2
• See Fig. 5.
pulse width
High level
Specification
pulse width
Output clock
Serial clock
Parameter
• Must be specified with
μs
respect to falling edge of
SIOCLK.
• Must be specified as the
time to the beginning of
1.8 to 5.5
(1/3)tCYC
+0.08
output state change in
open drain output mode.
• See Fig. 5.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0782-16/28
LC87F2416A
5. Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Conditions
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
INT2(P72),
enabled.
Specification
VDD[V]
min.
1.8 to 5.5
1
1.8 to 5.5
2
1.8 to 5.5
64
1.8 to 5.5
256
1.8 to 5.5
200
typ.
max.
unit
INT4(P20 to P21),
INT5(P30 to P31)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are enabled.
constant is 1/1
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are enabled.
tCYC
constant is 1/32
tPIH(4)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are enabled.
tPIL(5)
constant is 1/128
____
RES
• External reset input mode.
• Resetting is enabled.
μs
No.A0782-17/28
LC87F2416A
6. AD Converter Characteristics at VSS1 = VSS2 = 0V
<12-bit AD Converter Mode / Ta = -40 to +85°C>
Parameter
Symbol
Pin/Remarks
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07)
AN8(P70)
accuracy
AN9(P71)
Conversion time
TCAD
Specification
Conditions
VDD[V]
2.4 to 5.5
(Note 6-1)
(Note 6-1)
• Ta=-10 to +50°C
• See Conversion time calculation
formulas.
(Note 6-2)
min.
typ.
max.
unit
12
bit
3.0 to 5.5
±16
2.4 to 3.6
±20
4.0 to 5.5
32
115
3.0 to 5.5
64
115
LSB
μs
• See Conversion time calculation
formulas.
(Note 6-2)
2.4 to 3.6
410
425
2.4 to 5.5
VSS
VDD
• Ta=-10 to +50°C
Analog input
VAIN
voltage range
Analog port input
IAINH
VAIN=VDD
2.4 to 5.5
current
IAINL
VAIN=VSS
2.4 to 5.5
1
-1
V
μA
<8-bit AD Converter Mode / Ta = -40 to +85°C>
Parameter
Symbol
Pin/Remarks
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07)
VDD[V]
2.4 to 5.5
(Note 6-1)
TCAD
AN9(P71)
min.
typ.
max.
• See Conversion time calculation
formulas.
(Note 6-2)
unit
8
2.4 to 5.5
AN8(P70)
accuracy
Conversion time
Specification
Conditions
bit
±1.5
4.0 to 5.5
20
90
3.0 to 5.5
40
90
LSB
μs
• See Conversion time calculation
formulas.
(Note 6-2)
2.4 to 3.6
250
265
2.4 to 5.5
VSS
VDD
Ta=-10 to +50°C
Analog input
VAIN
voltage range
Analog port input
IAINH
VAIN=VDD
2.4 to 5.5
current
IAINL
VAIN=VSS
2.4 to 5.5
1
-1
V
μA
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be
measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input
channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the
analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
Conversion time calculation formulas :
12-bits AD Converter Mode : TCAD (Conversion time) = ((52/(division ratio))+2) × (1/3) × tCYC
8-bits AD Converter Mode : TCAD (Conversion time) = ((32/(division ratio))+2) × (1/3) × tCYC
External
Operating supply
oscillation
voltage range
(FmCF)
(VDD)
CF-12MHz
CF-10MHz
CF-4MHz
System division ratio
Cycle time
AD division ratio
(SYSDIV)
(tCYC)
(ADDIV)
4.0V to 5.5V
1/1
250ns
AD conversion time
(TCAD)
12bit AD
8bit AD
1/8
34.8μs
21.5μs
3.0V to 5.5V
1/1
250ns
1/16
69.5μs
42.8μs
4.0V to 5.5V
1/1
300ns
1/8
41.8μs
25.8μs
3.0V to 5.5V
1/1
300ns
1/16
83.4μs
51.4μs
3.0V to 5.5V
1/1
750ns
1/8
104.5μs
64.5μs
2.4V to 3.6V
1/1
750ns
1/32
416.5μs
256.5μs
No.A0782-18/28
LC87F2416A
7. Power-on reset (POR) Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
POR release
PORR
• Select from option.
voltage
Detection voltage
(Note 7-1)
POUKS
1.38
1.55
1.72
1.54
1.72
1.90
2.00V
1.81
2.00
2.19
2.37V
2.12
2.37
2.62
2.65V
2.39
2.65
2.91
0.7
0.95
• Power supply rise time
rise time
max.
1.72V
(Note 7-2)
PORIS
typ.
1.55V
• See Fig. 7.
unknown state
Power supply
min.
100
from 0V to 1.4V.
unit
V
ms
Note 7-1: The POR release level can be selected out of 5 levels only when the LVD reset function is disabled.
Note 7-2: POR is in an unknown state before transistors start operation.
8. Low voltage detection reset (LVD) Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
LVD reset
LVDET
• Select from option.
Voltage
(Note 8-1)
• See Fig. 8.
(Note 8-3)
(Note 8-2)
LVD hysteresys
LVHYS
min.
1.72
1.90
2.08
2.25V
2.03
2.25
2.47
2.50V
2.26
2.50
2.74
×0.054
unknown state
Low voltage
detection
×0.062
LVDET
minimum Width
×0.065
• See Fig. 8.
0.7
(Note 8-4)
TLVDW
V
LVDET
2.50V
LVUKS
unit
LVDET
2.25V
Detection voltage
max.
1.90V
1.90V
width
typ.
0.95
• See Fig. 9.
0.2
ms
(Reply sensitivity)
Note 8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled.
Note 8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note 8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note 8-4: LVD is in an unknown state before transistors start operation.
No.A0782-19/28
LC87F2416A
9. Consumption Current Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
consumption
Pin/Remarks
VDD1
Conditions
Specification
VDD[V]
min.
typ.
Max.
unit
• FmCF=12MHz
ceramic oscillation mode
current
• System clock set to 12MHz side
(Note 9-1)
• Internal RC oscillation stopped.
(Note 9-2)
• Frequency variable RC
oscillation stopped.
2.7 to 5.5
8.3
15.1
2.7 to 3.6
4.8
8.7
3.0 to 5.5
9
16.2
3.0 to 3.6
5.2
8.7
2.2 to 5.5
7.3
13.8
2.2 to 3.6
4.3
8.3
• 1/1 frequency division ratio
IDDOP(2)
• CF1=24MHz external clock
• System clock set to CF1 side
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
• 1/2 frequency division ratio
IDDOP(3)
• FmCF=10MHz
ceramic oscillation mode
• System clock set to 10MHz side
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
• 1/1 frequency division ratio
IDDOP(4)
mA
• FmCF=4 MHz
ceramic oscillation mode
1.8 to 5.5
3.6
7.8
1.8 to 3.6
2.5
4.9
1.8 to 5.5
0.7
2.4
1.8 to 3.6
0.4
1.2
1.8 to 5.5
1.3
2.8
1.8 to 3.6
0.8
1.6
1.8 to 5.5
39
139
1.8 to 3.6
17
66
5.0
39
101
3.3
17
47
2.5
10
29
• System clock set to 4MHz side
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
• 1/1 frequency division ratio
IDDOP(5)
• FsX’tal=32.768kHz
crystal oscillation mode
• System clock set to internal RC
oscillation.
• Frequency variable RC
oscillation stopped.
• 1/2 frequency division ratio
IDDOP(6)
• FsX’tal=32.768kHz
crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 1MHz with
Frequency variable RC
oscillation
• 1/2 frequency division ratio
IDDOP(7)
• FsX’tal=32.768kHz
crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
• 1/2 frequency division ratio
IDDOP(8)
μA
• FsX’tal=32.768kHz
crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C
Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note 9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A0782-20/28
LC87F2416A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(1)
consumption
Pin/remarks
VDD1
Conditions
min.
typ.
max.
unit
• HALT mode
• FmCF=12MHz
current
Specification
VDD[V]
ceramic oscillation mode
(Note 9-1)
• System clock set to 12MHz side
(Note 9-2)
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
2.7 to 5.5
3.4
6.2
2.7 to 3.6
1.8
3.1
3.0 to 5.5
4.9
8.6
3.0 to 3.6
2.3
3.8
2.2 to 5.5
2.9
5.6
2.2 to 3.6
1.5
2.8
• 1/1 frequency division ratio
IDDHALT(2)
• HALT mode
• CF1=24MHz external clock
• System clock set to CF1 side
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(3)
• HALT mode
• FmCF=10MHz
ceramic oscillation mode
• System clock set to 10MHz side
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(4)
mA
• HALT mode
• FmCF=4MHz
ceramic oscillation mode
1.8 to 5.5
1.5
3.7
1.8 to 3.6
0.7
1.6
1.8 to 5.5
0.5
1.4
1.8 to 3.6
0.2
0.6
1.8 to 5.5
T.B.D
T.B.D
1.8 to 3.6
T.B.D
T.B.D
1.8 to 5.5
25
112
• System clock set to 4MHz side
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(5)
• HALT mode
• FsX’tal=32.768kHz
crystal oscillation mode
• System clock set to internal RC
oscillation
• Frequency variable RC
oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(6)
• HALT mode
• FsX’tal=32.768kHz
crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 1MHz with
Frequency variable RC
oscillation
• 1/2 frequency division ratio
IDDHALT(7)
• HALT mode
• FsX’tal=32.768kHz
crystal oscillation mode
• System clock set to 32.768kHz side
μA
• Internal RC oscillation stopped
• Frequency variable RC
oscillation stopped.
1.8 to 3.6
8.5
56
• 1/2 frequency division ratio
Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note 9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A0782-21/28
LC87F2416A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(8)
Pin/remarks
VDD1
Conditions
min.
typ.
max.
unit
• HALT mode
• FsX’tal=32.768kHz
consumption
Specification
VDD[V]
5.0
25
69
3.3
8.5
29
2.5
4.2
15
1.8 to 5.5
0.04
30
1.8 to 3.6
0.02
21
5.0
0.04
2.3
3.3
0.02
1.5
2.5
0.017
1.2
1.8 to 5.5
2.2
34
1.8 to 3.6
1.7
24
5.0
2.2
5.4
3.3
1.7
3.8
2.5
1.5
3.3
1.8 to 5.5
22
106
1.8 to 3.6
7.5
45
crystal oscillation mode
current
(Note 9-1)
• System clock set to 32.768kHz side
(Note 9-2)
• Internal RC oscillation stopped
• Frequency variable RC
oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C
HOLD mode
IDDHOLD(1)
consumption
current
(Note 9-1)
HOLD mode
• CF1=VDD or open
(External clock mode)
IDDHOLD(2)
(Note 9-2)
HOLD mode
• CF1=VDD or open
(External clock mode)
• Ta=-10 to 50°C
IDDHOLD(3)
HOLD mode
• CF1=VDD or open
(External clock mode)
• LVD option selected
IDDHOLD(4)
HOLD mode
• CF1=VDD or open
(External clock mode)
• Ta=-10 to 50°C
• LVD option selected
Timer HOLD
IDDHOLD(5)
mode
• FsX’tal=32.768kHz
consumption
current
(Note 9-1)
(Note 9-2)
Timer HOLD mode
μA
crystal oscillation mode
IDDHOLD(6)
Timer HOLD mode
• FsX’tal=32.768kHz
crystal oscillation mode
• Ta=-10 to 50°C
5.0
22
62
3.3
7.5
23
2.5
2.9
12
Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note 9-2: The consumption current values do not include operational current of LVD function if not specified.
No.A0782-22/28
LC87F2416A
10. F-ROM Programming Characteristics at Ta = +10 to +55°C, VSS1 = VSS2 = 0V
Parameter
Onboard
Symbol
IDDFW
Pin/Remarks
VDD1
Conditions
Specification
VDD[V]
min.
typ.
max.
unit
• Only current of the Flash block.
programming
2.2 to 5.5
5
10
mA
20
30
ms
40
60
μs
current
Programming
tFW(1)
• Erasing time
time
tFW(2)
• Programming time
2.2 to 5.5
11. UART (Full Duplex) Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = 0V
Parameter
Transfer rate
Symbol
UBR
Data length
Stop bits
Parity bits
Pin/Remarks
Conditions
P20, P21
Specification
VDD[V]
1.8 to 5.5
min.
typ.
16/3
max.
unit
8192/3
tCYC
: 7/8/9 bits (LSB first)
: 1 bit(2-bit in continuous data transmission)
: None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit
Start of
transmission
Stop bit
Transmit data (LSB first)
End of
transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Receive data (LSB first)
Start of
reception
End of
reception
UBR
No.A0782-23/28
LC87F2416A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using our
company-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Frequency
Circuit Constant
Vendor Name
12MHz
Oscillator Name
C1
CSTCE12M0G52-R0
CSTCE10M0G52-R0
10MHz
MURATA
CSTLS10M0G53-B0
CSTCR4M00G53-R0
4MHz
CSTLS4M00G53-B0
C2
Rf
Operating
Oscillation
Voltage
Stabilization Time
Rd
Range
Typ
Max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
(10)
(10)
Open
470
2.7 to 3.6
0.1
0.5
(10)
(10)
Open
680
3.6 to 5.5
0.1
0.5
(10)
(10)
Open
680
2.2 to 3.6
0.1
0.5
(10)
(10)
Open
1.0k
3.6 to 5.5
0.1
0.5
(15)
(15)
Open
680
2.2 to 3.6
0.1
0.5
(15)
(15)
Open
680
3.6 to 5.5
0.1
0.5
(15)
(15)
Open
2.2k
1.8 to 2.7
0.2
0.6
(15)
(15)
Open
3.3k
2.7 to 5.5
0.2
0.6
(15)
(15)
Open
2.2k
1.8 to 2.7
0.2
0.6
(15)
(15)
Open
3.3k
2.7 to 5.5
0.2
0.6
Remarks
Internal C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using our
company-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Frequency
32.768kHz
Vendor Name
EPSON
TOYOCOM
Circuit Constant
Oscillator
Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rf
Rd
Range
Typ
Max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
9
9
Open
330k
1.8 to 5.5
1.4
4.0
Remarks
Applicable
MC-306
CL value =
7.0pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1/XT1
CF2/XT2
Rf
C1
Rd
C2
CF/X’tal
Figure 1 CF and XT Oscillator Circuit
0.5VDD
Figure 2 AC Timing Measurement Point
No.A0782-24/28
LC87F2416A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal RC oscillation
tmsCF/tmsX’tal
CF1, CF2
Operating
mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC oscillation
tmsCF/tmsX’tal
CF1, CF2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 3 Oscillation Stabilization Times
No.A0782-25/28
LC87F2416A
VDD
Note: External circuits for reset may vary depending on the
usage of POR and LVD. Please refer to the user’s
manual for more information.
RRES
RES
CRES
Figure 4 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer
period (SIO0 only)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer
period (SIO0 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 5 Serial I/O Output Waveforms
tPIL
tPIH
Figure 6 Pulse Input Timing Signal Waveform
No.A0782-26/28
LC87F2416A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
100μs or longer
Reset period
Unknown-state
(POUKS)
RES
Figure 7 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
Reset period
Reset period
Reset period
LVD reset voltage
(LVDET)
Unknown-state
(LVUKS)
RES
Figure 8 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
No.A0782-27/28
LC87F2416A
VDD
LVD release voltage
LVD reset voltage
LVDET-0.5V
TLVDW
VSS
Figure 9 Low voltage detection minimum width
(Example of momentary power loss / Voltage variation waveform)
ORDERING INFORMATION
Device
LC87F2416AU-EB-2E
Package
QFP36
(Pb-Free)
Shipping (Qty / Packing)
1250 / Tray JEDEC
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nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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PS No.A0782-28/28
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