ENA1335 D

Ordering number : ENA1335B
LC87F2708A
CMOS LSI
8-bit Microcontroller
http://onsemi.com
8K-byte Flash ROM / 512-byte RAM / 14-pin
Overview
The LC87F2708A is an 8-bit microcotroller that, centered around a CPU
running at a minimum bus cycle time of 100ns, integrates on a single chip
a number of hardware features such as 8K-byte flash ROM (onboard
programmable), 512-byte RAM, an on-chip debugger, a sophisticated 16bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter
(may be divided into 8-bit timers or PWMs), a synchronous SIO interface,
a high-speed 12-bit PWM, two high-speed pulse width/period counters, a
7-channel AD converter with 12-/8-bit resolution selector, an analog
comparator, a watchdog timer, an internal reset circuit, a system clock
frequency divider, and a 16-source 10-vector interrupt feature.
MFP14S(225mil)
Features
■ Flash ROM
- 8192  8 bits
- Capable of on-board-programming
with wide range of voltage source (3.0 to 5.5V).
- Block-erasable in 128-byte units
■ RAM
- 512  9 bits
■ Minimum Bus Cycle Time Note1
- 100ns (10MHz) VDD=2.7 to 5.5V Note2
P31/INTB/HCT2IN/DBGP01
1
14
VDD1
P30/INTA/HCT1IN/DBGPX0
2
13
P32/INTC/CMPO/DBGP11
RES
3
12
P33/INTD/HPWM/DBGP12
P10/SO7/INTE/AN0/DBGP02
4
11
P11/SI7/SB7/INTE/IN0+/HCT2IN/AN1
VSS1
5
10
P12/SCK7/INTF/IN0-/AN2
P16/INTF/IN1-/AN6
6
9
P13/INTF/T1PWML/AN3/DBGP20
P15/INTE/IN1+/AN5/DBGP22
7
8
P14/INTE/T1PWMH/AN4/DBGP21
■ Minimum Instruction Cycle Time
- 300ns (10MHz) VDD=2.7 to 5.5V Note2
Note1: The bus cycle time here refers to the ROM read speed.
Note2: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the poweron reset (POR) circuit is 2.87V0.12V.
■ Package Form
- MFP14S (Pb-Free / Halogen Free type)
* This product is licensed from Silicon Storage Technology, Inc.
ORDERING INFORMATION
See detailed ordering and shipping information on page 24 of this data sheet.
Semiconductor Components Industries, LLC, 2014
September, 2014
Ver. 1.02
91214HK 20130322-S00003/91609HKIM No.A1335-1/24
LC87F2708A
■ Ports
- I/O ports
Ports whose I/O direction can be designated in 1 bit units: 11 (P10 to P16, P30 to P33)
- Reset pins:
1 (RES#)
- Power pins:
2 (VSS1, VDD1)
■ Timers
- Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit
counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
- Timer 1: 16-bit timer/counter that can provide with PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle output) + 8-bit timer/counter with an 8-bit
prescaler (with toggle output)
Mode 1: 8-bit PWM with an 8-bit prescaler 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle output)
(Toggle output also possible from lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle output)
(Lower-order 8 bits may be used as PWM.)
■ Serial Interface
- SIO7: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
■ High-speed 12-bit PWM
- System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable
- Duty/period programmable
- Continuous PWM output/specific count PWM output (automatic stop) selectable
■ High-speed Pulse Width/Period Counter
- HCT1: High-speed pulse width/period counter 1
1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable
2) H-level width/L-level width/period measurement modes selectable
3) Input triggering noise filter
- HCT2: High-speed pulse width/period counter 2
1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable
2) Can measure both L-level width and period simultaneously.
3) Input triggering noise filter
4) Input trigger selectable
(from 3 signals, i.e., P11/HCT2IN, P31/HCT2IN, and analog comparator output)
■ AD converter: 12 bits  7 channels
- 12-/8-bit AD converter resolution selectable
No.A1335-2/24
LC87F2708A
■ Analog Comparator
- Sends output to the P32/CMPO port (polarity selectable).
- Edge detection function (shared with INTC and also allows the selection of the noise filter function)
■ Watchdog Timer
- Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed
RC oscillation clock (30kHz).
- Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/
HOLD mode.
■ Interrupt Source Flags
- 16 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any
interrupt requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the
highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt
into the smallest vector address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INTA
2
0000BH
X or L
INTB
3
00013H
H or L
INTC/T0L/INTE
4
0001BH
H or L
INTD/INTF
5
00023H
H or L
T0H/SIO7
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
HCT1
8
0003BH
H or L
HCT2
9
00043H
H or L
ADC/HPWM automatic stop/HPWM cycle
10
0004BH
H or L
None
- Priority levels X > H > L
- Of interrupts of the same level, the one with the smallest vector address takes precedence.
■ Subroutine Stack Levels: 256 levels maximum (The stack is allocated in RAM.)
■ High-speed Multiplication/Division Instructions
- 16 bits × 8 bits
(5 tCYC execution time)
- 24 bits × 16 bits (12 tCYC execution time)
- 16 bits ÷ 8 bits
(8 tCYC execution time)
- 24 bits ÷ 16 bits (12 tCYC execution time)
■ Oscillation Circuits
- Medium speed RC oscillation circuit (internal):
- Low speed RC oscillation circuit (internal):
- High speed RC oscillation circuit (internal):
1) 2 source oscillation frequencies (20MHz or
circuit by optional configuration.
For system clock
(1MHz)
For watchdog timer (30kHz)
For system clock
(20MHz or 40MHz)
40MHz) selectable for the high-speed RC oscillation
■ System Clock Divider Function
- Can run on low current.
- The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s,
38.4s, and 76.8s (when high speed RC oscillation is selected for system clock.).
No.A1335-3/24
LC87F2708A
■ Internal Reset Circuit
- Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 3 levels (2.87V, 3.86V, and 4.35V) by optional
configuration.
- Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power
voltage falls below a certain level.
2) The use or disuse of the LVD function and the low voltage threshold level (3 levels: 2.81V, 3.79V,
and 4.28V) can be selected by optional configuration.
■ Standby Function
- HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are the following three ways of resetting the HALT mode.
<1> Setting the Reset pin to the low level
<2> Generating a reset signal via the watchdog timer or brown-out detector
<3> Having an interrupt generated
- HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The medium- and high-speed RC oscillation circuits automatically stop operation.
2) There are the following four ways of resetting the HOLD mode.
<1> Setting the Reset pin to the low level
<2> Generating a reset signal via the watchdog timer or brown-out detector
<3> Setting at least one of the INTA, INTB, INTC, INTD, INTE, and INTF pins to the specified
level (INTA and INTB HOLD mode reset is available only when level detection is set.)
<4> Applying input signals to the IN+ and IN pins so that the analog comparator output is set to the
specified level (when the analog comparator output is assigned to the INTC input)
■ On-chip Debugger Function
- Supports software debugging with the IC mounted on the target board (LC87D2708A).
LC87F2708A has an On-chip debugger but its function is limited.
- 3 channels of on-chip debugger pins are available.
■ Data Security Function Note3
- Protects the program data stored in flash memory from unauthorized read or copy.
Note3: This data security function does not necessarily provide absolute data security.
■ Development Tools
- On-chip debugger: 1) TCB87-Type B + LC87D2708A
2) TCB87-Type B + LC87F2708A
3) TCB87-Type C (3 wire version) + LC87D2708A
4) TCB87-Type C (3 wire version) + LC87F2708A
No.A1335-4/24
LC87F2708A
■ Programming Board
Package
MFP14S
Programming Board
W87F27M-DBG
■ Flash ROM Programming Board
Maker
Flash Support Group,
Inc. (FSG)
+
ON Semiconductor
(Note 4)
ON Semiconductor
Model
In-circuit
Programmer
Single/Gang
Programmer
In-circuit/
Gang
Programmer
AF9101/AF9103 (Main body)
(FSG models)
SIB87 (Inter Face Driver)
(ON Semiconductor model)
SKK-DBG Type B
(SanyoFWS)
Version
Device
(Note 5)
LC87F2708A
Application Version
1.04 or later
Chip Data Version
2.10 or later
LC87F2708A
For information about AF-series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: [email protected]
Note4: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from ON Semiconductor (SIB87)
together can give a PC-less, standalone on-board-programming capabilities.
Note5: It needs a special programming devices and applications depending on the use of programming environment. Please
ask FSG or ON Semiconductor for the information.
No.A1335-5/24
LC87F2708A
Package Dimensions
unit : mm
SOIC14 W / MFP14S (225 mil)
CASE 751CB
ISSUE A
(Unit: mm)
1.10
SOLDERING FOOTPRINT*
5.70
GENERIC
MARKING DIAGRAM*
1.00
0.47
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
may or may not be present.
No.A1335-6/24
LC87F2708A
Pin Assignment
P31/INTB/HCT2IN/DBGP01
1
14
VDD1
P30/INTA/HCT1IN/DBGPX0
2
13
P32/INTC/CMPO/DBGP11
RES
3
12
P33/INTD/HPWM/DBGP12
P10/SO7/INTE/AN0/DBGP02
4
11
P11/SI7/SB7/INTE/IN0+/HCT2IN/AN1
VSS1
5
10
P12/SCK7/INTF/IN0-/AN2
P16/INTF/IN1-/AN6
6
9
P13/INTF/T1PWML/AN3/DBGP20
P15/INTE/IN1+/AN5/DBGP22
7
8
P14/INTE/T1PWMH/AN4/DBGP21
MFP14S (Pb-Free / Halogen Free type)
MFP14S
NAME
1
P31/INTB/HCT2IN/DBGP01
2
P30/INTA/HCT1IN/DBGPX0
3
RES
4
P10/SO7/INTE/AN0/DBGP02
5
VSS1
6
P16/INTF/IN1-/AN6
7
P15/INTE/IN1+/AN5/DBGP22
8
P14/INTE/T1PWMH/AN4/DBGP21
9
P13/INTF/T1PWML/AN3/DBGP20
10
P12/SCK7/INTF/IN0-/AN2
11
P11/SI7/SB7/INTE/IN0+/HCT2IN/AN1
12
P33/INTD/HPWM/DBGP12
13
P32/INTC/CMPO/DBGP11
14
VDD1
No.A1335-7/24
LC87F2708A
System Block Diagram
Interrupt control
IR
Standby control
PLA
Flash ROM
High-speed Freq. divider
RC
Clock
Mediumgenerator
speed RC
PC
RES#
WDT
(Low-speed RC)
ACC
Reset
control
Reset circuit
(LVD/POR)
Bus interface
Timer 0
Port 1
(INTE-INTF)
Timer 1
Port 3
(INTA-INTD)
DATA
High-speed PWM
BUS
SIO7
DATA
BUS
B register
C register
ALU
PSW
ADC
RAR
High-speed pulse
width/period counter1
High-speed pulse
width/period counter2
RAM
Analog
comparator
Stack pointer
On-chip debugger
No.A1335-8/24
LC87F2708A
Pin Description
Pin Name
VSS1
VDD1
PORT1
P10 to P16
I/O


I/O
Description
Rising &
Falling
H level
L level








External reset input/internal reset output
L level




H level




Falling
Falling




Rising &
Rising
I/O


- 4-bit I/O port
- I/O specifiable in 1-bit units
- Pull-up resistors can be turned on and off in 1-bit units
- Multiplexed pins
P30: INTA input/HOLD release input/timer 0L capture input
/high-speed pulse width/period counter 1 input
P31: INTB input/HOLD release input/timer 0H capture input
/high-speed pulse width/period counter 2 input
P32: INTC input/HOLD release input/timer 0 event input
/timer 0L capture input/analog comparator output
P33: INTD input/HOLD release input/timer 0 event input
/timer 0H capture input/high-speed PWM output
On-chip debugger pin 1: DBGPX0 to DBGP01(P30 to P31)
On-chip debugger pin 2: DBGPX0 to DBGP12(P30, P32 to P33)
- Interrupt acknowledge type
INTA
INTB
INTC
INTD
RES
Falling
I/O
Rising
INTE
INTF
PORT3
P30 to P33
Option
 power supply pin
+ power supply pin
- 7-bit I/O port
- I/O specifiable in 1-bit units
- Pull-up resistors can be turned on and off in 1-bit units
- Multiplexed pins
P10: SIO7 data output
P11: SIO7 data input/bus I/O
/high-speed pulse width/period counter 2 input
P12: SIO7 clock I/O
P13: Timer 1 PWML output
P14: Timer 1 PWMH output
P10, P11, P14, P15:
INTE input/HOLD release input/timer 1 event input
/timer 0L capture input/timer 0H capture input
P12, P13, P16:
INTF input/HOLD release input/timer 1 event input
/timer 0L capture input/timer 0H capture input
AD converter input port: AN0 to AN6(P10 to P16)
Analog comparator input port 0: IN0+, IN0-(P11, P12)
Analog comparator input port 1: IN1+, IN1-(P15, P16)
On-chip debugger pin 1: DBGP02 (P10)
On-chip debugger pin 3: DBGP20 to DBGP22 (P13 to P15)
- Interrupt acknowledge type








No
No
Yes
Yes
No
No.A1335-9/24
LC87F2708A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option
Selected in
Units of
Port Name
P10 to P16
1 bit
P30 to P33
1 bit
Option
Type
Output Type
Pull-up Resistor
1
CMOS
Programmable
2
1
N-channel open drain
CMOS
Programmable
Programmable
2
N-channel open drain
Programmable
On-chip Debugger Pin Processing
For the processing of the on-chip debugger pins, refer to the separately available documents entitled "RD87
On-chip Debugger Installation" and "LC872000 Series On-chip Debugger Pin Processing."
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Pin Name
Board
Software
P10 to P16
OPEN
Set output low
P30 to P33
OPEN
Set output low
User Options
Option Name
Option Type
Flash
Version
Option
Switched in
Unit of
Description
P10 to P16

1bit
CMOS
N-channel open drain
P30 to P33

1bit



Brown-out detector
function


Brown-out trip level


3 levels
Power-on-reset
level


3 levels
Oscillation
frequency


Port output type
Program start address
Brown-out detector reset
function
Power-on-reset function
High-speed RC oscillator
circuit
CMOS
N-channel open drain
00000H
01E00H
Enable: Used
Disable: Not used
20 MHz
40 MHz
No.A1335-10/24
LC87F2708A
1. Absolute Maximum Ratings at Ta=25C, VSS1=0V
Symbol
Maximum supply
voltage
Input voltage
Input/output
voltage
Peak output
current
VDDMAX
VDD1
0.3
VI
VIO
0.3
0.3
IOPH(1)
RES#
 Port 1
 Port 3
Port 1
IOPH(2)
Port 3
IOMH(1)
Port 1
IOMH(2)
Port 3
IOAH(1)
High level output current
Parameter
Mean output
current
(Note 1-1)
Pin/Remarks
Conditions
VDD[V]
min.
7.5
Total of currents at all
applicable pins
20
Total of currents at all
applicable pins
Total of currents at all
applicable pins
Per applicable pin
Per applicable pin
Per applicable pin
20
to
to
mA
10
5
7.5
Peak output
current
Mean output
current
(Note 1-1)
IOPL(1)
IOPL(2)
IOML(1)
IOML(2)
Port 3
Per applicable pin
7.5
Total output
current
IOAL(1)
 Port 10
 Ports 30, 31
 Ports 11 to 16
 Ports 32, 33
 Port 1
 Port 3
Total of currents at all
applicable pins
Total of currents at all
applicable pins
Total of currents at all
applicable pins
25
MFP14S
 Ta=40 to +85C
 Independent package
 Ta=40 to +85C
 Mounted on thermal
test board
 (Note 1-2)
IOAH(2)
IOAL(2)
IOAL(3)
Power dissipation
Pdmax(1)
Pdmax(2)
Operating ambient
temperature
Storage ambient
temperature
unit
V
VDD+0.3
VDD+0.3
 Ports 10, 15,
16
 Ports 30, 31
 Ports 11 to 14
 Ports 32, 33
 Port 1
 Port 3
Port 1
Port 3
Port 1
Total output
current
IOAH(3)
Low level output current
 CMOS output selected
 Per applicable pin
 CMOS output selected
 Per applicable pin
 CMOS output selected
 Per applicable pin
 CMOS output selected
 Per applicable pin
Specification
typ.
max.
to
+6.5
35
15
10
10
35
55
113
mW
260
Topr
40
to
+85
Tstg
55
to
+125
C
Note 1-1: Mean output current refers to the average of output currents measured for a period of 100ms.
Note 1-2: Thermal test board used conforms to SEMI (size : 76.1 114.3 1.6 tmm, glass epoxy board).
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
No.A1335-11/24
LC87F2708A
2. Allowable Operating Conditions at Ta=40 to +85C, VSS1=0V
Parameter
Operating supply
voltage (Note 2-1)
Memory
sustaining supply
voltage
High level input
voltage
Low level input
voltage
Symbol
Conditions
min.
typ.
max.
unit
V
VDD1
0.272s ≤ tCYC ≤ 100s
2.7
5.5
VHD
VDD1
RAM and register contents
sustained in HOLD mode
2.0
5.5
VIH(1)
 Port 1
 Port 3
Output disabled
VDD
VIH(2)
RES#
2.7 to 5.5
0.3VDD
+0.7
0.75VDD
VIL(1)
 Port 1
 Port 3
4.0 to 5.5
VSS
2.7 to 4.0
VSS
0.1VDD
+0.4
0.2VDD
2.7 to 5.5
VSS
0.25VDD
2.7 to 5.5
0.272
100
s
4.5 to 5.5
38
40
42
MHz
4.5 to 5.5
37.6
40
42.4
3.5 to 5.5
36.8
40
43.2
2.7 to 5.5
32
40
43.2
3.0 to 5.5
19
20
21
2.7 to 5.5
18.7
20
21.3
2.7 to 5.5
0.5
1.0
2.0
2.7 to 5.5
15
30
60
kHz
100
s
Output disabled
RES#
tCYC
FmHRC(1)
FmHRC(2)
FmHRC(3)
 High-speed RC oscillation
 40MHz selected as option
 Ta=20 to +85C
 High-speed RC oscillation
 40MHz selected as option
 Ta=40 to +85C
FmHRC(4)
FmHRC(5)
FmHRC(6)
FmRC
FmSLRC
Oscillation
stabilization time
Specification
VDD[V]
VDD
VIL(2)
Instruction cycle
time (Note 2-2)
Oscillation
frequency range
Pin/Remarks
tmsHRC
 High-speed RC oscillation
 20MHz selected as option
 Ta=20 to +85C
 High-speed RC oscillation
 20MHz selected as option
 Ta=40 to +85C
Medium-speed RC
oscillation
Low-speed RC oscillation
 When high-speed RC
oscillation state is switched
from stopped to enabled.
 See Fig. 2.
2.7 to 5.5
2.7 to 5.5
VDD
Note 2-1: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the
power-on reset (POR) circuit is 2.87V0.12V.
Note 2-2: Relationship between tCYC and oscillation frequency is as follows:
- When system clock source is set to medium-speed RC oscillation
3/FmRC at a division ratio of 1/1, 6/FmRC at a division ratio of 1/2, 12/FmRC a division ratio of 1/4, and so
forth
- When system clock source is set to high-speed RC oscillation (40MHz selected by optional configuration)
12/FmHRC at a division ratio of 1/1, 24/FmHRC at a division ratio of 1/2, 48/FmHRC a division ratio of 1/4,
and so forth
- When system clock source is set to high-speed RC oscillation (20MHz selected by optional configuration)
6/FmHRC at a division ratio of 1/1, 12/FmHRC at a division ratio of 1/2, 24/FmHRC a division ratio of 1/4, and
so forth
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
No.A1335-12/24
LC87F2708A
3. Electrical Characteristics at Ta=40 to +85C, VSS1=0V
Parameter
High level input
current
Low level input
current
High level output
voltage
Symbol
IIH(1)
 Port 1
 Port 3
IIH(2)
RES#
IIL
 Port 1
 Port 3
VOH(1)
CMOS output type
port 1
VOH(2)
VOH(3)
VOH(4)
Low level output
voltage
Pin/Remarks
VOL(1)
Rpu(1)
Rpu(2)
max.
unit
2.7 to 5.5
min.
typ.
1
A
2.7 to 5.5
1
2.7 to 5.5
1
4.5 to 5.5
VDD1
IOH=0.35mA
2.7 to 5.5 VDD0.4
CMOS output type
port 3
IOH=5mA
4.5 to 5.5 VDD1.5
IOH=0.7mA
2.7 to 5.5 VDD0.4
Port 1
IOL=10mA
4.5 to 5.5
1.5
IOL=1.4mA
2.7 to 5.5
0.4
Port 3
VOL(4)
Pull-up resistance
 Output disabled
 Pull-up resistor off
 VIN=VDD
(including output Tr. off
leakage current)
VIN=VDD
Specification
VDD[V]
 Output disabled
 Pull-up resistor off
 VIN=VSS
(including output Tr. off
leakage current)
IOH=1mA
VOL(2)
VOL(3)
Conditions
 Port 1
 Port 3
V
IOL=5mA
4.5 to 5.5
1.5
IOL=0.7mA
2.7 to 5.5
0.4
VOH=0.9VDD
4.5 to 5.5
15
35
80
kΩ
2.7 to 4.5
18
50
150
Rpu(3)
RES#
2.7 to 5.5
216
360
504
Hysteresis voltage
VHYS
2.7 to 5.5
0.1VDD
V
Pin capacitance
CP
 Port 1
 Port 3
 RES#
All pins
2.7 to 5.5
10
pF
 VIN=VSS for pins
other than that under
test
 f=1MHz
 Ta=25C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A1335-13/24
LC87F2708A
4. Serial I/O Characteristics at Ta=40 to +85C, VSS1=0V
4-1. SIO7 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Input clock
Output clock
Serial clock
Frequency
tSCK(1)
Low level
pulse width
High level
pulse width
tSCKL(1)
Frequency
tSCK(2)
SCK7(P12)
Conditions
 See Fig. 4.
(Note 4-1-2)
Specification
VDD[V]
min.
2.7 to 5.5
2
Serial input
tSCKL(2)
Data hold time
thDI(1)
Serial output
Input clock Output clock
tdDO(1)
tdDO(2)
max.
unit
tCYC
1
SCK7(P12)
 CMOS output
selected
 See Fig. 4.
2.7 to 5.5
4/3
1/2
tSCKH(2)
tsDI(1)
typ.
1
tSCKH(1)
Low level
pulse width
High level
pulse width
Data setup time
Output
delay time
Pin/Remarks
tSCK
1/2
SB7(P11),
SI7(P11)
SO7(P10),
SB7(P11)
 Must be specified
with respect to rising
edge of SIOCLK.
 See Fig. 4.
2.7 to 5.5
 Must be specified
with respect to rising
edge of SIOCLK.
 Must be specified as
the time to the
beginning of output
state change in open
drain output mode.
 See Fig. 4.
2.7 to 5.5
s
0.03
0.03
1tCYC
+0.05
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in transmission/reception mode, the time from SI7RUN being set when serial clock
is "H" to the first falling edge of the serial clock must be longer than 1tCYC.
No.A1335-14/24
LC87F2708A
5. Pulse Input Conditions at Ta=40 to +85C, VSS1=0V
Parameter
High/low level
pulse width
Symbol
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
Pin/Remarks
INTA(P30),
INTB(P31),
INTD(P33),
INTE
(P10, P11, P14,
P15),
INTF
(P12, P13, P16)
INTC(P32) when
noise filter time
constant is "none"
tPIH(3)
tPIL(3)
INTC(P32) when
noise filter time
constant is "1/16"
tPIH(4)
tPIL(4)
INTC(P32) when
noise filter time
constant is "1/32"
tPIH(5)
tPIL(5)
INTC(P32) when
noise filter time
constant is "1/64"
tPIH(6)
tPIL(6)
HCT1IN(P30)
tPIH(7)
tPIL(7)
HCT2IN(P11, P31)
tPIL(8)
RES#
Conditions
Specification
VDD[V]
min.
 Interrupt source flag can be
set.
 Event inputs for timers 0
and 1 are enabled.
2.7 to 5.5
1
 Interrupt source flag can be
set.
 Event inputs for timer 0 are
enabled.
 Interrupt source flag can be
set.
 Event inputs for timer 0 are
enabled.
 Interrupt source flag can be
set.
 Event inputs for timer 0 are
enabled.
 Interrupt source flag can be
set.
 Event inputs for timer 0 are
enabled.
Pulses can be recognized as
signals by the high-speed
pulse width/period counter 1.
Pulses can be recognized as
signals by the high-speed
pulse width/period counter 2.
Resetting is enabled.
2.7 to 5.5
1
2.7 to 5.5
64
2.7 to 5.5
128
2.7 to 5.5
256
2.7 to 5.5
3
2.7 to 5.5
6
2.7 to 5.5
200
typ.
max.
unit
tCYC
H1CK
(Note
5-1)
H2CK
(Note
5-2)
s
Note 5-1: H1CK denotes the period of the base clock (1 to 8 high-speed RC oscillation clock or system clock) for the
high-speed pulse width/period counter 1.
Note 5-2: H2CK denotes the period of the base clock (2 to 16 high-speed RC oscillation clock or system clock) for the
high-speed pulse width/period counter 2.
6. Comparator Characteristics at Ta=40 to +85C, VSS1=0V
Parameter
Symbol
Common mode
input voltage
range
Offset voltage
VCMIN
VOFF
Response time
tRT
Operation
stabilization time
(Note 6-1)
tCMW
Pin/Remarks
IN0+(P11),
IN0(P12),
IN1+(P15),
IN1(P16)
Conditions
Within common mode input
voltage range
 Within common mode input
voltage range
 Input amplitude=100mV
 Overdrive=50mV
Specification
VDD[V]
min.
2.7 to 5.5
VSS
typ.
max.
Unit
VDD
1.5
V
2.7 to 5.5
10
30
mV
2.7 to 5.5
200
600
ns
1.0
s
2.7 to 5.5
Note 6-1: The interval after CMPON is set till the operation gets stabilized.
No.A1335-15/24
LC87F2708A
7. AD Converter Characteristics at VSS1=0V
< 12-bit AD conversion mode at Ta=40 to +85C >
Parameter
Symbol
Resolution
N
Absolute accuracy
ET
Conversion time
tCAD
Analog input
voltage range
Analog port input
current
Pin/Remarks
AN0(P10)
to AN6(P16)
Conditions
Specification
VDD[V]
min.
typ.
3.0 to 5.5
max.
12
unit
bit
(Note7-1)
3.0 to 5.5
16
LSB
 See "Conversion time
calculation method."
 (Note7-2)
4.0 to 5.5
38
104.3
s
3.0 to 5.5
75.8
104.3
3.0 to 5.5
VSS
VDD
V
1
A
VAIN
IAINH
VAIN=VDD
3.0 to 5.5
IAINL
VAIN=VSS
3.0 to 5.5
1
VDD[V]
min.
< 8-bit AD conversion mode at Ta=40 to +85C >
Parameter
Symbol
Resolution
N
Absolute accuracy
ET
Conversion time
tCAD
Analog input
voltage range
Analog port input
current
Pin/Remarks
AN0(P10)
to AN6(P16)
Conditions
Specification
typ.
3.0 to 5.5
max.
8
unit
bit
(Note7-1)
3.0 to 5.5
1.5
LSB
 See "Conversion time
calculation method."
 (Note7-2)
4.0 to 5.5
23.4
64.3
s
3.0 to 5.5
46.7
64.3
3.0 to 5.5
VSS
VDD
V
1
A
VAIN
IAINH
VAIN=VDD
3.0 to 5.5
IAINL
VAIN=VSS
3.0 to 5.5
1
< Conversion time calculation method >
12-bit AD conversion mode: tCAD (conversion time) = ((52/(division ratio)) + 2) (1/3) tCYC
8-bit AD conversion mode: tCAD (conversion time) = ((32/(division ratio)) + 2) (1/3) tCYC
< Recommended Operating Conditions >
High-speed RC
Oscillation
(FmHRC)
40MHz/20MHz
Supply Voltage
Range
(VDD)
System Clock
Division Ratio
(SYSDIV)
Cycle Time
(tCYC)
AD Division
Ratio
(ADDIV)
12-bit AD
8-bit AD
4.0V to 5.5V
1/1
300ns
1/8
41.8s
25.8s
3.0V to 5.5V
1/1
300ns
1/16
83.4s
51.4s
Conversion Time (tCAD)
Note 7-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is measured
when no change occurs in the I/O state of the pins that are adjacent to the analog input channel during AD
conversion processing.
Note 7-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time
the complete digital conversion value against the analog input value is loaded in the result register.
* The conversion time is twice the normal value when one of the following conditions occurs:
- The first AD conversion executed in the 12-bit AD conversion mode after a system reset.
- The first AD conversion executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion
mode.
No.A1335-16/24
LC87F2708A
8. Power-on Reset (POR) Characteristics at Ta=40 to +85C, VSS1=0V
Specification
Parameter
POR release
voltage
Unknown voltage
area
Power startup time
Symbol
Pin/Remarks
Conditions
 Option selected
 See Fig. 6.
(Note 8-1)
PORRL
Option
Selecting
Voltage
min.
typ.
max.
unit
2.87V
2.75
2.87
2.99
V
3.86V
3.73
3.86
3.99
4.35V
4.21
4.35
4.49
0.7
0.95
 See Fig. 6.
(Note 8-2)
Power startup time from
VDD=0V to 2.8V
POUKS
PORIS
100
ms
Note 8-1: The POR release voltage can be selected from three levels when the low-voltage detection feature is deselected.
Note 8-2: There is an unpredictable period before the power-on reset transistor starts to turn on.
9. Low-voltage Detection (LVD) Characteristics at Ta=40 to +85C, VSS1=0V
Specification
Parameter
LVD reset voltage
(Note 9-2)
LVD voltage
hysteresis
Unknown voltage
area
Minimum low
voltage detection
width (response
sensitivity)
Symbol
LVDET
Pin/Remarks
Conditions
 Option selected
 See Fig. 7.
(Note 9-1)
(Note 9-3)
LVHYS
LVUKS
tLVDW
 See Fig. 7.
(Note 9-4)
 LVDET-0.5V
 See Fig. 8.
Option
Selecting
Voltage
min.
typ.
max.
unit
2.81V
2.71
2.81
2.91
V
3.79V
3.69
3.79
3.89
4.28V
4.18
4.28
4.38
2.81V
60
3.79V
65
4.28V
65
0.7
0.2
mV
0.95
V
ms
Note 9-1: The LVD reset voltage can be selected from three levels when the low-voltage detection feature is selected.
Note 9-2: The hysteresis voltage is not included in the LVD reset voltage value.
Note 9-3: There are cases when the LVD reset voltage value is exceeded when a greater change in the output level or
large current is applied to the port.
Note 9-4: There is an unpredictable period before the low-voltage detection resetting transistor starts to run.
No.A1335-17/24
LC87F2708A
10. Consumption Current Characteristics at Ta=40 to +85C, VSS1=0V
Parameter
Normal mode
consumption
current
(Note 10-1)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
HALT mode
consumption
current
(Note 10-1)
IDDHALT(1)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
HOLD mode
consumption
current
(Note 10-1)
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
IDDHOLD(4)
IDDHOLD(5)
IDDHOLD(6)
IDDHOLD(7)
IDDHOLD(8)
IDDHOLD(9)
IDDHOLD(10)
IDDHOLD(11)
IDDHOLD(12)
IDDHOLD(13)
IDDHOLD(14)
Pin/Remarks
VDD1
Conditions
 FmHRC=40MHz oscillation mode
 System clock set to high-speed RC,
10MHz (1/4 of 40MHz)
 Medium-speed RC oscillation stopped
 System clock frequency division ratio
set to 1/1
 FmHRC=20MHz oscillation mode
 System clock set to high-speed RC,
10MHz (1/2 of 20MHz)
 Medium-speed RC oscillation stopped
 System clock frequency division ratio
set to 1/1
 High-speed RC oscillation stopped
 System clock set to medium-speed RC
oscillation mode
 System clock frequency division ratio
set to 1/2
HALT mode
 FmHRC=40MHz oscillation mode
 System clock set to high-speed RC,
10MHz(1/4 of 40MHz)
 Medium-speed RC oscillation stopped
 System clock frequency division ratio
set to 1/1
HALT mode
 FmHRC=20MHz oscillation mode
 System clock set to high-speed RC,
10MHz (1/2 of 20MHz)
 Medium-speed RC oscillation stopped
 System clock frequency division ratio
set to 1/1
HALT mode
 High-speed RC oscillation stopped
 System clock set to medium-speed RC
oscillation mode
 System clock frequency division ratio
set to 1/2
HOLD mode
 Ta=10 to +50C
Specification
VDD[V]
min.
typ.
max.
unit
4.5 to 5.5
7.8
14
mA
2.7 to 3.6
4.9
9.4
4.5 to 5.5
7.1
12.8
2.7 to 3.6
4.5
8.6
4.5 to 5.5
0.60
1.9
2.7 to 3.6
0.38
1.3
4.5 to 5.5
3.2
5.0
2.7 to 3.6
2.0
3.1
4.5 to 5.5
2.5
3.9
2.7 to 3.6
1.6
2.5
4.5 to 5.5
0.32
1.0
2.7 to 3.6
0.16
0.55
4.5 to 5.5
0.04
3.0
2.7 to 3.6
0.02
1.8
HOLD mode
 Ta=40 to +85C
4.5 to 5.5
0.04
34
2.7 to 3.6
0.02
22
HOLD mode
 LVD option selected
 Ta=10 to +50C
HOLD mode
 LVD option selected
 Ta=40 to +85C
HOLD mode
 Watchdog timer active
 Ta=10 to +50C
HOLD mode
 Watchdog timer active
 Ta=40 to +85C
HOLD mode
 Comparator active
(IN+=VDD, IN=VSS)
4.5 to 5.5
3.1
6.8
2.7 to 3.6
2.4
4.2
4.5 to 5.5
3.1
39
2.7 to 3.6
2.4
25
4.5 to 5.5
3.4
10
2.7 to 3.6
1.7
6.0
4.5 to 5.5
3.4
42
2.7 to 3.6
1.7
27
4.5 to 5.5
110
160
2.7 to 3.6
65
100
A
Note 10-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A1335-18/24
LC87F2708A
11. F-ROM Programming Characteristics at Ta=+10 to +55C, VSS1=0V
Parameter
Onboard
programming
current
Programming
time
Symbol
Pin/Remarks
IDDFW
Conditions
 Microcontroller
consumption current is
excluded.
 Erase operation
 Programming operation
VDD1
tFW(1)
tFW(2)
VDD[V]
min.
Specification
typ.
max.
unit
3.0 to 5.5
5
10
mA
3.0 to 5.5
20
40
30
60
ms
s
12. Power Pin Treatment Recommendations (VDD1, VSS1)
Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins:
 Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible
heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors
are as equal as possible (L1=L1', L2=L2').
 Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should be approximately 0.1F.
L2
L1
VSS1
C1
C2
VDD1
L1’
L2’
No.A1335-19/24
LC87F2708A
0.5VDD
Figure 1
AC Timing Measurement Point
VDD
Operating VDD
lower limit
0V
Power
Reset time
RES#
Medium-speed
RC oscillation
tmsHRC
High-speed
RC oscillation
Operating mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD/HALT
No HOLD release signal
release signal
HOLD release
signal valid
HALT release signal valid
Medium-speed
RC oscillation
tmsHRC
High-speed
RC oscillation
State
HOLD
HALT
Instruction execution
HOLD Release Signal and Oscillation Stabilization Time
Figure 2 Oscillation Stabilization Times
No.A1335-20/24
LC87F2708A
VDD
Note:
RRES
The external peripheral circuit differs depending on the way
in which the power-on reset and low-voltage detection reset
RES#
functions are used. Refer to the Chapter, entitled "Reset
Function," of the user's manual.
CRES
Figure 3
Sample Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 4 Serial I/O Waveforms
tPIL
tPIH
Figure 5 Pulse Input Timing Signal Waveform
No.A1335-21/24
LC87F2708A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
Reset period
100s or longer
Reset unknown area
(POUKS)
RES#
Figure 6
Example of POR Only (LVD Deselected) Mode Waveforms
(at Reset Pin with RRES Pull-up Resistor Only)
 The POR circuit generates a reset signal only when the power voltage is raised from the VSS level.
 No stable reset signal is generated if power is turned on again when the power voltage does not go
down to the VSS level as shown in (a). If this case is anticipated, use the LVD function as explained
below or configure an external reset circuit.
 A reset is effected only when power is turned on again after the power voltage goes down to and
remains at the VSS level for 100s or longer as shown in (b).
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
LVD voltage
(LVDET)
Reset period
Reset period
Reset period
Reset unknown area
(LVUKS)
RES#
Figure 7
Example of POR + LVD Mode Waveforms
(at Reset Pin with RRES Pull-up Resistor Only)
 A reset is effected both when power is turned on and when it goes down.
 The hysteresis width (LVHYS) is introduced in the LVD circuit to prevent the iterations of the IC
entering and exiting the reset state near the detection threshold level.
No.A1335-22/24
LC87F2708A
VDD
LVD release voltage
LVD voltage
LVDET-0.5V
tLVDW
VSS
Figure 8
Minimum Low Voltage Detection Width
(Example of Short Interruption of Power/ Power Fluctuation Waveform)
No.A1335-23/24
LC87F2708A
ORDERING INFORMATION
Device
LC87F2708AUMD-AH
Package
MFP14S(225mil)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
1000 / Tape & Reel
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and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
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directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
PS No.A1335-24/24
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