ENA1935 D

Ordering number : ENA1935
LC87F2C64A
CMOS IC
64K-byte FROM and 2048-byte RAM integrated
8-bit 1-chip Microcontroller
http://onsemi.com
Overview
The LC87F2C64A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard
programmable), 2048-byte RAM, an on-chip debugger, sophisticated 16-bit timer/counter (may be divided into 8-bit
timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a calendar function (RTC), High-speed clock counter, a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO interface, two channels of UART interface
(full duplex), four 12bit-PWMs, a 12/8-bit 16-channel AD converter, a system clock frequency divider, an internal
reset function and a 28-source 10-vector interrupt feature.
Features
Flash ROM
• On-board-programmable with wide range (3.0 to 5.5V) of voltage source
• Block-erasable in 128 byte units
• Writable in 2-byte units
• 65536 × 8 bits
RAM
• 2048 × 9 bits
Minimum Bus Cycle
• 83.3ns (12MHz at VDD=3.0V to 5.5V)
• 250ns (4MHz at VDD=2.4V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.0.21
O1911HKIM 20100216-S00003 No.A1935-1/28
LC87F2C64A
Minimum Instruction Cycle Time
• 250ns (12MHz at VDD=3.0 to 5.5V)
• 750ns (4MHz at VDD=2.4 to 5.5V)
Temperature Range
• -30 to +70 degree Celsius
Ports
• Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units
• Normal withstand voltage input port (Oscillator)
• Reset pin
• Power pins
71 (P0n, P1n, P2n, P30 to P34, P70 to P73, P8n, PAn,
PBn, PCn, Pen, XT2, CF2)
2 (XT1, CF1)
1 (RES)
6 (VSS1 to VSS3, VDD1 to VDD3)
Timers
• Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with a 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler
(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from
the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as
PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer
1) The clock is selectable from the sub-clock (32.768kHz crystal oscillation/slow RC oscillation), system clock, and
prescaler output from timer 0.
2) Interrupts are programmable in 5 different time schemes.
• Real time clock (RTC)
1) Used with a base timer, it can be used as a century + year + month + day + hour + minute + second counter.
2) Calendar counts up to December 31, 2799 with automatic leap-year calculation.
High-speed Clock Counter
• Count clocks with a maximum clock rate of 24MHz (when main clock is 12MHz)
• Real-time output
No.A1935-2/28
LC87F2C64A
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baud rate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
4) HOLD/X’tal HOLD mode release function by receiving 1-byte (8-bit clock)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baud rates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 TCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
Remote Control Receiver Circuit
• Noise rejection function on P73/INT3/T0IN pin (noise rejection filter’s time constant can be selected from 1,
32 or 128 tCYC.)
AD Converter: 12 bits × 16 channels
• 12 bits/8 bits AD converter resolution selectable
PWM: 4 channels
• Multi frequency 12-bit PWM
Clock Output Function
• Output clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 or 1/64 of the source clock of the system clock.
• Output clock of the sub-clock.
Buzzer Output
• 2kHz or 4kHz buzzer output can be generated using base timer.
Watchdog Timer
• Watchdog timer can generate interrupt or system reset.
• Two types of watchdog timers are available:
(1) External RC watchdog timer
(2) Base timer watchdog timer
• Watchdog timer with base timer can select only one period (1, 2, 4 or 8s) by the user option.
Once set the watchdog timer period and start the watchdog timer, the period is not changeable.
No.A1935-3/28
LC87F2C64A
Interrupts
• 28 sources, 10 vector addresses
(1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
(2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/INT4/T0L
4
0001BH
H or L
INT3/INT5/Base timer0/ Base timer1/RTC
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive/UART2 receive
8
0003BH
H or L
SIO1/UART1 transmit/UART2 transmit
9
00043H
H or L
ADC/T6/T7/PWM4, 5/SPI
10
0004BH
H or L
Port0/T4/T5/PWM0, 1
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
(1) Shows a list of interrupt source flags that caused a branching to a particular vector address
(shown in the table above).
Subroutine Stack Levels
• 1024 levels (Stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16 bits×8 bits
(5 tCYC execution time)
• 24 bits×16 bits
(12 tCYC execution time)
• 16 bits÷8 bits
(8 tCYC execution time)
• 24 bits÷16 bits
(12 tCYC execution time)
Oscillation Circuits
• On-chip fast RC oscillation circuit
: For system clock
• On-chip slow RC oscillation circuit
: For system clock
• CF oscillation circuit
: For system clock, with built in Rf
• Crystal oscillation circuit
: For low-speed system clock
• On-chip Frequency variable RC oscillation circuit
: For system clock
(1) Adjustable by ±4% (typical) step from selected center frequency
(2) Frequency measurable by referencing input signal from XT1
System Clock Divider Function
• Enables low power consumption operation
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and 64μs
(at a main clock rate of 12MHz).
Internal Reset Function
• Power-on reset (POR) function
(1) POR reset is generated only at power-on.
(2) The POR release level can be selected through option configuration.
• Low-voltage detection reset (LVD) function
(1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
(2) The use/no-use of the LVD function and the low voltage threshold level can be selected through option
configuration.
No.A1935-4/28
LC87F2C64A
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(1) Oscillation is not halted automatically.
(2) There are three ways of resetting the HALT mode.
1) Setting the reset pin to the lower level
2) System resetting by watchdog timer
3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
(1) The CF, RC, crystal, and frequency variable RC oscillators automatically stop operation.
(2) There are five ways of resetting the HOLD mode.
1) Setting the reset pin to the lower level
2) System resetting by watchdog timer
3) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5 pins to the specified level
4) Having an interrupt source established at port 0
5) Having an interrupt source established in SPI receiving 1-byte (8-bit clock)
• X’'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
(1) The CF, RC, and frequency variable RC oscillators automatically stop operation.
(2) The state of crystal oscillation established when the X’tal HOLD mode is entered is retained.
(3) Power-save mode is available for even lower current consumption.
(4) There are seven ways of resetting the X’tal HOLD mode.
1) Setting the reset pin to the low level
2) System resetting by watchdog timer
3) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5 pins to the specified level
4) Having an interrupt source established at port0
5) Having an interrupt source established in the base timer circuit
6) Having an interrupt source established in the RTC
7) Having an interrupt source established in SPI receiving 1-byte (8-bit clock)
On-chip Debugging Function (flash ROM version)
• Supports software debugging with the test device installed on the target board.
Data Security Function (flash ROM version)
• Protects the program data stored in flash memory from unauthorized read or copy.
Note: The data security function does not necessarily provide an absolute data security.
Shipping form
• QFP80 (14×14): Lead-free type
• TQFP80J (12×12): Lead-free type
Development Tools
• On-chip-debugger: TCB87 TypeB + LC87F2C64A
No.A1935-5/28
LC87F2C64A
Package Dimensions
unit : mm (typ)
3255
17.2
0.8
14.0
60
41
40
80
21
14.0
17.2
61
1
20
0.25
0.65
0.15
(2.7)
0.1
3.0max
(0.83)
SANYO : QFP80(14X14)
Package Dimensions
unit : mm (typ)
3290
14.0
0.5
12.0
41
40
80
21
12.0
61
1
20
0.5
0.2
14.0
60
0.125
0.1
1.2max
(1.0)
(1.25)
SANYO : TQFP80J(12X12)
No.A1935-6/28
P03/URX2
P04
P05/CKO
P06/T6O
P07/T7O
VSS3
VDD3
PA0/PWM0
PA1/PWM0
PA2/PWM0
PA3/PWM0
PA4/PWM1
PA5/PWM1
PA6/PWM1
PA7/PWM1
P30/PWM4
P31/PWM5
P32/DBGP0
P33/DBGP1
P34/DBGP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P70/INT0/T0LCP
P71/INT1/T0HCP
P72/INT2/T0IN/NKIN
P73/INT3/T0IN
RES
XT1
XT2
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
PB0/AN8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P02/UTX2
P01/URX1
P00/UTX1
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P27/INT5/T1IN/T0LCP/T0HCP
P26/INT5/T1IN/T0LCP/T0HCP
P25/INT5/T1IN/T0LCP/T0HCP
P24/INT5/T1IN/T0LCP/T0HCP
P23/INT4/T1IN/T0LCP/T0HCP
P22/INT4/T1IN/T0LCP/T0HCP
P21/INT4/T1IN/T0LCP/T0HCP
P20/INT4/T1IN/T0LCP/T0HCP
PE3
LC87F2C64A
Pin Assignment
LC87F2C64A
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS2
VDD2
PE2
PE1
PE0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7/AN15
PB6/AN14
PB5/AN13
PB4/AN12
PB3/AN11
PB2/AN10
PB1/AN9
Top view
QFP80 (14×14) “Lead-free type”
TQFP80J (12×12) “Lead-free type”
No.A1935-7/28
LC87F2C64A
System Block Diagram
Interrupt Control
IR
Stand-by Control
PLA
Flash ROM
RC × 2
VMRC
Clock
Generator
CF
PC
X’tal
RES
Reset Circuit
(POR/LVD)
Reset Control
WDT
ACC
B Register
SIO0
Bus Interface
SIO1
Port 0
UART1
Port 1
UART2
Port 2
C Register
ALU
PSW
Timer 0
(High-speed clock counter)
Port 3
RAR
Timer 1
Port 7
Timer 4
Port 8
Timer 5
ADC
Timer 6
INT0 to 5
Noise rejection filter
RAM
Stack Pointer
Watchdog Timer
Timer 7
Port A
Base Timer
Port B
RTC
Port C
On-Chip-Debugger
PWM0/1
Port E
PWM4/5
No.A1935-8/28
LC87F2C64A
Pin Description
Pin Name
I/O
Description
Option
VSS1 to VSS3
-
- Power supply pin
No
VDD1 to VDD3
-
+ Power supply pin
No
V1
-
Open
No
VDC
-
Open
No
CUP1, CUP2
-
Open
No
• 8-bit I/O port
Yes
PORT 0
I/O
P00 to P07
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
• HOLD release input
• Port 0 interrupt input
Other functions:
P00: UART1 transmit
P01: UART1 receive
P02: UART2 transmit
P03: UART2 receive
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
PORT 1
I/O
P10 to P17
• 8-bit I/O port
Yes
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
Other functions:
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
PORT 2
I/O
P20 to P27
• 8-bit I/O port
Yes
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
Other functions:
P20 to P23: INT4 input/HOLD release input/timer 1 event input
/timer 0L capture input/timer 0H capture input
P24 to P27: INT5 input/HOLD release input/timer 1 event input
/timer 0L capture input/timer 0H capture input
• Interrupt acknowledge type
PORT 3
P30 to P34
I/O
Rising
Falling
INT4
Yes
Yes
INT5
Yes
Yes
Rising &
H level
L level
Yes
No
No
Yes
No
No
Falling
• 5-bit I/O port
Yes
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
Other functions:
P30: PWM4 output
P31: PWM5 output
P32 (DBGP0) to P34 (DBGP2): On-chip-debugger port (Only on Flash version)
Continued on next page.
No.A1935-9/28
LC87F2C64A
Continued from preceding page.
Pin Name
PORT 7
I/O
I/O
P70 to P73
Description
Option
• 4-bit I/O port
No
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
Other functions:
P70: INT0 input/HOLD release input/timer 0L capture input
/watchdog timer output
P71: INT1 input/HOLD release input/timer 0H capture input
P72: INT2 input/HOLD release input/timer 0 event input
/timer 0L capture input/high speed clock counter input
P73: INT3 input (with noise filter)/ HOLD release input
/timer 0 event input/timer 0H capture input
• Interrupt acknowledge type
PORT 8
I/O
P80 to P87
Rising
Falling
INT0
Yes
Yes
INT1
Yes
Yes
INT2
Yes
INT3
Yes
Rising &
H level
L level
No
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
Falling
• 8-bit I/O port
No
• I/O specifiable in 1 bit units
Other functions:
P80 to P87(AN0 to AN7): AD converter input
PORT A
I/O
PA0 to PA7
• 8-bit I/O port
Yes
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
Other functions:
PA0 to PA3: PWM0 output
PA4 to PA7: PWM1 output
PORT B
I/O
PB0 to PB7
• 8-bit I/O port
Yes
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
Other functions:
PB0 to PB7 (AN8 to AN15): AD converter input
PORT C
I/O
PC0 to PC7
• 8-bit I/O port
Yes
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
PORT E
I/O
PE0 to PE3
• 4-bit I/O port
Yes
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
RES
I/O
XT1
I
External reset input pin/Internal reset output pin
No
• Input for 32.768kHz crystal oscillation
No
Other functions:
• General purpose input port
*Connect to VDD1 when the port is not used.
XT2
I/O
• Output for 32.768kHz crystal oscillation
No
Other functions:
• General-purpose I/O port
*Must be set for oscillation mode and kept open if not to be used.
CF1
I
• Input for ceramic resonator
No
Other functions:
• General purpose input port
*Connect to VDD1 when the port is not used.
CF2
I/O
• Output for ceramic resonator
No
Other functions:
• General-purpose I/O port
*Must be set for oscillation mode and kept open if not to be used.
No.A1935-10/28
LC87F2C64A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up/down resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option Selected
iIn Units of
P00 to P07
Option Type
1
1bit
P10 to P17
CMOS
Programmable
Programmable
2
Nch-open drain
CMOS
Programmable
Programmable
2
Nch-open drain
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
1bit
P30 to P34
Pull-Up Resistor
1
1bit
P20 to P27
Output Type
1bit
2
Nch-open drain
Programmable
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
P80 to P87
-
No
Nch-open drain
No
PA0 to PA7
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
Programmable
1bit
PB0 to PC7
1bit
PC0 to PC7
2
Nch-open drain
1
CMOS
Programmable
Programmable
1bit
PE0 to PE3
2
Nch-open drain
1
CMOS
Programmable
2
Nch-open drain
Programmable
32.768kHz crystal oscillator output or
No
1bit
XT2
CF2
-
No
-
No
Nch-open drain when selected as normal port
Ceramic resonator output or
No
Nch-open drain when selected as normal port
No.A1935-11/28
LC87F2C64A
User Option Table
Option Name
Port output type
Option to be
Mask-ROM
Flash-ROM
Option Selected in
Applied on
Version*1
Version
Units of
Yes
Yes
1 bit
P00 to P07
Option Selection
CMOS
Nch-open drain
P10 to P17
CMOS
Yes
Yes
1 bit
Nch-open drain
P20 to P27
CMOS
Yes
Yes
1 bit
Nch-open drain
P30 to P34
CMOS
Yes
Yes
1 bit
Nch-open drain
PA0 to PA7
CMOS
Yes
Yes
1 bit
Nch-open drain
PB0 to PB7
CMOS
Yes
Yes
1 bit
Nch-open drain
PC0 to PC7
CMOS
Yes
Yes
1 bit
Nch-open drain
PE0 to PE3
CMOS
Yes
Yes
1 bit
Nch-open drain
Program start
-
Base timer Watchdog
timer
0000H
No*2
address
Yes
FE00H
Watchdog timer
1s
period
2s
Yes
Yes
4s
8s
Low-Voltage
detect function
Detection level
(Enable)
-
Yes
-
-
Yes
-
Power-on reset level
(Disable)
*1: The option selection cannot to be changed after the mask is created.
*2: Program start address for the mask-ROM version is 0000H.
No.A1935-12/28
LC87F2C64A
*Note1: Connect the IC as shown below to minimize the noise input to the VDD1. Be sure to electrically short the
VSS1, VSS2 and VSS3 pins.
*Note2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output
at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and
thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup
mode.
Example of power connection when power-save mode is used
LSI
VDD1
Power
Supply
Back-up capacitors
VDD2
VDD3
VSS1
VSS2 VSS3
No.A1935-13/28
LC87F2C64A
Absolute Maximum Ratings at Ta=25°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pin/Remarks
Maximum supply voltage
VDD max
VDD1, VDD2, VDD3
Input voltage
VI
XT1, CF1, RES
Input/output voltage
VIO
Ports 0, 1, 2, 3, 7, 8,
Conditions
• VDD1=VDD2=VDD3
A, B, C, E, XT2, CF2
Peak output
Ports 0, 1, 2, 3, A, B,
• CMOS output select
C, E
• Per 1 applicable pin
IOPH(2)
P71, P72, P73
• Per 1 applicable pin
IOMH(1)
Ports 0, 1, 2, 3, A, B,
• CMOS output select
C, E
• Per 1 applicable pin
IOPH(1)
current
Mean output
High level output current
current
Specification
VDD[V]
min
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
-7.5
P71, P72, P73
• Per 1 applicable pin
IOAH(1)
Port 0, P14 to P17
• Total of all applicable pins
-25
current
IOAH(2)
Port 3, A
• Total of all applicable pins
-25
IOAH(3)
Port 0, 3, A
• Total of all applicable pins
• Total of all applicable pins
P10 to P13,PE3
IOAH(5)
Port B, C,
• Total of all applicable pins
PE0 to PE2
IOAH(6)
Port 2, B, C, E
• Total of all applicable pins
P10 to P13
IOAH(7)
P71, P72, P73
• Total of all applicable pins
Peak output
IOPL(1)
Ports 0, 1, 2, 3, A, B, C, E
• Per 1 applicable pin
current
IOPL(2)
Port 7, 8
• Per 1 applicable pin
Mean output
IOML(1)
Ports 0, 1, 2, 3, A, B, C, E
• Per 1 applicable pin
current
IOML(2)
Port 7, 8
• Per 1 applicable pin
-3
-45
-25
-25
-45
-5
20
Low level output current
15
7.5
XT2, CF2
Total output
IOAL(1)
Port 0, P14 to P17
• Total of all applicable pins
45
current
IOAL(2)
Port 3, A
• Total of all applicable pins
45
IOAL(3)
Port 0, 3, A
• Total of all applicable pins
80
P14 to P17
IOAL(4)
Port 2
• Total of all applicable pins
45
P10 to P13, PE3
IOAL(5)
Port B, C,
• Total of all applicable pins
45
PE0 to PE2
IOAL(6)
Port 2, B, C,E
• Total of all applicable pins
80
P10 to P13
Power dissipation
mA
10
XT2, CF2
(Note 1-1)
V
-5
IOMH(2)
Port 2
unit
-10
Total output
IOAH(4)
max
-0.3
(Note 1-1)
P14 to P17
typ
IOAL(7)
Port 7, XT2
• Total of all applicable pins
15
IOAL(8)
Port 8, CF2
• Total of all applicable pins
15
IOAL(9)
Port 7, 8, XT2, CF2
• Total of all applicable pins
20
Pd max(1)
QFP80
• Ta=-30 to +70°C
T.B.D
• Package only
• Ta=-30 to +70°C
• Package with thermal
T.B.D
resistance board
(Note 1-2)
Pd max(2)
TQFP80J
mW
• Ta=-30 to +70°C
T.B.D
• Package only
• Ta=-30 to +70°C
• Package with thermal
T.B.D
resistance board
(Note 1-2)
Operating ambient
Topr
temperature
Storage ambient
temperature
Tstg
-30
+70
-55
+125
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1935-14/28
LC87F2C64A
Allowable Operating Conditions at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Operating supply
voltage (Note 2-1)
Memory sustaining
VDD(1)
VDD(2)
VHD
VIH(1)
max
unit
• 0.245μs≤tCYC≤200μs
3.0
5.5
• 0.735μs≤tCYC≤200μs
2.4
5.5
VDD1
• RAM and register contents
2.2
5.5
sustained in HOLD mode.
voltage
typ
VDD1=VDD2
=VDD3
supply voltage
High level input
min
Ports 0, 1, 2, 3, 8,
• Output disabled
A, B, C, E,
P71, P72, P73
2.4 to 5.5
0.3VDD
2.4 to 5.5
0.9VDD
VDD
2.4 to 5.5
0.75VDD
VDD
2.4 to 5.5
VSS
2.4 to 5.5
VSS
2.4 to 5.5
VSS
P70 port input
VDD
+0.7
/interrupt side
VIH(2)
Port 70 watchdog
• Output disabled
timer side
VIH(3)
Low level input
VIL(1)
voltage
XT1, XT2, CF1,
CF2, RES
Ports 0, 1, 2, 3, 8,
V
• Output disabled
A, B, C, E,
P71, P72, P73
0.1VDD
+0.4
P70 port input
/interrupt side
VIL(2)
Port 70 watchdog
• Output disabled
timer side
VIL(3)
Instruction cycle
tCYC
time (Note 2-1)
(Note 2-2)
External system
FEXCF
XT1, XT2, CF1,
CF2, RES
CF1
-1.0
0.25VDD
3.0 to 5.5
0.245
200
2.4 to 5.5
0.735
200
3.0 to 5.5
0.1
12
2.4 to 5.5
0.1
4
μs
• CF2 pin open
• System clock frequency
clock frequency
0.8VDD
division ratio = 1/1
• External system clock duty
= 50±5%
MHz
• CF2 pin open
• System clock frequency
3.0 to 5.5
0.2
24
2.4 to 5.5
0.2
8
division ratio = 1/2
• External system clock duty
= 50±5%
Oscillation
FmCF(1)
CF1, CF2
(Note 2-3)
• 12MHz ceramic oscillation
• See Fig. 1.
frequency range
FmCF(2)
CF1, CF2
• 4MHz ceramic oscillation
• See Fig. 1.
3.0 to 5.5
12
2.4 to 5.5
4
3.0 to 5.5
10
2.4 to 5.5
4
• Frequency variable RC
FmVMRC(1)
source oscillation
• VMRAJ2 to 0 = 4
• VMFAJ2 to 0 = 0
MHz
• VMSL4M = 0
FmVMRC(2)
• Frequency variable RC
source oscillation
• VMRAJ2 to 0 = 4
• VMFAJ2 to 0 = 0
• VMSL4M=1
FmRC
• Internal fast RC oscillation
2.4 to 5.5
500
FsRC
• Internal slow RC oscillation
2.4 to 5.5
50
2.4 to 5.5
32.768
FsX’tal
XT1, XT2
• 32.768kHz crystal oscillation
• See Fig. 2.
kHz
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Table 1, 2 for the oscillation constants
Continued on next page.
No.A1935-15/28
LC87F2C64A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
OpVMRC(1)
• VMSL4M=0
usable range
OpVMRC(2)
• VMSL4M=1
Frequency variable
VmADJ(1)
• 1 step of VMRAJn
Frequency variable
RC oscillation
RC oscillation
adjustment range
(large range)
• 1 step of VMFAJn
VmADJ(2)
(small range)
min
typ
max
unit
3.0 to 5.5
8
10
12
2.4 to 5.5
3.5
4
4.5
2.4 to 5.5
8
24
64
2.4 to 5.5
1
4
8
MHz
%
Electrical Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2, 3,
• Output disabled
7, 8, A, B, C, E
• Pull-up resistor off
• VIN=VDD
min
typ
max
unit
2.4 to 5.5
1
2.4 to 5.5
1
(Including output Tr's off
leakage current)
Low level input
IIH(3)
RES
• VIN=VDD
IIH(4)
XT1, XT2
• Configured as input ports
CF1, CF2
• VIN=VDD
2.4 to 5.5
1
IIH(5)
CF1
• VIN=VDD
2.4 to 5.5
15
IIL(1)
Ports 0, 1, 2, 3,
• Output disabled
7, 8, A, B, C, E
• Pull-up resistor off
current
• VIN=VSS
2.4 to 5.5
-1
2.4 to 5.5
-1
-1
μA
(Including output Tr's off
leakage current)
IIL(2)
RES
• VIN=VSS
IIL(3)
XT1, XT2
• Configured as input ports
CF1, CF2
• VIN=VSS
2.4 to 5.5
IIL(4)
CF1
• VIN=VSS
2.4 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2, 3,
• IOH=-1.0mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
A, B, C
• IOH=-0.4mA
3.0 to 5.5
VDD-0.4
• IOH=-0.2mA
2.4 to 5.5
VDD-0.4
• IOH=-0.4mA
3.0 to 5.5
VDD-0.4
• IOH=-0.2mA
2.4 to 5.5
VDD-0.4
VOH(3)
VOH(4)
P71, P72, P73
VOH(5)
VOH(6)
P30, P31, Port A
• IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(7)
(using as PWM)
• IOH=-1.6mA
3.0 to 5.5
VDD-0.4
• IOH=-1.0mA
2.4 to 5.5
VDD-0.4
VOH(8)
Low level output
voltage
VOL(1)
Ports 0, 1, 2, 3,
• IOL=10mA
4.5 to 5.5
1.5
VOL(2)
A, B, C, E
• IOL=1.6mA
3.0 to 5.5
0.4
• IOL=1.0mA
2.4 to 5.5
0.4
0.4
VOL(3)
Pull-up resistance
VOL(4)
Port 7, 8
• IOL=1.6mA
3.0 to 5.5
VOL(5)
XT2, CF2
• IOL=1.0mA
2.4 to 5.5
Rpu
Ports 0, 1, 2, 3,
• VOH=0.9VDD
4.5 to 5.5
15
40
70
2.4 to 4.5
25
70
150
7, A, B, C, E
Hysteresis voltage
VHYS
Ports 0, 1, 2, 3,
7, A, RES
Pin capacitance
V
CP
All pins
0.4
kΩ
2.4 to 5.5
0.1VDD
V
2.4 to 5.5
10
pF
• f=1MHz
• Ta=25°C
• For pins other than that
under test: VIN=VSS
No.A1935-16/28
LC87F2C64A
Serial I/O Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
• See Fig. 6.
Input clock
tSCKH(1)
pulse width
tSCKHA(1)
typ
max
unit
2
1
pulse width
High level
min
1
• Continuous data
2.4 to 5.5
tCYC
transmission/reception
mode
4
Serial clock
• See Fig. 6.
Output clock
(Note 4-1-2)
Frequency
tSCK(2)
Low level
tSCKL(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
1/2
pulse width
High level
tSCKH(2)
pulse width
tSCKHA(2)
1/2
• Continuous data
2.4 to 5.5
tSCK
transmission/reception
tSCKH(2)
mode
+2tCYC
• CMOS output selected
tSCKH(2)
+(10/3)
tCYC
• See Fig. 6.
input
Serial
Data setup time
tsDI
SB0(P11),
SI0(P11)
Data hold time
• Must be specified with
respect to rising edge
of SIOCLK.
thDI
0.03
2.4 to 5.5
0.03
• See Fig. 6.
Output delay
tdD0(1)
Input clock
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception
(1/3)tCYC
mode
+0.05
(Note 4-1-3)
tdD0(2)
mode
tdD0(3)
μs
• Synchronous 8-bit
(Note 4-1-3)
Output clock
Serial output
time
1tCYC
2.4 to 5.5
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: When using serial clock input under continuous data transmission/reception mode, the time from SI0RUN
is set while serial clock is “H” to the first falling edge of serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A1935-17/28
LC87F2C64A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
• See Fig. 6.
min
2.4 to 5.5
tSCK(4)
Low level
tSCKL(4)
1
SCK1(P15)
• CMOS output
2.4 to 5.5
2
selected
1/2
• See Fig. 6.
pulse width
High level
tSCK
tSCKH(4)
1/2
Serial input
pulse width
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
Data hold time
unit
tCYC
tSCKH(3)
Frequency
max
1
pulse width
High level
typ
2
pulse width
Output clock
Serial clock
VDD[V]
• Must be specified
2.4 to 5.5
with respect to
0.03
rising edge of
thDI(2)
SIOCLK.
0.03
• See Fig. 6.
Output delay time
tdD0(4)
SO1(P13),
• Must be specified
SB1(P14)
with respect to
2.4 to 5.5
falling edge of
μs
Serial output
SIOCLK.
• Must be specified
(1/3)tCYC
as the time to the
+0.05
beginning of
output state
change in open
drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70)
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71)
• Event inputs for timer 0 or 1 are
INT2(P72)
enabled.
INT3(P73)
min
typ
2.4 to 5.5
1
2.4 to 5.5
2
max
unit
INT4(P20 to P23)
INT5(P24 to P27)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
constant is 1/1
enabled.
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
constant is 1/32
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
tPIH(5)
NKIN(P72)
tPIL(5)
tPIL(6)
64
2.4 to 5.5
256
2.4 to 5.5
1/12
2.4 to 5.5
200
enabled.
• High speed clock counter
countable
RES
2.4 to 5.5
enabled.
tPIH(4)
constant is 1/128
tCYC
• External reset input mode
• Resetting is enabled
μs
No.A1935-18/28
LC87F2C64A
AD Converter Characteristics at VSS1=VSS2=VSS3=0V
<12bits AD Converter Mode / Ta=-30 to +70°C>
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
min
typ
max
unit
Resolution
N
AN0(P80) to
Absolute accuracy
ET
AN7(P87)
(Note 6-1)
3.0 to 5.5
Conversion time
tCAD
AN8(PB0) to
• See Conversion time calculation
4.0 to 5.5
32
115
3.0 to 5.5
64
115
3.0 to 5.5
VSS
VDD
3.0 to 5.5
AN15(PB7)
bit
±16
LSB
μs
formulas.
(Note 6-2)
Analog input voltage
12
VAIN
range
Analog port input
IAINH
• VAIN=VDD
3.0 to 5.5
current
IAINL
• VAIN=VSS
3.0 to 5.5
V
1
µA
-1
<8bits AD Converter Mode / Ta=-30 to +70°C>
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
min
typ
max
unit
Resolution
N
AN0(P80) to
Absolute accuracy
ET
AN7(P87)
(Note 6-1)
3.0 to 5.5
Conversion time
tCAD
AN8(PB0) to
• See Conversion time calculation
4.0 to 5.5
20
95
3.0 to 5.5
40
95
3.0 to 5.5
VSS
VDD
AN15(PB7)
3.0 to 5.5
bit
±1.5
LSB
μs
formulas.
(Note 6-2)
Analog input voltage
8
VAIN
range
Analog port input
IAINH
• VAIN=VDD
3.0 to 5.5
current
IAINL
• VAIN=VSS
3.0 to 5.5
1
-1
V
μA
Conversion time calculation formulas:
12bits AD Converter Mode : TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode : TCAD(Conversion time) = ((32/(AD division ratio))+2)×(1/3)×tCYC
External
Operating supply
oscillation
voltage range
(FmCF)
(VDD)
System division ratio
Cycle time
(SYSDIV)
(tCYC)
AD division
AD conversion time
(TCAD)
ratio
(ADDIV)
12bit AD
8bit AD
4.0V to 5.5V
1/1
250ns
1/8
34.8μs
21.5μs
3.0V to 5.5V
1/1
250ns
1/16
69.5μs
42.8μs
3.0V to 5.5V
1/1
750ns
1/8
104.5μs
64.5μs
CF-12MHz
CF-4MHz
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion
mode.
No.A1935-19/28
LC87F2C64A
Power-on Reset (POR) Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected voltage
POR release
PORRL
voltage
Detection voltage
typ
• Select from option.
1.67V
1.67
(Note 7-1)
1.97V
1.97
2.07V
2.07
2.37V
2.37
2.57V
2.57
2.87V
2.87
3.86V
3.86
4.35V
4.35
• See Fig. 8.
POUKS
unknown state
Power supply rise
min
0.7
(Note 7-2)
max
V
0.95
• Power supply rise time
PORIS
time
unit
100
from 0V to x V.
ms
Note7-1: The POR release level can be selected out of 7 levels only when the LVD reset function is disabled.
Note7-2: POR is in an unknown state before transistors start operation.
Low Voltage Detection Reset (LVD) Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected voltage
min
typ
max
• Select from option.
1.91V
1.91
Voltage
(Note 8-1)
2.01V
2.01
(Note 8-2)
(Note 8-3)
2.31V
2.31
2.51V
2.51
2.81V
2.81
3.79V
3.79
4.28V
4.28
1.91V
55
2.01V
55
2.31V
55
2.51V
55
2.81V
60
3.79V
65
4.28V
65
LVD reset
LVDET
• See Fig. 9.
LVD hysteresis width
Detection voltage
LVHYS
LVUKS
unknown state
Low voltage detection
minimum width
• See Fig. 9.
0.7
(Note 8-4)
TLVDW
unit
V
mV
0.95
V
• LVDET-0.5V
• See Fig. 10.
0.2
ms
(Reply sensitivity)
Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled.
Note8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4: LVD is in an unknown state before transistors start operation.
No.A1935-20/28
LC87F2C64A
Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Conditions
VDD[V]
• FmCF=12MHz Ceramic resonator oscillation
consumption
VDD1
=VDD2
during normal
=VDD3
• Frequency variable RC oscillation stopped.
Current
IDDOP(1)
Specification
Pin/
Remarks
• FsX’tal=32.768kHz crystal oscillation
operation
• Internal RC oscillation stopped.
(Note 9-1)
• System clock: CF oscillation 12MHz
min
typ
max
4.5 to 5.5
8.4
22.1
3.0 to 3.6
4.9
12.1
4.5 to 5.5
3.5
10.0
2.4 to 3.6
2.8
6.3
4.5 to 5.5
6.9
16.6
2.4 to 3.6
4.2
101
4.5 to 5.5
2.8
8.5
2.4 to 3.6
2.5
5.4
4.5 to 5.5
400
1000
2.4 to 3.6
300
600
unit
• Divider : 1/1
IDDOP(2)
• FmCF=4MHz Ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: CF oscillation 4MHz
• Divider : 1/1
IDDOP(3)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• FmVMRC=10MHz Frequency variable RC
mA
oscillation
• Internal RC oscillation stopped.
• System clock: Frequency variable RC
oscillation 10MHz
• Divider :1/1
IDDOP(4)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• FmVMRC=4MHz Frequency variable RC
oscillation
• Internal RC oscillation stopped.
• System clock: Frequency variable RC
oscillation 4MHz
• Divider :1/1
IDDOP(5)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation=Fast RC oscillation
• System clock: Fast RC oscillation
• Divider :1/1
IDDOP(6)
μA
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
4.5 to 5.5
74
269.4
2.4 to 3.6
26.1
110.1
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: 32.768kHz
• Divider :1/1
Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Continued on next page.
No.A1935-21/28
LC87F2C64A
Continued from preceding page.
Parameter
Current
Symbol
IDDHALT(1)
Specification
Pin/
Conditions
Remarks
VDD[V]
HALT mode
consumption
VDD1
= VDD2
during HALT
= VDD3
• FsX’tal=32.768kHz crystal oscillation
• FmCF=12MHz Ceramic resonator oscillation
mode
• Frequency variable RC oscillation stopped.
(Note 9-1)
• Internal RC oscillation stopped.
• System clock: CF oscillation 12MHz
min
typ
max
4.5 to 5.5
3.3
8.4
3.0 to 3.6
1.7
4.3
4.5 to 5.5
0.3
4.1
2.4 to 3.6
0.1
1.8
4.5 to 5.5
2.3
5.8
2.4 to 3.6
1.3
3.2
4.5 to 5.5
1.0
2.5
2.4 to 3.6
0.5
1.3
4.5 to 5.5
200
500
2.4 to 3.6
100
200
unit
• Divider : 1/1
IDDHALT(2)
HALT mode
• FmCF=4MHz Ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: CF oscillation 4MHz
• Divider : 1/1
IDDHALT(3)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
mA
• FmVMRC=10MHz Frequency variable RC
oscillation
• Internal RC oscillation stopped.
• System clock: Frequency variable RC
oscillation 10MHz
• Divider :1/1
IDDHALT(4)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• FmVMRC=4MHz Frequency variable RC
oscillation
• Internal RC oscillation stopped.
• System clock: Frequency variable RC
oscillation 4MHz
• Divider :1/1
IDDHALT(5)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation=Fast RC oscillation
• System clock: Fast RC oscillation
• Divider :1/1
IDDHALT(6)
μA
HALT mode
• FmCF=0Hz (No oscillation)
4.5 to 5.5
57.2
230.9
2.4 to 3.6
13.6
83.2
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: 32.768kHz
• Divider :1/1
Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Continued on next page.
No.A1935-22/28
LC87F2C64A
Continued from preceding page
Parameter
Symbol
Current
IDDHOLD(1)
Specification
Pin/
Conditions
Remarks
consumption
VDD1
= VDD2
during HOLD
= VDD3
VDD[V]
min
typ
max
unit
HOLD mode
• CF1=VDD or open
4.5 to 5.5
0.1
52
2.4 to 3.6
0.04
22
4.5 to 5.5
49.9
213
2.4 to 3.6
9.6
73.4
4.5 to 5.5
1.0
94.3
2.4 to 3.6
0.76
39.3
(when using external clock)
mode
(Note 9-1)
Current
IDDHOLD(3)
Date/time clock HOLD mode
consumption
• CF1=VDD or open (when using external clock)
during
• FmX’tal=32.768kHz crystal oscillation
Date/time
• Normal mode
clock HOLD
IDDHOLD(4)
Date/time clock HOLD mode
mode
• CF1=VDD or open (when using external clock)
(Note 9-1)
• FmX’tal=32.768kHz crystal oscillation
• Power save mode
μA
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Onboard
IDDFW
VDD1
min
typ
max
unit
• Current of the Flash module
programming
3.0 to 5.5
5
10
mA
20
30
ms
40
60
μs
current
Programming
tFW(1)
• Erase time
time
tFW(2)
• Program time
3.0 to 5.5
UART (Full Duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Transfer rate
UBR
UTX1(P00), URX1(P01)
UTX2(P02), URX2(P03)
Data length:
Stop bits:
Parity bits:
2.4 to 5.5
min
typ
16/3
max
unit
8192/3
tCYC
7, 8, and 9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit
Start of
transmission
Stop bit
Transmit data (LSB first)
End of
transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
Start bit
Start of
reception
Receive data (LSB first)
End of
reception
UBR
No.A1935-23/28
LC87F2C64A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table1. Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Circuit Constant
Nominal
Vendor Name
Frequency
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rf
Rd
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after
VDD goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table2. Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor Name
Frequency
Circuit Constant
Oscillator
Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rf
Rd
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
Remarks
32.768kHz
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
XT1
CF2
XT2
Rf2
Rf1
Rd2
Rd1
C1
C2
C3
C4
X’tal
CF
Figure 1 Ceramic Oscillation Circuit
Figure 2 Crystal Oscillation Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1935-24/28
LC87F2C64A
VDD
VDD limit
Power supply
0V
Reset time
RES
Internal RC oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operating mode
Unfixed
Reset
Instruction execution
Reset Time and Oscillation Stable Time
HOLD release signal
Without HOLD release signal
HOLD release signal VALID
Internal RC oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operation mode
HOLD
HALT
HOLD Release Signal and Oscillation Stable Time
Figure 4 Oscillation Stabilization Times
No.A1935-25/28
LC87F2C64A
VDD
Note:
External circuits for reset may vary depending on
the usage of POR and LVD. Please refer to the
user’s manual for more information.
RRES
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transmission period
(SIO0)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transmission period
(SIO0)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1935-26/28
LC87F2C64A
(a)
POR release
voltage(PORRL)
(b)
VDD
Reset period
100μs or longer
Reset period
Unknown-state
(POUKS)
RES
Figure 8 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.
LVD release
voltage
(LVDET+LVHYS)
LVD hysteresis width
(LVHYS)
VDD
Reset
period
Reset
period
Reset
period
LVD reset
voltage
(LVDET)
Unknown-state
(LVUKS)
RES
Figure 9 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
No.A1935-27/28
LC87F2C64A
VDD
LVD release
voltage
LVD reset
voltage
LVDET-0.5V
tLVDW
VSS
Figure 10 Low voltage detection minimum width
(Example of momentary power loss/Voltage variation waveform)
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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PS No.A1935-28/28
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