ENA2279 D

Ordering number : EN*A2279
LC87F2L08A
Advance Information
CMOS LSI
8-bit Microcontroller
http://onsemi.com
8K-Byte Flash ROM / 256-Byte RAM / 30-pin
Overview
The LC87F2L08A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM
(On-board-programmable), 256-byte RAM, an On-chip-debugger, two sophisticated 16-bit timers/counters (may be
divided into 8-bit timers), an asynchronous/synchronous SIO interface, a 12/8-bit 9-channel AD converter, four
analog comparator, two AMP circuits, an IGBT control circuit(PPG), a watch dog timer, an internal reset a system
clock frequency divider, and a 19-source 10-vector interrupt feature.
Features
 Flash ROM
 8192  8 bits
 Capable of on-board programming with a power voltage range of 4.5 to 5.5V
 Block-erasable in 128 byte units
 Writing in 2-byte units
 ROM
 256  9 bits
 Package : DIP30SD(400mil), Lead-free type
 Minimum bus cycle time
 83.3ns (12MHz)
Note : The bus cycle time here refers to the ROM read speed.
 Minimum instruction cycle time
 250ns (12MHz)
DIP30SD(400mil)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 30 of this data sheet.
Semiconductor Components Industries, LLC, 2014
July, 2014 Ver. 1.04
71514HK No.A2279-1/30
LC87F2L08A
 Ports
● Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1 bit units
Ports I/O direction can be designated in 4 bit units
● Dedicated PPG ports
9(P14, P15, P20, P21, P30, P70 to P73)
8 (P0n)
7 (PPGO, AMP1I, AMP2O, CMP1IA, CMP1IB,
CMP2I, CMP4I)
2 (CF1/XT1, CF2/XT2)
1 (RES#)
3 (VSS1, VSS2, VDD1)
● Dedicated oscillator ports/input ports
● Reset pin
● Power pins
 Timers
●Timer 0 : 16-bit timer/counter with a capture register.
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3 : 16-bit counter (with a 16-bit capture register)
● Timer 1 : 16-bit timer/counter
Mode 0 : 8-bit timer with an 8-bit prescaler + 8-bit timer/counter with an 8-bit prescaler
Mode 2 : 16-bit timer/counter with an 8-bit prescaler
Mode 3 : 16-bit timer with an 8-bit prescaler
● Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
● Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
● Base timer
1) The clock is selectable from the subclock (32.768 kHz crystal oscillation), system clock, and timer 0
prescaler output.
2) Interrupts are programmable in 5 different time schemes
 High-speed clock counter
● Can count clocks with a maximum clock rate of 20 MHz (at a main clock of 10 MHz).
 SIO
● SIO1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2-wire configuration, 2 to 512 Tcyc transfer clocks)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 Tcyc transfer clocks)
Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)
 UART
● Full duplex
● 7/8/9 bit data bits selectable
● 1 stop bit (2-bit in continuous data transmission)
● Built-in baudrate generator
 AD converter : 12 bits/8 bits  9 channels
● 12/8 bits AD converter resolution selectable
 Remote control receiver circuit (sharing pins with P73, INT3, and T0IN)
● Noise rejection function (noise filter time constant selectable from 1Tcyc/32Tcyc/128Tcyc)
 Clock output function
● Can generate clock outputs with a frequency of 1 ,
1
1
2
,
1
4
,
1
8
,
1
16
,
1
32
,
1
64
of the source clock selected as the system
clock.
● Can generate the source clock for the subclock.
No.A2279-2/30
LC87F2L08A
 Analog comparator  4 channels
● CMP1 : Both input terminals of “+” and “-”.
Output: For timing generation of PPG output and capture timer input(INT2).
● CMP2 : Input terminal of “+”, “-” input is 2/3VDD of internal Vref.
Interrupt flag set of output (INT0).
● CMP 3: “+” input is output of AMP1. “-” input is 2/3VDD of internal Vref.
PPG output control of CMP3 output (OFF only at a present cycle) and interrupt flag set (INT1).
● CMP4 : Input terminal of “+”, “-” input is 2/3VDD of internal Vref.
PPG output control of CMP4 output (compulsion OFF) and interrupt flag set(CMP4).
 AMP circuit  2 channels
● AMP1 : The magnification is set by the user option (6/8/10).
Input terminal (AMP1I)
Output is CMP3 input and AMP2 input.
● AMP2 : The magnification is set by the register (1/2/4).
Input is AMP1 output.
Output rerminal (AMP2O)
 Pulse output control circuit (PPG output)  1 channels
● Output synchronous signal switch : Set by the register (1 pulse output) / Continuous pulse output of
synchronizationto CMP1 output .
● Duty control : The pulse beginning delay time and the pulse end time form synchronous idle are set according to the
register.
● PPG output is compulsion OFF by the CMP3/CMP4 output.
● CMP1 output : Timing detection of pulse signal.
● The output polarity can be switched : User option setting.
Setting at pulse end time
Setting at pulse beginning delay time
 Watchdog timer
● Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed
RC oscillation clock (30kHz).
● Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/
HOLD mode.
No.A2279-3/30
LC87F2L08A
 Interrupts
● 19 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
2
3
4
5
6
7
8
9
10
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
INT2/T0L/INT4
INT3/INT5/base timer
T0H
T1L/T1H
UART1 receive
SIO1/UART1 transmit
ADC/T6/T7
Port 0/CMP4
● Priority levels X > H > L
● Of interrupts of the same level, the one with the smallest vector address takes precedence.
 Subroutine stack levels: 128levels (the stack is allocated in RAM.)
 High-speed multiplication/division instructions
● 16 bits  8 bits
● 24 bits  16 bits
● 16 bits ÷ 8 bits
● 24 bits ÷ 16 bits
(5 Tcyc execution time)
(12 Tcyc execution time)
(8 Tcyc execution time)
(12 Tcyc execution time)
 Oscillation circuits
● Internal oscillation circuits
Low-speed RC oscillation circuit 1
Medium-speed RC oscillation circuit
Multifrequency RC oscillation circuit
Low-speed RC oscillation circuit 2
: For system clock(100kHz)
: For system clock(1MHz)
: For system clock(8MHz)
: For watch dog timer(30kHz)
● External oscillation circuits
Hi-speed CF oscillation circuit
: For system clock, with internal Rf
Low speed crystal oscillation circuit : For low-speed system clock, with internal Rf
1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control.
2) Both the CF and crystal oscillator circuits stop operation on a system reset. When the reset is released, only the
CF oscillation circuit resumes operation.
 System clock divider function
● Can run on low current.
● The minimum instruction cycle selectable from 300 ns, 600 ns, 1.2 μs, 2.4 μs, 4.8 μs, 9.6 μs, 19.2 μs, 38.4 μs, and
76.8 μs (at a main clock rate of 10 MHz).
No.A2279-4/30
LC87F2L08A
 Internal reset function
● Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and
4.35V) through option configuration.
● Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, 4.28V).
 Standby function
● HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
● HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
●X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer or low-voltage detection.
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
Note: Available only when X’tal oscillation is selected.
No.A2279-5/30
LC87F2L08A
 On-chip debugger
● Supports software debugging with the IC mounted on the target board.
 Data security function (flash versions only)
● Protects the program data stored in flash memory from unauthorized read or copy.
Note : This data security function does not necessarily provide absolute data security.
 Development tools
● On-chip-debugger : TCB87 TypeB + LC87F2L08A
 Programming board
Package
Programming board
DIP30SD
W87F2LD
 Flash ROM programmer
Maker
Model
Supported version
Device
AF9708
Single
AF9709/AF9709B/AF9709C
Programmer
(Including Ando Electric Co., Ltd. models)
Rev03.12
LC87F2L08A
Flash
Support
AF9723/AF9723B(Main body)
Group, Inc.
(FSG)
(Including Ando Electric Co., Ltd. models)
*1
Gang
LC87F2L08A
AF9833(Unit)
Programmer
(Including Ando Electric Co., Ltd. models)
*1
Single/Gang
SKK/SKK Type B
Programmer
(SanyoFWS)
ON
Gang
SKK-4G
1.04 or later
Semiconductor
Programmer
(SanyoFWS)
Chip Data Version
In-circuit/Gang
SKK-DBG Type B
Programmer
(SanyoFWS)
Application Version
LC87F2L08
2.18 or later
Note : Check for the latest version.
*1 : We have a schedule to request the registration.
For information about AF-Series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: [email protected]
No.A2279-6/30
LC87F2L08A
Package Dimensions
unit : mm
PDIP30 / DIP30SD (400 mil)
CASE 646AZ
ISSUE A
GENERIC
MARKING DIAGRAM*
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
No.A2279-7/30
LC87F2L08A
Pin Assignment
P30/INT5//T1IN/BUZ/CMP1O
1
30
P15/SCK1
PPGO
2
29
P14/SB1
RES#
3
28
P21/URX/INT4/T1IN
VSS1
4
27
P20/UTX/INT4/T1IN
CF1/XT1
5
26
P73/INT3//T0IN
CF2/XT2
6
25
P72/INT2/T0IN
VDD1
7
24
P71/INT1/T0HCP/AN9
AMP1I
8
23
P70/INT0/T0LCP/AN8
CMP1IA
9
22
P07/T7O/DBGP02
CMP1IB
10
21
P06/AN6/T6O/DBGP01
CMP2I
11
20
P05/AN5/CKO/DBGP00
P00/AN0
12
19
P04/AN4
P01/AN1
13
18
VSS2
P02/AN2
14
17
AMP2O
P03/AN3
15
16
CMP4I
DIP30SD “Lead-free Type”
DIP30SD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NAME
P30/INT5//T1IN/BUZ/CMP1O
PPGO
RES#
VSS1
CF1/XT1
CF2/XT2
VDD1
AMP1I
CMP1IA
CMP1IB
CMP2I
P00/AN0
P01/AN1
P02/AN2
P03/AN3
DIP30SD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NAME
CMP4I
AMP2O
VSS2
P04/AN4
P05/AN5/CKO/DBGP00
P06/AN6/T6O/DBGP01
P07/T7O/DBGP02
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3//T0IN
P20/UTX/INT4/T1IN
P21/URX/INT4/T1IN
P14/SB1
P15/SCK1
No.A2279-8/30
LC87F2L08A
System Block Diagram
Interrupt control
IR
PLA
Flash ROM
Standby control
X'tal
SRC1
RC
Clock
generator
CF/
PC
MRC
ACC
WDT(SRC2)
Reset circuit
(LVD/POR)
Reset control
RES#
B register
C register
PPG
Bus interface
SIO1
Port 0
Timer 0
Port 1
Timer 1
Port 2
Timer 6
Port 3
Timer 7
Port 7
Base timer
ADC
ALU
PSW
RAR
RAM
Stack pointer
On-chip-debugger
INT0-2
INT3 (Noise filter)
Port 2 INT4
UART1
Port 3 INT5
No.A2279-9/30
LC87F2L08A
Pin Function Chart
Pin Name
I/O
VSS1
VSS2
VDD1
Port 0
P00 to P07


I/O
Description
Option
 power supply pins
No
power supply pin
 8-bit I/O port
 I/O specifiable in 4 bit units
 Pull-up resistors can be turned on and off in 4 bit units.
 HOLD reset input
 Port 0 interrupt input
 Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
P00(AN0) to P06(AN6):AD converter input
P05(DBGP00) to P07(DBGP02):On-chip debugger port
 2-bit I/O port
 I/O specifiable in 1 bit units
 Pull-up resistors can be turned on and off in 1 bit units.
 Pin functions
P14: SIO1 data I/O
P15: SIO1 clock I/O
No
Yes
Port 1
P14 to P15
I/O
Port 2
P20 to P21
I/O
 2-bit I/O port
 I/O specifiable in 1 bit units
 Pull-up resistors can be turned on and off in 1 bit units.
 Pin functions
P20 : UART transmit
P21 : UART receive
P20 to P21 : INT4 input / HOLD reset input / timer 1 event input /
timer 0L capture input / timer 0H capture input
Interrupt acknowledge type
Rising
Falling
Rising &
H level
L level
Falling
INT4





Yes
Port 3
P30
I/O
 1-bit I/O port
 I/O specifiable in 1 bit units
 Pull-up resistors can be turned on and off in 1 bit units.
 Pin functions
P30: BUZ output/CMP1O output/
INT5 input/HOLD reset input / timer 1 event input /
timer 0L capture input/timer 0H capture input
Interrupt acknowledge type
Rising
Falling
Rising &
H level
L level
Falling
INT5





Yes
Yes
No.A2279-10/30
LC87F2L08A
Pin Name
I/O
Port 7
P70 to P73
I/O
Description
Option
 4-bit I/O port
 I/O specifiable in 1 bit units
 Pull-up resistors can be turned on and off in 1 bit units.
 Pin functions
P70 : INT0 input / HOLD reset input / timer 0L capture input
P71 : INT1 input / HOLD reset input / timer 0H capture input
P72 : INT2 input / HOLD reset input / timer 0 event input /
timer 0L capture input
P73 : INT3 input (with noise filter) / timer 0 event input /
timer 0H capture input
P70(AN8),P71(AN9) : AD converter input
Interrupt acknowledge type
Rising
Falling
Rising &
H level
L level
Falling
INT0





INT1





INT2





INT3





No
AMP1I
I
AMP1 input
No
AMP2O
O
AMP2 output
No
CMP1IA
I
CMP1 input(-)
No
CMP1IB
I
CMP1 input(+)
No
CMP2I
I
CMP2 input(+)
No
CMP4I
I
CMP4 input(+)
No
PPGO
O
Yes
RES
CF1/XT1
I/O
I
PPG output
External reset Input / internal reset output
CF2/XT2
I/O
 Ceramic resonator or 32.768kHz crystal oscillator input pin
 Pin function
General-purpose input port
 Ceramic resonator or 32.768kHz crystal oscillator output pin
 Pin function
General-purpose input port
No
No
No
No.A2279-11/30
LC87F2L08A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option
selected in
units of
P00 to P07
1 bit
P14 to P15
P20 to P21
P30
P30 to P31
1 bit
1 bit
P70
P71 to P73
PPGO



Option type
Output type
Pull-up resistor
1
2
1
2
CMOS
Nch-open drain
CMOS
Nch-open drain
Programmable (Note 1)
No
Programmable
Programmable
1
2
No
No
1
2
CMOS
Nch-open drain
Nch-open drain
CMOS
CMOS
Nch-open drain
Programmable
Programmable
Programmable
Programmable
No
No
Note 1 : The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between
low- and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or P04 to 07).
User Option Table
Option name
Port output type
Option to be applied on
Flash-ROM
version
Option selected in units of
P00 to P07

P14 to P15

1 bit
P20 to P21

1 bit
P30

1 bit
PPGO

-
PPGO

-
1 bit
Option selection
CMOS
Nch-open drain
CMOS
Nch-open drain
CMOS
Nch-open drain
CMOS
Nch-open drain
CMOS
PPGO output
polarity
Magnification of
AMP1
Program start
address
Low-voltage
detection reset
function
Power-on reset
function
Nch-open drain
Not inverted
Inverted
x6
-

-
x8
x10
00000h
-

-
Detect function

-
Detect level

-
7-level
Power-On reset level

-
8-level
01E00h
Enable : Use
Disable : Not Used
No.A2279-12/30
LC87F2L08A
Recommended Unused Pin Connections
Pin Name
Recommended Unused Pin Connections
Board
Software
P00 to P07
Open
Output low
P14 to P15
Open
Output low
P20 to P21
Open
Output low
P30
Open
Output low
P70 to P73
Open
Output low
CF1/XT1
Pulled low with a 100kΩ resistor or less
General-purpose input port
CF2/XT2
Pulled low with a 100kΩ resistor or less
General-purpose input port
On-chip Debugger pin connection requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87 Onchip
Debugger Installation Manual" and "LC872000 Series Onchip debugger pin connection requirements"
Note : Be sure to electrically short-circuit between the VSS1 and VSS2 pins.
No.A2279-13/30
LC87F2L08A
1. Absolute Maximum Ratings at Ta=25C, VSS1= VSS2= 0V
Parameter
Maximum supply
voltage
Input voltage
Low level output current
High level output current
output voltage
Input/output
voltage
Peak output
current
Symbol
Specification
typ.
max.

+6.5
VI
CF1, RES#,
AMP1I,
CMP1IA,CMP1IB,
CMP2I, CMP4I
AMP2O, PPGO
CF2,
Ports 0, 1, 2, 3,
Port 7
Ports 0, 1, 2, 3,
PPGO
P71 to P73
0.3

VDD+0.3
0.3
0.3


VDD+0.3
VDD+0.3
VO
VIO
IOPH(1)
IOMH(1)
Total output
current
ΣIOAH(1)
ΣIOAH(2)
Peak output
current
IOPL(1)
IOPL(2)
IOPL(3)
IOML(1)
IOML(2)
IOML(3)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
Pdmax(1)
Pdmax(2)
Operating
ambient
temperature
Storage ambient
temperature
min.
0.3
IOMH(2)
Power
dissipation
VDD[V]
VDD1
Mean output
current
(Note 1-1)
Total output
current
Conditions
VDDMAX
IOPH(2)
Mean output
current
(Note 1-1)
Pin/Remarks
CMOS output select
Per 1 applicable pin
10
Per 1 applicable pin
5
Ports 0, 1, 2, 3,
PPGO
P71 to P73
CMOS output select
Per 1 applicable pin
7.5
Per 1 applicable pin
3
P71 to P73
Ports 0, 1, 2, 3,
PPGO
P02 to P07,
Ports 1, 2, 3,
PPGO
P00, P01
Port 7
P02 to P07,
Ports 1, 2, 3,
PPGO
P00, P01
Port 7
P00 to P03
P04 to P07,
Ports 1, 2, 3, 7,
PPGO
Ports 0, 1, 2, 3, 7,
PPGO
DIP30SD
Total of all applicable pins
Total of all applicable pins
unit
V
mA
10
25
Per 1 applicable pin
20
Per 1 applicable pin
30
10
15
Per 1 applicable pin
Per 1 applicable pin
Total of all applicable pins
20
7.5
40
40
Total of all applicable pins
70
Ta=40 to +85C
Package only
Ta=40 to +85C
Package with thermal
resistance board
(Note 1-2)
350
Per 1 applicable pin
Per 1 applicable pin
Total of all applicable pins
mW
540
Topr
40

+85
Tstg
55

+125
C
Note 1-1 : The mean output current is a mean value measured over 100ms.
Note 1-2 : SEMI standards thermal resistance board (size : 76.1×114.3×1.6tmm, glass epoxy) is used.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
No.A2279-14/30
LC87F2L08A
2. Allowable Operating Conditions at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Operating
supply voltage
(Note 2-1)
Memory
sustaining
supply voltage
High level
input voltage
Low level input
voltage
Instruction
cycle time
(Note 2-1)
External
system clock
frequency
Symbol
Pin/Remarks
Conditions
VDD[V]
min.
VDD
VDD1
0.245µs  tCYC  200µs
4.5
VHD
VDD1
RAM and register contents
sustained in HOLD mode.
2.0
VIH(1)
Ports 1, 2, 3, 7
4.5 to 5.5
VIH(2)
Ports 0
4.5 to 5.5
Specification
typ.
max.
5.5
VIH(3)
CF1, RES#
4.5 to 5.5
0.3VDD
+0.7
0.3VDD
+0.7
0.75VDD
VIL(1)
Ports 1, 2, 3, 7
4.5 to 5.5
VSS
0.1VDD
+0.4
VIL(2)
Ports 0
4.5 to 5.5
VSS
0.15VDD
+0.4
VIL(3)
CF1, RES#
tCYC
(Note 2-2)
FEXCF
CF1
 CF2 pin open
 System clock frequency
unit
V
VDD
VDD
VDD
1.8 to 5.5
VSS
0.25VDD
4.5 to 5.5
0.245
200
µs
4.5 to 5.5
0.1
12
MHz
4.5 to 5.5
0.2
24.4
division ratio = 1/1
 External system clock duty
= 505%
 CF2 pin open
 System clock frequency
division ratio = 1/2
 External system clock duty
Oscillation
frequency
range
(Note 2-3)
FmCF(1)
CF1, CF2
FmCF(2)
CF1, CF2
FmCF(3)
CF1, CF2
FmMRC
FmRC
FmSRC1
FmSRC2
FsX’tal
XT1, XT2
= 505%
12 MHz ceramic oscillation
See Fig. 1.
10 MHz ceramic oscillation
See Fig. 1.
4 MHz ceramic oscillation.
CF oscillation normal
amplifier size selected.
See Fig. 1. (CFLAMP=0)
4 MHz ceramic oscillation.
CF oscillation low amplifier
size selected. (CFLAMP=1)
See Fig. 1.
Frequency variable RC
oscillation.
1/2 frequency division ratio.
(RCCTD=0) (Note 2-4)
Internal Medium-speed RC
oscillation
Internal Low-speed RC
oscillation 1
Internal Low-speed RC
oscillation 2
32.768kHz crystal oscillation
See Fig. 2.
4.5 to 5.5
12
4.5 to 5.5
10
4.5 to 5.5
4
4.5 to 5.5
4
MHz
4.5 to 5.5
7.44
8.0
8.56
4.5 to 5.5
0.5
1.0
2.0
4.5 to 5.5
50
100
200
4.5 to 5.5
15
30
60
4.5 to 5.5
kHz
32.768
Note 2-1 : VDD must be held greater than or equal to 2.2 V in the flash ROM onboard programming mode.
Note 2-2 : Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3 : See Tables 1 and 2 for the oscillation constants.
Note 2-4 : When switching the system clock, allow an oscillation stabilization time of 100 μs or longer after the
multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
No.A2279-15/30
LC87F2L08A
3. Electrical Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Ports 0, 1, 2, 3
Ports 7,
CMP1IA, CMP1IB,
CMP2I, CMP4I,
AMP1I, RES#
CF1
Output disabled
Pull-up resistor off
VIN=VDD
(Including output Tr's off
leakage current)
VIN=VDD
4.5 to 5.5
IAMPO
AMP2O
Output disabled
Pull-up resistor off
VIN=VSS
(Including output Tr's off
leakage current)
VIN=VSS
Magnification of AMP1 is
selected x8 by user
option
Magnification of AMP2 is
selected x1 by resister
AMP1I=0.445V
IOH=1mA
4.5 to 5.5
IIL(2)
Ports 0, 1, 2, 3
Ports 7,
CMP1IA, CMP1IB,
CMP2I, CMP4I,
AMP1I, RES#
CF1
High level input
current
IIH(1)
Low level input
current
IIL(1)
AMP output
current
(Note 3-1)
High level output
voltage
VOH(1)
Ports 0, 1, 2
P71 to P73
Port 3,PPGO
Low level output
voltage
VOL(1)
IIH(2)
min.
Specification
typ. max.
1
4.5 to 5.5
15
4.5 to 5.5
15
5.0
2.3
4.5 to 5.5
VDD1
VDD1
0.30
IOH=6mA
4.5 to 5.5
4.5 to 5.5
1.5
VOL(2)
IOL=1.4mA
4.5 to 5.5
0.4
VOL(4)
Port 7
IOL=1.4mA
4.5 to 5.5
0.4
VOL(6)
P00, P01
IOL=25mA
4.5 to 5.5
1.5
IOL=4mA
4.5 to 5.5
Rpu(1)
Ports 0, 1, 2, 3
Port 7
4.5 to 5.5
18
50
230
Rpu(3)
Port 0
VOH=0.9VDD
When Port 0 selected
low-impedance pull-up.
VOH=0.9VDD
When Port 0 selected
High-impedance pull-up.
4.5 to 5.5
100
210
400
Hysteresis
voltage
VHYS(1)
Ports 1, 2, 3, 7,
RES#
Pin capacitance
CP
All pins
VOL(7)
For pins other than that
under test:
VIN=VSS
f=1MHz
Ta=25C
mA
V
IOL=10mA
Pull-up resistance
µA
1
Ports 0, 1, 2, 3,
PPGO
VOH(4)
unit
0.4
k
4.5 to 5.5
0.1
VDD
V
4.5 to 5.5
10
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Note 3-1 :
O u t put C h ar ac t er ist ic s C u r rent S in king
O u t put C h ar ac t er ist ic s C u r rent S o urc ing
5
5
4.5
4.5
4
4
AMP2O (V)
3
3
2.5
2.5
2
2
AMP2O (V)
3.5
3.5
1.5
1.5
1
1
0.5
0.5
0
0
-5
-4
-3
-2
Output Source Current (mA)
-1
0
0
0.05
0.1
0.15
0.2
Output Sink Current (mA)
0.25
0.3
0.35
No.A2279-16/30
LC87F2L08A
4. Serial I/O Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
4-1. SIO1 Serial I/O Characteristics (Note 4-1-1)
Serial output
Serial input
Output clock
Serial clock
Input clock
Parameter
Symbol
Pin/Remarks
 See Fig. 5.
VDD[V]
min.
4.5 to 5.5
2
Specification
typ.
max.
Frequency
tSCK(3)
Low level
pulse width
tSCKL(3)
1
High level
pulse width
tSCKH(3)
1
Frequency
tSCK(4)
Low level
pulse width
tSCKL(4)
1/2
High level
pulse width
tSCKH(4)
1/2
Data setup time
tsDI(2)
Data hold time
thDI(2)
Output delay
time
tdD0(4)
SCK1(P15)
Conditions
SCK1(P15)
SB1(P14)
SB1(P14)
 CMOS output selected
 See Fig. 5.
 Must be specified with
respect to rising edge of
SIOCLK.
 See Fig. 5.
4.5 to 5.5
4.5 to 5.5
unit
tCYC
2
tSCK
0.05
µs
0.05
4.5 to 5.5
 Must be specified with
respect to falling edge of
SIOCLK.
 Must be specified as the
time to the beginning of
output state change in
open drain output mode.
 See Fig. 5.
(1/3)tCYC
+0.08
Note 4-1-1 : These specifications are theoretical values. Add margin depending on its use.
5. Pulse Input Conditions at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Symbol
High/low
level pulse
width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
Pin/Remarks
INT0(P70),
INT1(P71),
INT2(P72),
INT4(P20 to P21),
INT5(P30 to P31)
INT3(P73) when
noise filter time
constant is 1/1
INT3(P73) when
noise filter time
constant is 1/32
INT3(P73) when
noise filter time
constant is 1/128
RES#
Conditions
VDD[V]
min.
 Interrupt source flag can be set. 4.5 to 5.5
 Event inputs for timer 0 or 1 are
enabled.
1
 Interrupt source flag can be set.
 Event inputs for timer 0 are
enabled.
 Interrupt source flag can be set.
 Event inputs for timer 0 are
enabled.
 Interrupt source flag can be set.
 Event inputs for timer 0 are
enabled.
 Resetting is enabled.
4.5 to 5.5
2
4.5 to 5.5
64
4.5 to 5.5
256
4.5 to 5.5
200
Specification
typ. max.
unit
tCYC
µs
No.A2279-17/30
LC87F2L08A
6. AD Converter Characteristics at VSS1= VSS2=0V
<12bits AD Converter Mode / Ta=40 to +85C >
Parameter
Symbol
Resolution
Absolute
accuracy
Conversion
time
N
ET
Analog input
voltage range
Analog port
input current
VAIN
Pin/Remarks
AN0(P00) to
AN6(P06)
AN8(P70)
AN9(P71)
TCAD
IAINH
IAINL
Conditions
VDD[V]
min.
4.5 to 5.5
4.5 to 5.5
(Note 6-1)
See Conversion time
calculation formulas.
(Note 6-2)
●
VAIN=VDD
VAIN=VSS
Specification
typ.
max.
12
unit
16
bit
LSB
4.5 to 5.5
32
115
µs
4.5 to 5.5
VSS
VDD
V
4.5 to 5.5
4.5 to 5.5
1
µA
1
VDD[V]
min.
<8bits AD Converter Mode / Ta=40 to +85C >
Parameter
Symbol
Resolution
Absolute
accuracy
Conversion
time
N
ET
Analog input
voltage range
Analog port
input current
VAIN
TCAD
Pin/Remarks
AN0(P00) to
AN6(P06)
AN8(P70)
AN9(P71)
IAINH
IAINL
Conditions
4.5 to 5.5
4.5 to 5.5
(Note 6-1)
See Conversion time
calculation formulas.
(Note 6-2)
●
VAIN=VDD
VAIN=VSS
Specification
typ.
max.
8
unit
1.5
bit
LSB
4.5 to 5.5
20
90
µs
4.5 to 5.5
VSS
VDD
V
4.5 to 5.5
4.5 to 5.5
1
µA
1
Conversion time calculation formulas :
12bits AD Converter Mode : TCAD(Conversion time)=((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode : TCAD(Conversion time)=((32/(AD division ratio))+2)×(1/3)×tCYC
External
oscillation
(FmCF)
Operating supply
voltage range
(VDD)
System
division ratio
(SYSDIV)
Cycle time
(tCYC)
AD division
ratio
(ADDIV)
CF-12MHz
CF-10MHz
CF-4MHz
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
1/1
1/1
1/1
250ns
300ns
750ns
1/8
1/8
1/8
AD conversion time
(TCAD)
12bit AD
8bit AD
34.8µs
41.8µs
104.5µs
21.5µs
25.8µs
64.5µs
Note 6-1 : The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2 : The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the
analog input value.
The conversion time is 2 times the normal-time conversion time when:
● The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
● The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.
No.A2279-18/30
LC87F2L08A
7. Power-on Reset (POR) Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Specification
Parameter
POR release
voltage
Symbol
Pin/Remarks
PORRL
Conditions
Option selected
voltage
min.
typ.
max.
unit
 Select from option.
(Note 7-1)
1.67V
1.97V
2.07V
2.37V
2.57V
1.55
1.85
1.95
2.25
2.45
1.67
1.97
2.07
2.37
2.57
1.79
2.09
2.19
2.49
2.69
V
2.87V
3.86V
4.35V
2.75
3.73
4.21
2.87
3.86
4.35
0.7
2.99
3.99
4.49
0.95
Detection
voltage
unknown state
POUKS
 See Fig. 7.
(Note 7-2)
Power supply
rise time
PORIS
 Power supply rise
time from 0V to 1.6V.
100
ms
Note7-1 : The POR release level can be selected out of 8 levels only when the LVD reset function is disabled.
Note7-2 : POR is in an unknown state before transistors start operation.
8. Low Voltage Detection Reset (LVD) Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
 Select from
option.
(Note 8-1)
(Note 8-3)
 See Fig. 8.
LVD reset
Voltage
(Note 8-2)
LVDET
LVD hysteresis
width
LVHYS
Detection
voltage
unknown state
Low voltage
detection
minimum width
(Reply
sensitivity)
LVUKS
 See Fig. 8.
(Note 8-4)
TLVDW
 LVDET-0.5V
 See Fig. 9.
Option selected
voltage
1.91V
2.01V
2.31V
2.51V
2.81V
3.79V
4.28V
1.91V
2.01V
2.31V
2.51V
2.81V
3.79V
4.28V
min.
typ.
max.
unit
1.81
1.91
2.21
2.41
2.71
3.69
4.18
1.91
2.01
2.31
2.51
2.81
3.79
4.28
55
55
55
55
60
65
65
0.7
2.01
2.11
2.41
2.61
2.91
3.89
4.38
V
mV
0.95
0.2
V
ms
Note8-1 : The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled.
Note8-2 : LVD reset voltage specification values do not include hysteresis voltage.
Note8-3 : LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4 : LVD is in an unknown state before transistors start operation.
No.A2279-19/30
LC87F2L08A
9. Amplifier and Comparator Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
min.
Input
common-mode
voltage
(Note9-1)
Internal
reference
voltage
VCMIN
CMP1IA, CMP1IB,
CMP2I,CMP4I
4.5 to 5.5
VSS
VREF
“-” inputs of CMP2,
CMP3, CMP4
4.5 to 5.5
2/3VDD
0.02
AMP input
voltage
(Note9-2)
VAMIN
AMP1I
4.5 to 5.5
VSS
Offset voltage
VOFF(1)
CMP1IA, CMP1IB
(CMP1)
Input common-mode
voltage range
VOFF(2)
CMP2I (CMP2),
CMP4I (CMP4)
VOFF(3)
AMP1I (CMP3)
 Input common-mode
voltage range
 Including VREF error
 AMP Input voltage range
 Magnification of AMP1 is
selected x8 by user
option
AMP output
error
VAER
AMP2O
CMP1
response
speed
tC1RT
CMP1O(P30)
CMP3
response
speed
(Note9-3)
tC3RT
PPGO
CMP4
response
speed
tC4RT
PPGO
 Including VREF error
 AMP Input voltage range
 Magnification of AMP1 is
selected x8 by user
option
 Magnification of AMP2 is
selected x1 by resister
 Input common-mode
voltage range
 Input amplitude=100mV
 Over drive=50mV
 Magnification of AMP1 is
selected x8 by user
option
 AMP1I rising timing
 AMP1I=(VREF±100mV)/8
 See Fig. 10.
 CMP4I rising timing
Specification
typ.
max.
VDD
1.5V
2/3VDD
unit
V
2/3VDD
+0.02
(VDD
1.5V)
/Magnific
ation of
AMP
V
4.5 to 5.5
20
mV
4.5 to 5.5
40
4.5 to 5.5
28
4.5 to 5.5
155
4.5 to 5.5
200
4.5 to 5.5
600
4.5 to 5.5
200
200
mV
ns
 CMP4I=VREF±50mV
 See Fig. 10.
Note9-1 : When VDD=5V, the comparison input voltage is effective from 0 to 3.5V.
Note9-2 : Magnification of AMP= Magnification of AMP1× Magnification of AMP2
When VDD=5V, magnification of AMP1 to 8 magnification of AMP2 to 1, the AMP input voltage is effective from
0 to 0.4375V.
Note9-3 : PPGO have a delay of 1/6tCYC to 1/2tCYC from CMP1O falling timing for synchronization with system clock,
when the pulse start delay setup register (ADDRESS: FE92H, FE93H) is set to 000H.
No.A2279-20/30
LC87F2L08A
10. Consumption Current Characteristics at Ta=40 to +85C, VSS 1= VSS 2=0V
Parameter
Normal
mode
consumption
current
(Note 10-1)
(Note 10-2)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
Pin/Remarks
VDD1
Conditions
 FmCF=12 MHz
ceramic oscillation mode
 System clock set to 12 MHz side
 Internal Low speed and Medium
speed RC oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/1 frequency division ratio
 FmCF=4 MHz
ceramic oscillation mode
 System clock set to 4 MHz side
 Internal Low speed and Medium
speed RC oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/1 frequency division ratio
 CF oscillation low amplifier size
selected. (CFLAMP=1)
 FmCF=4 MHz
ceramic oscillation mode
 System clock set to 4 MHz side
 Internal Low speed and Medium
speed RC oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/4 frequency division ratio
 FsX’tal=32.768 kHz
Crystal oscillation mode
 Internal Low speed RC
oscillation stopped.
 System clock set to internal
Medium speed RC oscillation.
 Frequency variable RC
oscillation stopped.
 1/2 frequency division ratio
 FsX’tal=32.768 kHz crystal
oscillation mode
 Internal Low speed and Medium
speed RC oscillation stopped.
 System clock set to 8MHz with
Frequency variable RC
oscillation
 1/1 frequency division ratio
 External FsX’tal and FmCF
oscillation stopped.
 System clock set to internal
Low speed RC oscillation.
 Internal Medium speed RC
oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/1 frequency division ratio
 FsX’tal=32.768 kHz crystal
oscillation mode
 System clock set to 32.768kHz
side
 Internal Low speed and Medium
speed RC oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/2 frequency division ratio
VDD[V]
min.
Specification
typ.
Max.
4.5 to 5.5
8.7
16
4.5 to 5.5
4.4
8.7
4.5 to 5.5
2.6
4.8
4.5 to 5.5
2.1
3.8
4.5 to 5.5
6.7
11.3
4.5 to 5.5
1.6
2.6
4.5 to 5.5
1.6
2.6
unit
mA
No.A2279-21/30
LC87F2L08A
Parameter
Symbol
HALT mode
consumption
current
(Note 10-1)
(Note 10-2)
IDDHALT(1)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
Pin/remarks
VDD1
Conditions
 HALT mode
 FmCF=12 MHz
ceramic oscillation mode
 System clock set to 12 MHz side
 Internal Low speed and Medium
speed RC oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/1 frequency division ratio
 HALT mode
 FmCF=4 MHz
ceramic oscillation mode
 System clock set to 4 MHz side
 Internal Low speed and Medium
speed RC oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/1 frequency division ratio
 HALT mode
 CF oscillation low amplifier size
selected. (CFLAMP=1)
 FmCF=4 MHz
ceramic oscillation mode
 System clock set to 4 MHz side
 Internal Low speed and Medium
speed RC oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/4 frequency division ratio
 HALT mode
 FsX’tal=32.768 kHz crystal
oscillation mode
 Internal Low speed RC oscillation
stopped.
 System clock set to internal
Medium speed RC oscillation
 Frequency variable RC
oscillation stopped.
 1/2 frequency division ratio
 HALT mode
 FsX’tal=32.768 kHz crystal
oscillation mode
 Internal Low speed and Medium
speed RC oscillation stopped.
 System clock set to 8MHz with
Frequency variable RC
oscillation
 1/1 frequency division ratio
 HALT mode
 External FsX’tal and FmCF
oscillation stopped.
 System clock set to internal
Low speed RC oscillation.
 Internal Medium speed RC
oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/1 frequency division ratio
 HALT mode
 FsX’tal=32.768 kHz crystal
oscillation mode
 System clock set to 32.768kHz
side
 Internal Low speed and Medium
speed RC oscillation stopped.
 Frequency variable RC
oscillation stopped.
 1/2 frequency division ratio
VDD[V]
min.
Specification
typ.
max.
4.5 to 5.5
4.4
8.7
4.5 to 5.5
2.9
5.5
4.5 to 5.5
2.2
3.9
4.5 to 5.5
1.9
3.1
4.5 to 5.5
3.3
5.9
4.5 to 5.5
1.5
2.5
4.5 to 5.5
1.6
2.6
unit
mA
No.A2279-22/30
LC87F2L08A
Parameter
HOLD mode
consumption
current
(Note 10-1)
(Note 10-2)
(Note 10-3)
Symbol
IDDHOLD
Pin/remarks
VDD1
Conditions
HOLD mode
 FsX’tal=32.768 kHz crystal
oscillation mode
 LVD option selected
VDD[V]
4.5 to 5.5
min.
Specification
typ.
max.
1.5
2.6
unit
mA
Note10-1 : Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note10-2 : The consumption current values do not include operational current of LVD function if not specified.
Note10-3 : AMP/CMP circuit is operating in HOLD mode.
No.A2279-23/30
LC87F2L08A
11. F-ROM Programming Characteristics at Ta=+10 to +55C, VSS1= VSS2=0V
Parameter
Symbol
Onboard
programming
current
Programming
time
IDDFW(1)
Pin/Remarks
VDD1
tFW(1)
tFW(2)
Conditions
VDD[V]
min.
Specification
typ. max.
unit
 Only current of the Flash block.
4.5 to 5.5
5
10
mA
 Erasing time
 Programming time
4.5 to 5.5
20
40
30
60
ms
µs
12. UART (Full Duplex) Operating Conditions at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Transfer rate
Symbol
UBR
Pin/Remarks
Conditions
UTX(P20)
URX(P21)
VDD[V]
min.
Specification
typ.
max.
unit
4.5 to 5.5
16/3
8192/3
tCYC
Data length : 7/8/9 bits (LSB first)
Stop bits
: 1 bit(2-bit in continuous data transmission)
Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit
Start of
transmission
Stop bit
End of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start bit
Start of
reception
Stop bit
Receive data (LSB first)
End of
reception
UBR
No.A2279-24/30
LC87F2L08A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
ON Semiconductor-designated oscillation characteristics evaluation board and external components with
circuit constant values with which the oscillator vendor confirmed normal and stable oscillation.
Table 1. Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
● CF oscillation normal amplifier size selected (CFLAMP=0)
 MURATA
Nominal
Frequency
12MHz
10MHz
8MHz
6MHz
4MHz
C1
[pF]
C2
[pF]
Rf
[]
Rd
[]
Operating
Voltage
Range
[V]
(10)
(10)
(15)
(10)
(15)
(15)
(15)
(15)
(15)
(10)
(10)
(15)
(10)
(15)
(15)
(15)
(15)
(15)
Open
Open
Open
Open
Open
Open
Open
Open
Open
680
680
680
1k
1k
1.5k
1.5k
1.5k
1.5k
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
Circuit Constant
Type
Oscillator Name
SMD
SMD
LEAD
SMD
LEAD
SMD
LEAD
SMD
LEAD
CSTCE12M0G52-R0
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCR6M00G53-R0
CSTLS6M00G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
Oscillation
Stabilization Time
Typ
Max
[ms]
[ms]
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.2
0.2
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.6
0.6
Remarks
Internal C1,C2
● CF oscillation low amplifier size selected (CFLAMP=1)
 MURATA
Nominal
Frequency
C1
[pF]
C2
[pF]
Rf
[]
Rd
[]
Operating
Voltage
Range
[V]
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
Open
Open
Open
Open
1k
1k
1k
1k
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
Circuit Constant
Type
SMD
4MHz
LEAD
Oscillator Name
CSTCR4M00G53-R0
CSTCR4M00G53095-R0
CSTLS4M00G53-B0
CSTLS4M00G53095-B0
Oscillation
Stabilization Time
Typ
Max
[ms]
[ms]
0.2
0.2
0.2
0.2
0.6
0.6
0.6
0.6
Remarks
Internal C1,C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 3).
No.A2279-25/30
LC87F2L08A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a
ON Semiconductor-designated oscillation characteristics evaluation board and external components with
circuit constant values with which the oscillator vendor confirmed normal and stable oscillation.
Table 2. Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
 EPSON TOYOCOM
Nominal
Frequency
Type
Oscillator
Name
32.768kHz
SMD
MC-306
C1
[pF]
C2
[pF]
Rf
[]
Rd
[]
Operating
Voltage
Range
[V]
8pF
8pF
Open
0
4.5 to 5.5
Circuit Constant
Oscillation
Stabilization Time
Typ
Max
[s]
[s]
1.00s
1.50s
Remarks
Applicable
CL value =
7.0pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 3).
Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they
are vulnerable to the influences of the circuit pattern.
CF1/XT
CF2/XT2
Rf
C1
CF/X’tal
Rd
C
Figure 1. CF and XT Oscillator Circuit
0.5VDD
Figure 2. AC Timing Measurement Point
No.A2279-26/30
LC87F2L08A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES#
Internal Medium speed
RC oscillation
tmsCF/tmsXtal
CF1, CF2
Operating
mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal Medium speed
RC oscillation or
Low speed RC oscillation
tmsCF/tmsXtal
CF1, CF2
(Note)
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Note : External oscillation circuit is selected.
Figure 3. Oscillation Stabilization Times
No.A2279-27/30
LC87F2L08A
VDD
RRES
Note :
External circuits for reset may vary depending on the usage of
POR and LVD. Please refer to the user’s manual for more
information.
RES#
CRES
Figure 4. Reset Circuit
SIOCLK :
DATAIN :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DATAOUT :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK
tSCKL
tSCKH
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Figure 5. Serial I/O Output Waveforms
tPIL
tPIH
Figure 6. Pulse Input Timing Signal Waveform
No.A2279-28/30
LC87F2L08A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
Reset period
100μs or longer
Unknown-state
(POUKS)
RES#
Figure 7. Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to
the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR
function or implement an external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is
turned on again after this condition continues for 100μs or longer.
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Unknown-state
(LVUKS)
RES#
Figure 8. Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near
the detection level.
No.A2279-29/30
LC87F2L08A
VDD
LVD release voltage
LVD reset voltage
LVDET-0.5V
TLVDW
VSS
Figure 9. Low voltage detection minimum width
(Example of momentary power loss / Voltage variation waveform)
(VREF+100mV)/8
VREF/8
(VREF100mV)/8
AMP1I
VREF+50mV
VREF
VREF50mV
CMP4I
PPGO
tC3RT
tC4RT
Figure 10. CMP response time
ORDERING INFORMATION
Device
LC87F2L08AU-DIP-E
Package
DIP30SD(400mil)
(Pb-Free)
Shipping (Qty / Packing)
20 / Fan-Fold
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
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directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
PS No.A2279-30/30
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