ENA1622 D

Ordering
Orderingnumber
number: :ENA1622B
ENA1951
LC87F2R04A
CMOS IC
4K-byte FROM and 128-byte RAM integrated
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F2R04A is an 8-bit microcontroller that, integrates on a single chip a number of hardware features such as
4K-byte flash ROM, 128-byte RAM, an On-chip-debugger, 16-bit timers/counters, two 8-bit timers,
an asynchronous/synchronous SIO interface, an 8-channel AD converter, an internal reset and an interrupt feature.
Package Dimensions
unit : mm (typ)
3287
6.5
24
13
0.5
RAM
• 128 × 9 bits
12
1
Package Form
• SSOP24(225mil): Lead-/Halogen-free type
6.4
Flash ROM
• 4096 × 8 bits
• Capable of on-board programming
with wide range (2.2 to 5.5V) of voltage source.
• Block-erasable in 128 byte units
• Writable in 2-byte units
4.4
Features
0.5
0.15
0.22
(0.5)
(1.3)
1.5max
• MFP24S(300mil): Lead-/Halogen-free type
(discontinued)
0.1
• SSOP24(275mil): Lead-/Halogen-free type
(build-to-order)
• VCT24(3mm×3mm): Lead-/Halogen-free type
(build-to-order)
SANYO : SSOP24(225mil)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.0.65
12313HK/51712HKIM 20120426-S00006 No.A1622-1/25
LC87F2R04A
Package Dimensions
unit : mm (typ)
3112B
(discontinued)
12.5
0.63
7.6
13
5.4
24
1
12
1.0
0.15
0.35
1.7max
0.1
(1.5)
(0.75)
SANYO : MFP24S(300mil)
Package Dimensions
Package Dimensions
unit : mm (typ)
3175C
(build-to-order )
unit : mm (typ)
3366
(build-to-order )
TOP VIEW
7.8
24
SIDE VIEW
BOTTOM VIEW
13
3.0
0.4
0.5
5.6
7.6
(C0.14)
12
1
0.65
24
0.15
2 1
0.19
SIDE VIEW
(0.5)
0.8
0.4
(0.035)
0.1
1.5max
0.22
(1.3)
(0.33)
(0.09)
(0.125)
3.0
SANYO : VCT24(3.0X3.0)
SANYO : SSOP24(275mil)
Minimum Bus Cycle
• 83.3ns (12MHz at VDD=2.7V to 5.5V)
• 100ns (10MHz at VDD=2.2V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
• 250ns (12MHz at VDD=2.7V to 5.5V)
• 300ns (10MHz at VDD=2.2V to 5.5V)
No.A1622-2/25
LC87F2R04A
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 11(P1n, P20, P21, P70)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
• Dedicated oscillator ports/input ports
2 (CF1, CF2)
• Reset pin
1 (RES)
• Power pins
2 (VSS1, VDD1)
Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
SIO
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
AD Converter: 12 bits/8 bits × 8 channels
• 12/8 bits AD converter resolution selectable
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC/32 tCYC/128 tCYC)
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Interrupts
• 12 sources, 8 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3
5
00023H
H or L
T0H
6
0002BH
H or L
None
7
00033H
H or L
None
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 64levels (The stack is allocated in RAM.)
No.A1622-3/25
LC87F2R04A
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• Internal oscillation circuits
Medium-speed RC oscillation circuit:
Multifrequency RC oscillation circuit:
• External oscillation circuits
Hi-speed CF oscillation circuit:
For system clock (1MHz)
For system clock (8MHz)
For system clock, with internal Rf
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (at a main clock rate of 10MHz).
Internal reset function
• Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and
4.35V) through option configuration.
• Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, 4.28V).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
On-chip Debugger
• Supports software debugging with the IC mounted on the target board.
• Software break point setting for debugger.
• Stepwise execution on debugger.
• Real time RAM data monitoring function on debugger.
All the RAM data map can be monitored on screen when the program is running.
(The RAM & SFR data can be changed by screen patch when the program is running)
• Two channels of on-chip debugger pins are available to be compatible with small pin count devices.
DBGP0 (P0), DBGP1 (P1)
Data Security Function (flash versions only)
• Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
No.A1622-4/25
LC87F2R04A
Development Tools
• On-chip debugger: TCB87 TypeB+LC87F2R04A
: TCB87 TypeC (3 wire version) +LC87F2R04A
Programming Boards
Package
Programming boards
MFP24S(300mil)
W87F2GM
SSOP24(225mil)
W87F2GS
SSOP24(275mil)
build-to-order
VCT24
build-to-order
Flash ROM Programmer
Maker
Model
Supported Version
Device
Rev 03.11 or later
LC87F2L08A
-
-
-
-
(Note 2)
-
AF9708
Single
AF9709/AF9709B/AF9709C
(including Ando Electric Co., Ltd. models)
Flash Support Group, Inc.
AF9723/AF9723B(Main unit)
(FSG)
Ganged
(including Ando Electric Co., Ltd. models)
AF9833(Unit)
(including Ando Electric Co., Ltd. models)
AF9101/AF9103(Main unit)
Flash Support Group, Inc.
(FSG)
Onboard
(FSG)
+
single/ganged
SIB87(Interface driver)
Our company (Note 1)
(Our company)
Single/ganged
Our company
SKK/SKK Type B
Application version
(SANYO FWS)
1.05 or later
Onboard
SKK-DBG Type B
Chip data version
single/ganged
(SANYO FWS)
2.22 or later
LC87F2R04A
For information about AF-Series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: [email protected]
Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87)
together
can give a PC-less, standalone on-board-programming capabilities.
Note2: It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or Our company for the information.
No.A1622-5/25
LC87F2R04A
Pin Assignment
P70/INT0/T0LCP/AN8
1
24
P07/T7O/DBGP02
RES
2
23
P06/AN6/T6O/DBGP01
VSS1
3
22
P05/AN5/DBGP00
CF1
4
21
P04/AN4
CF2
5
20
P03/AN3
VDD1
6
19
P02/AN2
P10
7
18
P01/AN1
P11
8
17
P00/AN0
P12
9
16
P21/INT4
P13/SO1/DBGP12
10
15
P20/INT4
P14/SI1/SB1/DBGP11
11
14
P17/INT1/T0HCP
P15/SCK1/INT3/T0IN/DBGP10
12
13
P16/INT2/T0IN
LC87F2R04A
Top view
MFP24S(300mil) “Lead-/Halogen-free Type” (discontinued)
SSOP24(225mil) “Lead-/Halogen-free Type”
SSOP24(275mil) “Lead-/Halogen-free Type” (build-to-order)
MFP24S
SSOP24
NAME
MFP24S
SSOP24
NAME
1
P70/INT0/T0LCP/AN8
13
P16/INT2/T0IN
2
RES
14
P17/INT1/T0HCP
3
VSS1
15
P20/INT4
4
CF1
16
P21/INT4
5
CF2
17
P00/AN0
6
VDD1
18
P01/AN1
7
P10
19
P02/AN2
8
P11
20
P03/AN3
9
P12
21
P04/AN4
10
P13/SO1/DBGP12
22
P05/AN5/DBGP00
11
P14/SI1/SB1/DBGP11
23
P06/AN6/T6O/DBGP01
12
P15/SCK1/INT3/T0IN/DBGP10
24
P07/T7O/DBGP02
No.A1622-6/25
13 P20/INT4
14 P21/INT4
15 P00/AN0
16 P01/AN1
17 P02/AN2
18 P03/AN3
LC87F2R04A
P04/AN4 19
12 P17/INT1/T0HCP
P05/AN5/DBGP00 20
P06/AN6/T6O/DBGP01 21
P07/T7O/DBGP02 22
11 P16/INT2/T0IN
10 P15/SCK1/INT3/T0IN/DBGP10
LC87F2R04A
9 P14/SI1/SB1/DBGP11
8 P13/SO1/DBGP12
P70/INT0/T0LCP/AN8 23
RES 24
P11 6
P10 5
VDD1 4
CF2 3
CF1 2
VSS1 1
7 P12
Top view
VCT24(3.0×3.0) “Lead-/Halogen-free Type” (build-to-order)
VCT24
NAME
VCT24
NAME
1
VSS1
13
P20/INT4
2
CF1
14
P21/INT4
3
CF2
15
P00/AN0
4
VDD1
16
P01/AN1
5
P10
17
P02/AN2
6
P11
18
P03/AN3
7
P12
19
P04/AN4
8
P13/SO1/DBGP12
20
P05/AN5/DBGP00
P06/AN6/T6O/DBGP01
9
P14/SI1/SB1/DBGP11
21
10
P15/SCK1/INT3/T0IN/DBGP10
22
P07/T7O/DBGP02
11
P16/INT2/T0IN
23
P70/INT0/T0LCP/AN8
12
P17/INT1/T0HCP
24
RES
No.A1622-7/25
LC87F2R04A
System Block Diagram
Interrupt control
IR
PLA
Flash ROM
Standby control
Clock
generator
CF
RC
PC
MRC
ACC
WDT
Reset circuit
(LVD/POR)
Reset control
RES
B register
C register
SIO1
Bus interface
Timer 0
Port 0
Timer 6
Port 1
Timer 7
Port 2
ADC
Port 7
INT0-2
INT3 (Noise filter)
Port 2 INT4
ALU
PSW
RAR
RAM
Stack pointer
On-chip-debugger
No.A1622-8/25
LC87F2R04A
Pin Description
Pin Name
I/O
Description
Option
VSS1
-
- power supply pins
No
VDD1
-
+ power supply pin
No
Port 0
I/O
• 8-bit I/O port
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
Yes
• Pin functions
P06: Timer 6 toggle output
P07: Timer 7 toggle output
P00(AN0) to P06(AN6): AD converter input
P05(DBGP00) to P07(DBGP02): On-chip debugger 0 port
Port 1
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O/INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
P16: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input
P17: INT1 input/HOLD reset input/timer 0H capture input
Yes
P15(DBGP10) to P13(DBGP12): On-chip debugger 1 port
Interrupt acknowledge types
Port 2
I/O
Rising &
Rising
Falling
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
Falling
H level
L level
• 2-bit I/O port
• I/O specifiable in 1-bit units
P20 to P21
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20 to P21: INT4 input/HOLD reset input/timer 0L capture input/ timer 0H capture input
Yes
Interrupt acknowledge types
INT4
Port 7
I/O
Rising
Falling
enable
enable
Rising &
Falling
enable
H level
L level
disable
disable
• 1-bit I/O port
• I/O specifiable in 1-bit units
P70
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P70(AN8): AD converter input
No
Interrupt acknowledge types
INT0
Rising
Falling
enable
enable
Rising &
Falling
disable
H level
L level
enable
enable
RES
I/O
External reset Input/internal reset output
No
CF1
I
• Ceramic resonator oscillator input pin
No
• Pin function
General-purpose input port
CF2
I/O
• Ceramic resonator oscillator output pin
No
• Pin function
General-purpose input port
No.A1622-9/25
LC87F2R04A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option selected in
units of
Option type
P00 to P07
1 bit
1
P10 to P17
1 bit
P20 to P21
P70
1 bit
-
Output type
Pull-up resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
No
Nch-open drain
Programmable
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching
between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or P04 to 07).
User Option Table
Option Name
Option Type
Port output type
P00 to P07
Mask version
Flash Version
*1


Option Selected
Option Selection
in Units of
1 bit
CMOS
Nch-open drain
P10 to P17


1 bit
CMOS
P20 to P21


1 bit
CMOS
-
×

-
00000h
Nch-open drain
Nch-open drain
Program start
address
*2
Low-voltage
01E00h
Detect function


-
Detect level


-
7-level
Power-On reset level


-
8-level
Enable: Use
detection reset
function
Power-on reset
Disable: Not Used
function
*1: Mask option selection-No change possible after mask is completed.
*2: Program start address of the mask version is 00000h.
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Port Name
Board
Software
P00 to P07
Open
Output low
P10 to P17
Open
Output low
P20 to P21
Open
Output low
P70
Open
Output low
CF1
Pulled low with a 100kΩ resistor or less
General-purpose input port
CF2
Pulled low with a 100kΩ resistor or less
General-purpose input port
On-chip Debugger Pin Connection Requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87
on-chip debugger installation manual" and "LC872000 series on-chip debugger pin connection requirements"
Notes on CF1 and CF2 Pins
• When using as general-purpose input ports
Since the CF1 and CF2 pins are configured as CF oscillator pins at system reset time, it is necessary to add a current
limiting resistor of 1kΩ or greater to the CF2 pin in series when using them as general-purpose input pins.
No.A1622-10/25
LC87F2R04A
Differences between LC872G00 and LC872R00 Series.
System Reset Time State
After System Reset is Released
Flash ROM version
CF1/XT1
Set high via the internal Rf resistor
CF oscillation state
LC87F2G08A
CF2/XT2
Set high
CF oscillation state
Mask ROM version
CF1/XT1
Set low via the internal Rf resistor
CF oscillation state
LC872G08A
CF2/XT2
Set low
CF oscillation state
Flash ROM version
CF1
Set low via the internal Rf resistor
CF oscillation state
LC87F2R04A
CF2
High-impedance (OPEN)
CF oscillation state
Mask ROM version
LC872R04A
Power Pin Treatment Recommendations (VDD1, VSS1)
Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins:
• Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead
wires, making sure that the impedances between the both pins and the bypass capacitors are as possible (L1=L1’ ,
L2=L2’).
• Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should approximately 0.1μF.
L2
L1
VSS1
C1
C2
VDD1
L1’
L2’
No.A1622-11/25
LC87F2R04A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Maximum supply
VDD max
VDD1
Input voltage
VI
CF1, CF2
Input/output
VIO
Ports 0, 1, 2
voltage
voltage
High level output current
Peak output
P70
IOPH
Mean output
CMOS output select
Per 1 applicable pin
IOMH
Ports 0, 1, 2
current
typ
max
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
unit
V
-10
CMOS output select
Per 1 applicable pin
-7.5
-20
(Note 1-1)
Total output
ΣIOAH(1)
P10 to P14
Total of all applicable pins
current
ΣIOAH(2)
P15 to P17
Total of all applicable pins
Ports 0, 2
Peak output
ΣIOAH(3)
Ports 0, 1, 2
Total of all applicable pins
IOPL(1)
P02 to P07
Per 1 applicable pin
current
Low level output current
Ports 0, 1, 2
current
min
Mean output
-25
20
Ports 1, 2
IOPL(2)
P00, P01
Per 1 applicable pin
30
IOPL(3)
P70
Per 1 applicable pin
10
IOML(1)
P02 to P07
Per 1 applicable pin
IOML(2)
P00, P01
Per 1 applicable pin
20
IOML(3)
P70
Per 1 applicable pin
7.5
Total output
ΣIOAL(1)
P10 to P14
Total of all applicable pins
50
current
ΣIOAL(2)
Ports 0, 2
Total of all applicable pins
60
P15 to P17
Power
ΣIOAL(3)
Ports 0, 1, 2
Total of all applicable pins
70
ΣIOAL(4)
P70
Total of all applicable pins
7.5
Pd max(1)
MFP24S(300mil))
Ta=-40 to +85°C
Dissipation
129
Package only
Pd max(2)
Ta=-40 to +85°C
Package with thermal
229
resistance board
(Note 1-2)
Pd max(3)
SSOP24(225mil)
mW
Ta=-40 to +85°C
111
Package only
Pd max(4)
mA
15
Ports 1, 2
current
(Note 1-1)
-20
Ta=-40 to +85°C
Package with thermal
334
resistance board
(Note 1-2)
Operating ambient
Topr
Temperature
Storage ambient
temperature
Tstg
-40
+85
-55
+125
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1622-12/25
LC87F2R04A
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Operating
VDD(1)
supply voltage
VDD(2)
VDD1
VHD
VDD1
sustaining
typ
max
unit
0.245μs ≤ tCYC ≤ 200μs
2.7
5.5
0.294μs ≤ tCYC ≤ 200μs
2.2
5.5
(Note 2-1)
Memory
min
RAM and register contents sustained
in HOLD mode.
1.6
supply voltage
High level
VIH(1)
input voltage
Ports 1, 2
P70 port input/
2.2 to 5.5
0.3VDD+0.7
VDD
2.2 to 5.5
0.3VDD+0.7
VDD
2.2 to 5.5
0.9VDD
VDD
interrupt side
VIH(2)
Port 0
VIH(3)
Port 70 watchdog
timer side
Low level
VIH(4)
CF1, RES
2.2 to 5.5
0.75VDD
VDD
VIL(1)
Ports 1, 2,
4.0 to 5.5
VSS
0.1VDD+0.4
2.2 to 4.0
VSS
0.2VDD
4.0 to 5.5
VSS
0.15VDD+0.4
2.2 to 4.0
VSS
0.2VDD
2.2 to 5.5
VSS
0.8VDD-1.0
2.2 to 5.5
VSS
0.25VDD
2.7 to 5.5
0.245
200
2.2 to 5.5
0.294
200
2.7 to 5.5
0.1
12
2.2 to 5.5
0.1
10
input voltage
P70 port input/
interrupt side
VIL(2)
VIL(3)
Port 0
Port 70 watchdog
timer side
VIL(4)
Instruction
tCYC
cycle time
(Note 2-2)
CF1, RES
(Note 2-1)
External
V
FEXCF
CF1
• CF2 pin open
μs
• System clock frequency division
system clock
frequency
ratio=1/1
• External system clock duty=50±5%
MHz
• CF2 pin open
• System clock frequency division
ratio=1/2
3.0 to 5.5
0.2
24.4
• External system clock duty=50±5%
Oscillation
FmCF(1)
CF1, CF2
frequency
range
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
(Note 2-3)
10MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
2.7 to 5.5
12
2.2 to 5.5
10
2.2 to 5.5
4
4MHz ceramic oscillation.
CF oscillation normal amplifier size selected.
(CFLAMP=0)
See Fig. 1
MHz
4MHz ceramic oscillation.
CF oscillation low amplifier size
selected. (CFLAMP=1)
2.2 to 5.5
4
See Fig. 1.
FmMRC
Frequency variable RC oscillation.
1/2 frequency division ration.
2.7 to 5.5
7.6
8.0
8.4
2.2 to 5.5
0.5
1.0
2.0
(RCCTD=0) (Note 2-4)
FmRC
Internal medium-speed RC oscillation
Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Note 2-4: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the
multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
No.A1622-13/25
LC87F2R04A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2
Output disabled
P70
Pull-up resistor off
RES
VIN=VDD
(Including output Tr's off leakage
min
typ
max
unit
2.2 to 5.5
1
2.2 to 5.5
15
current)
IIH(2)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disabled
P70
Pull-up resistor off
RES
VIN=VSS
(Including output Tr's off leakage
IIL(2)
CF1
VIN=VSS
High level output
VOH(1)
Ports 0, 1, 2
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
IOH=-0.35mA
2.7 to 5.5
VDD-0.4
IOH=-0.15mA
2.2 to 5.5
VDD-0.4
Low level input
current
2.2 to 5.5
-1
2.2 to 5.5
-15
μA
current)
VOH(3)
Low level output
VOL(1)
voltage
VOL(2)
Ports 0, 1, 2
VOL(3)
4.5 to 5.5
1.5
IOL=1.4mA
2.7 to 5.5
0.4
IOL=0.8mA
2.2 to 5.5
0.4
IOL=1.4mA
2.7 to 5.5
0.4
IOL=0.8mA
2.2 to 5.5
0.4
IOL=25mA
4.5 to 5.5
1.5
VOL(7)
IOL=4mA
2.7 to 5.5
0.4
VOL(8)
IOL=2mA
2.2 to 5.5
0.4
VOH=0.9VDD
When Port 0 selected
4.5 to 5.5
15
35
80
low-impedance pull-up.
2.2 to 4.5
18
50
230
VOH=0.9VDD
When Port 0 selected
2.2 to 5.5
VOL(4)
P70
VOL(5)
VOL(6)
Pull-up resistance
IOL=10mA
Rpu(1)
Rpu(2)
Rpu(3)
P00, P01
Ports 0, 1, 2
P70
Port 0
V
kΩ
100
210
400
high-impedance pull-up.
Hysteresis voltage
VHYS(1)
VHYS(2)
Pin capacitance
CP
Ports 1, 2
2.7 to 5.5
0.1VDD
2.2 to 5.5
0.07VDD
2.2 to 5.5
10
P70
RES
All pins
V
For pins other than that under test:
VIN=VSS
f=1MHz
pF
Ta=25°C
No.A1622-14/25
LC87F2R04A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = 0V (Note 4)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Specification
Pin/
Conditions
Remarks
SCK1(P15)
VDD[V]
See Fig. 5.
2.2 to 5.5
pulse width
High level
tSCK(4)
SCK1(P15)
• CMOS output selected
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with respect
(1/3)tCYC
to rising edge of SIOCLK.
• See Fig. 5.
Data hold time
unit
1
2.2 to 5.5
pulse width
High level
max
1
• See Fig. 5.
Low level
typ
tCYC
tSCKH(3)
Frequency
min
2
pulse width
Output clock
Serial clock
Parameter
thDI(2)
+0.01
2.2 to 5.5
0.01
Output delay time
tdD0(4)
SO1(P13),
Serial output
SB1(P14)
μs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
(1/2)tCYC
2.2 to 5.5
+0.05
change in open drain output
mode.
• See Fig. 5.
Note 4: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P17),
• Event inputs for timer 0 or 1 are
INT2(P16),
enabled.
min
typ
2.2 to 5.5
1
2.2 to 5.5
2
max
unit
INT4(P20 to P21),
tPIH(2)
INT3(P15) when noise
• Interrupt source flag can be set.
tPIL(2)
filter time constant is
• Event inputs for timer 0 are
1/1
enabled.
tPIH(3)
INT3(P15) when noise
• Interrupt source flag can be set.
tPIL(3)
filter time constant is
• Event inputs for timer 0 are
1/32
INT3(P15) when noise
• Interrupt source flag can be set.
tPIL(4)
filter time constant is
• Event inputs for timer 0 are
tPIL(5)
RES
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
200
enabled.
tPIH(4)
1/128
tCYC
enabled.
• Resetting is enabled.
μs
No.A1622-15/25
LC87F2R04A
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
12bits AD Converter Mode
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN6(P06),
Conversion time
• See Conversion time calculation
TCAD
formulas.
(Note 6-2)
Analog input
typ
2.4 to 5.5
(Note 6-1)
AN8(P70)
accuracy
min
VAIN
voltage range
max
unit
12
bit
2.7 to 5.5
±16
2.4 to 5.5
±20
4.0 to 5.5
32
115
2.7 to 5.5
64
115
2.4 to 5.5
410
425
2.4 to 5.5
VSS
VDD
Analog port
IAINH
VAIN=VDD
2.4 to 5.5
input current
IAINL
VAIN=VSS
2.4 to 5.5
LSB
μs
V
1
μA
-1
8bits AD Converter Mode
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN6(P06)
Conversion time
(Note 6-1)
formulas.
(Note 6-2)
Analog input
max
VAIN
voltage range
4.0 to 5.5
unit
8
bit
±1.5
2.4 to 5.5
• See Conversion time calculation
TCAD
typ
2.4 to 5.5
AN8(P70)
accuracy
min
20
90
2.7 to 5.5
40
90
2.4 to 5.5
250
265
2.4 to 5.5
VSS
VDD
Analog port
IAINH
VAIN=VDD
2.4 to 5.5
input current
IAINL
VAIN=VSS
2.4 to 5.5
LSB
1
-1
μs
V
μA
Conversion time calculation formulas:
12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)× (1/3)×tCYC
External
Operating supply
oscillation
voltage range
(FmCF)
(VDD)
System division ratio
Cycle time
(SYSDIV)
(tCYC)
4.0V to 5.5V
1/1
3.0V to 5.5V
1/1
AD division
AD conversion time
(TCAD)
ratio
(ADDIV)
12bit AD
8bit AD
250ns
1/8
34.8μs
21.5μs
250ns
1/16
69.5μs
42.8μs
CF-12MHz
4.0V to 5.5V
1/1
300ns
1/8
41.8μs
25.8μs
3.0V to 5.5V
1/1
300ns
1/16
83.4μs
51.4μs
3.0V to 5.5V
1/1
750ns
1/8
104.5μs
64.5μs
2.4V to 5.5V
1/1
750ns
1/32
416.5μs
256.5μs
CF-10MHz
CF-4MHz
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A1622-16/25
LC87F2R04A
Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1= 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
POR release
• Select from option.
PORRL
voltage
Detection
(Note 7-1)
min
typ
max
1.67V
1.55
1.67
1.79
1.97V
1.85
1.97
2.09
2.07V
1.95
2.07
2.19
2.37V
2.25
2.37
2.49
2.57V
2.45
2.57
2.69
2.87V
2.75
2.87
2.99
3.86V
3.73
3.86
3.99
4.35V
4.21
4.35
4.49
0.7
0.95
unit
V
• See Fig. 7.
POUKS
(Note 7-2)
voltage
unknown state
Power supply
• Power supply rise
PORIS
rise time
100
time from 0V to 1.6V.
ms
Note7-1: The POR release level can be selected out of 4 levels only when the LVD reset function is disabled.
Note7-2: POR is in an unknown state before transistors start operation.
Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
LVD reset Voltage
LVDET
(Note 8-2)
• Select from option.
(Note 8-1)
(Note 8-3)
• See Fig. 8.
LVD hysteresis
LVHYS
width
Detection voltage
LVUKS
unknown state
Low voltage
detection
minimum Width
min
max
1.91V
1.81
1.91
2.01
2.01V
1.91
2.01
2.11
2.31V
2.21
2.31
2.41
2.51V
2.41
2.51
2.61
2.81V
2.71
2.81
2.91
3.79V
3.69
3.79
3.89
4.28V
4.18
4.28
4.38
1.91V
55
2.01V
55
2.31V
55
2.51V
55
2.81V
60
3.79V
65
4.28V
65
• See Fig. 8.
0.7
(Note 8-4)
TLVDW
typ
unit
V
mV
0.95
V
• LVDET-0.5V
• See Fig. 9.
0.2
ms
(Reply sensitivity)
Note8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled.
Note8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4: LVD is in an unknown state before transistors start operation.
No.A1622-17/25
LC87F2R04A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
Specification
Pin/
Conditions
Remarks
VDD1
VDD[V]
min
typ
max
unit
• FmCF=12MHz ceramic oscillation mode
consumption
• System clock set to 12MHz side
current
• Internal medium speed RC oscillation
2.7 to 5.5
6.1
10
2.7 to 3.6
3.7
6.4
2.2 to 5.5
5.3
9.1
2.2 to 3.6
3.4
5.8
2.2 to 5.5
2.6
5.5
2.2 to 3.6
1.9
3.4
stopped.
(Note 9-1)
• Frequency variable RC oscillation stopped.
(Note 9-2)
• 1/1 frequency division ratio
IDDOP(2)
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal medium speed RC oscillation
stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal medium speed RC oscillation
stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(4)
• CF oscillation low amplifier size selected.
(CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
mA
2.2 to 5.5
1.1
2.1
2.2 to 3.6
0.56
1.1
2.2 to 5.5
0.47
1.2
2.2 to 3.6
0.28
0.65
2.7 to 5.5
4.2
8.1
2.7 to 3.6
3.3
5.6
• System clock set to 4MHz side
• Internal medium speed RC oscillation
stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDOP(5)
• External FmCF oscillation stopped.
• System clock set to internal medium speed
RC oscillation.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(6)
• External FmCF oscillation stopped.
• Internal medium speed RC oscillation
stopped.
• System clock set to 8MHz with frequency
variable RC oscillation.(RCCTD=0)
• 1/1 frequency division ratio.
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A1622-18/25
LC87F2R04A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(1)
Specification
Pin/
Conditions
Remarks
VDD1
VDD[V]
consumption
• FmCF=12MHz ceramic oscillation mode
current
• System clock set to 12MHz side
(Note 9-1)
• Internal medium speed RC oscillation
(Note 9-2)
min
typ
max
unit
• HALT mode
2.7 to 5.5
2.3
4.1
2.7 to 3.6
1.2
1.9
2.2to 5.5
1.9
3.4
2.2 to 3.6
1.0
1.6
2.2 to 5.5
1.3
2.5
2.2 to 3.6
0.53
1.0
stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• HALT mode
IDDHALT(2)
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal medium speed RC oscillation
stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• HALT mode
IDDHALT(3)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal medium speed RC oscillation
stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• HALT mode
IDDHALT(4)
mA
• CF oscillation low amplifier size selected.
2.2 to 5.5
0.80
1.5
2.2 to 3.6
0.31
0.62
2.2 to 5.5
0.28
0.73
2.2 to 3.6
0.14
0.36
2.7 to 5.5
1.3
2.7
2.7 to 3.6
0.93
1.8
2.2 to 5.5
0.03
25
2.2 to 3.6
0.02
5.9
5.0
0.03
1.2
3.3
0.02
0.56
2.5
0.01
0.40
2.2 to 5.5
3.0
29
2.2 to 3.6
2.3
10
5.0
3.0
7.3
• Ta=-10 to +50°C
3.3
2.3
3.4
• LVD option selected
2.5
2.0
2.9
(CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal medium speed RC oscillation
stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
• HALT mode
IDDHALT(5)
• External FmCF oscillation stopped.
• System clock set to internal medium speed
RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• HALT mode
IDDHALT(6)
• External FmCF oscillation stopped.
• Internal medium speed RC oscillation
stopped.
• System clock set to 8MHz with frequency
variable RC oscillation. (RCCTD=0)
• 1/1 frequency division ratio.
HOLD mode
IDDHOLD(1)
VDD1
HOLD mode
• CF1=VDD or open (External clock mode)
consumption
current
(Note 9-1)
IDDHOLD(2)
HOLD mode
• CF1=VDD or open (External clock mode)
(Note 9-2)
• Ta=-10 to +50°C
IDDHOLD(3)
HOLD mode
• CF1=VDD or open (External clock mode)
• LVD option selected
IDDHOLD(4)
HOLD mode
• CF1=VDD or open (External clock mode)
μA
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
No.A1622-19/25
LC87F2R04A
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Onboard
IDDFW(1)
VDD1
min
typ
max
unit
• Only current of the flash block.
programming
2.2 to 5.5
5
10
mA
20
30
ms
40
60
μs
current
Programming
tFW(1)
• Erasing time
time
tFW(2)
• Programming time
2.2 to 5.5
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
• CF oscillation normal amplifier size selected (CFLAMP=0)
MURATA
Nominal
Frequency
12MHz
Circuit Constant
Type
SMD
SMD
Oscillator Name
CSTCE12M0G52-R0
CSTCE10M0G52-R0
C1
C2
[pF]
[pF]
(10)
(10)
Rf
Operating
Rd
Voltage Range
[V]
Oscillation
Stabilization Time
typ
max
[Ω]
[Ω]
[ms]
[ms]
Open
680
2.2 to 5.5
0.1
0.5
0.5
Remarks
(10)
Open
1.0k
2.5 to 5.5
0.1
Open
680
2.0 to 5.5
0.1
0.5
Open
1.0k
2.1 to 5.5
0.1
0.5
(10)
10MHz
LEAD
SMD
CSTLS10M0G53-B0
CSTCE8M00G52-R0
(15)
(10)
Open
680
2.2 to 5.5
0.1
0.5
Open
1.0k
2.4 to 5.5
0.1
0.5
Open
1.0k
1.9 to 5.5
0.1
0.5
(15)
(10)
Open
1.5k
2.0 to 5.5
0.1
0.5
Open
1.0k
2.0 to 5.5
0.1
0.5
Internal
Open
1.5k
2.2 to 5.5
0.1
0.5
C1,C2
Open
1.5k
1.9 to 5.5
0.1
0.5
8MHz
LEAD
SMD
CSTLS8M00G53-B0
CSTCR6M00G53-R0
(15)
(15)
(15)
(15)
Open
2.2k
2.0 to 5.5
0.1
0.5
Open
1.5k
2.0 to 5.5
0.1
0.5
Open
2.2k
2.1 to 5.5
0.1
0.5
Open
1.5k
1.8 to 5.5
0.2
0.6
Open
3.3k
1.9 to 5.5
0.2
0.6
Open
1.5k
1.8 to 5.5
0.2
0.6
Open
3.3k
1.9 to 5.5
0.2
0.6
6MHz
LEAD
SMD
CSTLS6M00G53-B0
CSTCR4M00G53-R0
(15)
(15)
(15)
(15)
4MHz
LEAD
CSTLS4M00G53-B0
(15)
(15)
No.A1622-20/25
LC87F2R04A
• CF oscillation low amplifier size selected (CFLAMP=1)
MURATA
Nominal
Frequency
Circuit Constant
Type
Oscillator Name
CSTCR4M00G53-R0
C1
C2
[pF]
[pF]
(15)
Rf
Operating
Voltage Range
Rd
[V]
Oscillation
Stabilization Time
typ
max
[Ω]
[Ω]
[ms]
[ms]
Open
1.0k
1.9 to 5.5
0.2
0.6
Open
2.2k
2.1 to 5.5
0.2
0.6
Open
1.0k
1.8 to 5.5
0.2
0.6
Remarks
(15)
SMD
CSTCR4M00G53095-R0
(15)
(15)
Open
2.2k
1.9 to 5.5
0.2
0.6
Internal
Open
1.0k
2.0 to 5.5
0.2
0.6
C1,C2
Open
2.2k
2.1 to 5.5
0.2
0.6
Open
1.0k
1.8 to 5.5
0.2
0.6
Open
2.2k
1.9 to 5.5
0.2
0.6
4MHz
CSTLS4M00G53-B0
(15)
(15)
LEAD
CSTLS4M00G53095-B0
(15)
(15)
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 3).
• Time till the oscillation gets stabilized after the CPU reset state is released.
• Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed.
• Till the oscillation gets stabilized after the HOLD mode is reset.
(Notes on the implementation of the oscillator circuit)
• Oscillation is influenced by the circuit pattern layout of printed circuit board. Place the oscillation-related
components as close to the CPU chip and to each other as possible with the shortest possible pattern length.
• Keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator
circuit as possible and make sure that they do not cross one another.
• Be sure to insert a current limiting resistor (Rd) so that the oscillation amplitude never exceeds the input voltage
level that is specified as the absolute maximum rating.
• The oscillator circuit constants shown above are sample characteristic values that are measured using the Our
designated oscillation evaluation board. Since the accuracy of the oscillation frequency and other characteristics vary
according to the board on which the IC is installed, it is recommended that the user consult the resonator vendor for
oscillation evaluation of the IC on a user's production board when using the IC for applications that require high
oscillation accuracy. For further information, contact your resonator vendor or Our company Semiconductor sales
representative serving your locality.
• It must be noted, when replacing the flash ROM version of a microcontroller with a mask ROM version, that their
operating voltage ranges may differ even when the oscillation constant of the external oscillator is the same.
CF1
CF2
Rf
Rd
C1
C2
CF
Figure 1 CF Oscillator Circuit
0.5VDD
Figure 2 AC Timing Measurement Point
No.A1622-21/25
LC87F2R04A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal medium speed
RC oscillation
tmsCF
CF1
CF2
Unpredictable
Operating mode
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal medium speed
RC oscillation
tmsCF
CF1, CF2
(Note)
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Note: External oscillation circuit is selected.
Figure 3 Oscillation Stabilization Times
No.A1622-22/25
LC87F2R04A
VDD
Note:
External circuits for reset may vary
depending on the usage of POR and LVD.
Please refer to the user’s manual for more
information..
RRES
RES
CRES
Figure 4 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 5 Serial I/O Output Waveforms
tPIL
tPIH
Figure 6 Pulse Input Timing Signal Waveform
No.A1622-23/25
LC87F2R04A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
100μs or longer
Reset period
Unknown-state
(POUKS)
RES
Figure 7 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Unknown-state
(LVUKS)
RES
Figure 8 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
No.A1622-24/25
LC87F2R04A
VDD
LVD release voltage
LVD reset voltage
LVDET-0.5V
TLVDW
VSS
Figure 9 Low voltage detection minimum width
(Example of momentary power loss / Voltage variation waveform)
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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PS No.A1622-25/25
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