ENA2330 D

Ordering number : ENA2330
LC74735YW
CMOS LSI
On-Screen Display Controller
http://onsemi.com
Overview
The LC74735YW is an on-screen display CMOS IC that displays characters and patterns on a TV screen. For
QVGA display, the LC74735YW supports the use of both a 12  18 dot character font and a 12  18 dot graphics
font with 16 colors with a total of 512 characters and glyphs. For WVGA display, the LC74735YW supports the use
of both a 24  32 dot character font and a 12  16 dot graphics font with 16 colors with a total of 512 characters and
glyphs. The LC74735YW can also implement extremely varied displays by the use of an external ROM. The
LC74735YW supports both QVGA (480  234) and WVGA (800  480).
Features
 Screen structure
— Main :
QVGA mode: 40 characters 13 lines (up to 520 characters) on a QVGA panel
WVGA mode: 33 characters 15 lines (up to 495 characters) on a WVGA panel
— Wallpaper display screen: Permanent repetition of a 2 2 (horizontal vertical) character pattern
 Character structure
— QVGA mode :
12 dots (horizontal) 18 dots (vertical) : Character display
12 dots (horizontal) 18 dots (vertical) : Graphic glyph display
— WVGA mode:
24 dots (horizontal) 32 dots (vertical) : Character display
12 dots (horizontal) 16 dots (vertical) : Graphic glyph display (1 pixel : 2 2 dots)
— Character display clock:
About 9 MHz — QVGA with an LC oscillator 33.2 MHz (maximum: 40 MHz)
WVGA with an external clock signal input
*: The ROM image is known when QVGA or WVGA mode is specified.
 Number of characters: 512 (internal)
Up to 2048 characters when an external 16-bit 4M ROM is used.
 Character sizes: Four horizontal sizes (1, 2, 3, and 4)
Four vertical sizes (1, 2, 3, and 4)
(The character size is specified in line units.)
 Display start positions : 512 positions in the horizontal direction and 256 positions in the vertical direction.
QVGA mode WVGA mode Setting units : Horizontal : 1 dot 2 dots (In screen units)
Vertical: 1 dot 2 dots (In screen units)
 Display functions
— Blinking specification (in character units)
Period : 1/64, 1/32, and 1/16 of the vertical sync signal (in screen units)
Duty : Fixed at 50%
— Box (raised or recessed) display
Raised/recessed specification (in character units)
Left
: Off/on specification (in character units)
Right : Off/on specification (in character units)
Top
: Off/on specification (in character units)
Bottom : Off/on specification (in character units)
— Border specification (in line units) :
Only valid with glyphs from the character font.
 Color specification
SQFP80(12X12)
Character
— Character color (in character units) : 1 of 16 colors can be specified.
— Character background color (in character units) : 1 of 16 colors can be specified.
— Border color (in line units) : 1 of 16 colors can be specified.
Semiconductor Components Industries, LLC, 2013
July, 2013
hk 20110413-S00004/ O1003TN(OT) No.A2330-1/52
LC74735YW
 Graphic
— 16 types can be specified by ROM data
 Box color (line units) : 1/16 colors
 Background color (screen units) : 1/16 colors
 Color table (palette)
— Sixteen colors can be selected from a set of 512 colors (One of which is specified to be transparent.)
— Number of color tables: 2. This allows up to 32 colors to be displayed at the same time.
 Wallpaper screen (Graphics glyphs only)
Wallpaper display
: Repeated display under the main screen (2 characters horizontally by 2 characters
vertically)
Sprite character display : Displayed above the main screen (2 characters horizontally by 2 characters vertically)
 Output
— QVGA
Analog RGB output
BLK (OSD display period signal)
— WVGA
Digital RGB output (3 bits per color)
BLK (OSD display period signal)
 Package : SQFP80
 Voltage : 3.3 V
Package Dimensions
unit : mm
SPQFP80 12x12 / SQFP80
CASE 131AL
ISSUE A
0.5±0.2
14.0±0.2
1 2
14.0±0.2
12.0±0.1
12.0±0.1
0.135
+0.05
0.5
0.2 −0.04
+0.055
0.045
0.10
1.6 MAX
(1.4)
(1.25)
0.1±0.1
0~10°
0.10
GENERIC MARKING DIAGRAM*
SOLDERING FOOTPRINT*
13.40
XXXXXXXX
YMDDD
XXXXXXXX
YDD
13.40
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.28
1.00
may or may not be present.
0.50
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
No.A2330-2/52
LC74735YW
VDD3
VSS3
A0
A1
A2
A3
A4
A5
A6
A7
VDD3
VSS3
A8
A9
A10
A11
A12
A13
A14
A15
Pin Assignments
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
54 D0
VDD1
8
53 D1
VSYNC
9
52 D2
VBLK
10
51 D3
HSYNC
11
50 D4
HBLK
12
49 D5
TEST1
13
48 D6
TEST2
14
47 D7
RST
15
46 VDD1
VSS1
16
45 VSS1
VDD1
17
44 D8
CLKOUT
18
43 D9
VSS1
19
42 D10
VDD1
20
41 D11
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS2
7
RREF
CS
CVREF
55 VSS3
CCOMP
6
BOUT
SIN
GOUT
56 VDD3
ROUT
5
OUTR
SCLK
VDD2
57 OE
VSS1
4
BLK
CTRL1
BD0
58 CE
BD1
3
BD2
OSCout
GD0
59 A17
GD1
2
GD2
OSCin
RD0
60 A16
RD1
1
RD2
VSS1
Top view
No. 7545-3/52
LC74735YW
Pin Functions
Pin No.
Symbol
1
VSS1
Type
Functional description
Ground
Connect a ground to this pin. (Digital system ground)
LC oscillator
Connect to the character output dot clock generator oscillator coil and capacitor.
May also be used for external clock input.
2
OSCin
3
OSCout
4
CTRL1
OSCin oscillator input control
Switches between external clock input mode and LC oscillator mode.
Low: LC oscillator, high: external clock input MORE+
5
SCLK
Clock input
Clock input for the serial data input system
MORE+ (This input has hysteresis characteristics.)
6
SIN
Data input
Serial data input
MORE+ (This input has hysteresis characteristics.)
7
CS
Enable input
Enable input for the serial data input system. Serial data input is enabled when this pin is set low.
MORE+ (This input has hysteresis characteristics.)
8
VDD1
Power supply (+3.3 V)
Digital system power supply: +3.3 V
9
VSYNC
Vertical sync signal input
Vertical sync signal input
MORE+ (This input has hysteresis characteristics.)
10
VBLK
Vertical blanking signal input
Vertical blanking signal input
MORE+ (This input has hysteresis characteristics.)
11
HSYNC
Horizontal sync signal input
Horizontal sync signal input
MORE+ (This input has hysteresis characteristics.)
12
HBLK
Horizontal blanking signal input
Horizontal blanking signal input
MORE+ (This input has hysteresis characteristics.)
13
TEST1
Test mode control 1
Test mode control 1
Low: normal operation, high: test mode MORE+
14
TEST2
Test mode control 2
Test mode control 2
Low: normal operation, high: test mode (scan mode) MORE+
15
RST
Reset input
System reset input
MORE+ (This input has hysteresis characteristics.)
16
VSS1
Ground
Connect a ground to this pin. (Digital system ground)
17
VDD1
Power supply (+3.3 V)
Power supply: (+3.3 V: Digital system)
18
CLKOUT
19
Clock output
Clock output
VSS1
Ground
Connect a ground to this pin. (Digital system ground)
20
VDD1
Power supply (+3.3 V)
Power supply: (+3.3 V: Digital system)
21
RD2
Rout output: bit 2
22
RD1
Rout output: bit 1
Rout output: bit 0
Rout output
This is a 3-bit digital output with values from 000 to 111.
23
RD0
24
GD2
Gout output: bit 2
25
GD1
Gout output: bit 1
26
GD0
Gout output: bit 0
27
BD2
Bout output: bit 2
28
BD1
Bout output: bit 1
29
BD0
Bout output: bit 0
30
BLK
Blanking signal output
This signal indicates the OSD display period.
31
VSS1
Ground
Connect a ground to this pin. (Digital system ground)
32
VDD2
Power supply (+3.3 V)
Power supply: (+3.3 V: D/A converter)
33
OUTR
Outr output: analog
Output. Connect a resistor Ro (68 Ω) to this pin.
34
Rout
Rout output: analog
D/A converter (3 bits) output. Connect a resistor Ro to this pin.
35
Gout
Gout output: analog
D/A converter (3 bits) output. Connect a resistor Ro to this pin.
36
Bout
Bout output: analog
D/A converter (3 bits) output. Connect a resistor Ro to this pin.
37
CCOMP
Phase correction capacitor connection Capacitor connection: 1.5 µF
38
CVREF
Reference voltage output
Capacitor connection: 0.1 µF
39
RREF
Reference resistor connection
Connect a reference register to this pin.
40
VSS2
Ground
Connect a ground to this pin. (D/A converter ground)
Gout output
This is a 3-bit digital output with values from 000 to 111.
Bout output
This is a 3-bit digital output with values from 000 to 111.
Continued on next page.
No. 7545-4/52
LC74735YW
Continued from preceding page.
Pin No.
Symbol
41
D11
Data input 11
Type
ROM data input 11. MORE+
Functional description
42
D10
Data input 10
ROM data input 10. MORE+
43
D9
Data input 9
ROM data input 9. MORE+
44
D8
Data input 8
ROM data input 8. MORE+
45
VSS1
Ground
Connect a ground to this pin. (Digital system ground)
46
VDD1
Power supply (+3.3 V)
Power supply: (+3.3 V: Digital system)
47
D7
Data input 7
ROM data input 7. MORE+
48
D6
Data input 6
ROM data input 6. MORE+
49
D5
Data input 5
ROM data input 5. MORE+
50
D4
Data input 4
ROM data input 4. MORE+
51
D3
Data input 3
ROM data input 3. MORE+
52
D2
Data input 2
ROM data input 2. MORE+
53
D1
Data input 1
ROM data input 1. MORE+
54
D0
Data input 0
ROM data input 0. MORE+
55
VSS3
Ground
Connect a ground to this pin. (External ROM output system ground)
56
VDD3
Power supply (+3.3 or +5.5 V)
Power supply (External ROM output system power supply)
57
OE
Output enable
ROM output enable output. This is an active low output.
58
CE
Chip enable
ROM chip enable output. This is an active low output.
59
A17
Address output 17
ROM address output 17
60
A16
Address output 16
ROM address output 16
61
A15
Address output 15
ROM address output 15
62
A14
Address output 14
ROM address output 14
63
A13
Address output 13
ROM address output 13
64
A12
Address output 12
ROM address output 12
65
A11
Address output 11
ROM address output 11
66
A10
Address output 10
ROM address output 10
67
A9
Address output 9
ROM address output 9
68
A8
Address output 8
ROM address output 8
69
VSS3
Ground
Connect a ground to this pin. (External ROM output system ground)
70
VDD3
Power supply (+3.3 or +5.5 V)
Power supply (External ROM output system power supply)
71
A7
Address output 7
ROM address output 7
72
A6
Address output 6
ROM address output 6
73
A5
Address output 5
ROM address output 5
74
A4
Address output 4
ROM address output 4
75
A3
Address output 3
ROM address output 3
76
A2
Address output 2
ROM address output 2
77
A1
Address output 1
ROM address output 1
78
A0
Address output 0
ROM address output 0
79
VSS3
Ground
Connect a ground to this pin. (External ROM output system ground)
80
VDD3
Power supply (+3.3 or +5.5 V)
Power supply (External ROM output system power supply)
No. 7545-5/52
LC74735YW
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Supply voltage
Input voltage
Maximum power dissipation
Ratings
Unit
VDD1, VDD2
VSS – 0.3 to VSS + 4.6
VDD3
VDD3
VSS – 0.3 to VSS + 6.0
V
All input pins
VSS – 0.3 to VDD1 + 0.3
V
VOUT1
RD2 to 0, GD2 to 0, BD2 to 0, and BLK outputs
VSS – 0.3 to VDD1 + 0.3
V
VOUT2
A0 to A17, CE, OE outputs
VSS – 0.3 to VDD1 + 0.3
VIN
Output voltage
Conditions
VDD1
Pdmax
230
V
V
mW
Operating temperature
Topg
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Recommended Operating Conditions
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Oscillator frequency
External clock input
Symbol
Ratings
min
typ
Unit
max
VDD1
VDD1, VDD2
3.0
3.3
3.6
VDD3
VDD3
3.0
3.3
5.5
V
VIH1
CTRL1, TEST1, TEST2
0.7 VDD1
—
5.5
V
VIH2
SCLK, SIN, CS, VSYNC, HSYNC, RST
0.8 VDD1
—
5.5
V
VIH3
D0 to D11
0.7 VDD1
—
5.5
V
VIL1
CTRL1, TEST1, TEST2
VSS – 0.3
—
0.3 VDD1
V
VIL2
SCLK, SIN, CS, VSYNC, HSYNC, RST
VSS – 0.3
—
0.2 VDD1
V
VIL3
D0 to D11
VSS – 0.3
—
0.3 VDD1
—
10
—
FOSC1
FOSC2
VIN1
Vrefda
D/A converter (3 bit, 3 ch)
When maximum output voltage =
0.7 V
Conditions
Rfda
Rfbda
Rref
OSCin and OSCout oscillator pins (LC oscillator)
OSCin, VDD1 = 3.3 V
VDD1 = 3.3 V, CTRL1 = high
Reference voltage
Output load resistance ROUT, GOUT, and BOUT
Output load resistance OUTR
Reference load resistance, RREF
V
V
MHz
—
33
40
MHz
0.5
—
3.3
Vp-p
—
1.1
—
V
120
—
225
Ω
40
—
75
Ω
1232
—
2310
Ω
No. 7545-6/52
LC74735YW
Electrical Characteristics at Ta = –30 to +70°C, VDD = 3.3 V unless otherwise specified.
Parameter
Output high-level voltage
Output low-level voltage
Input current
Operating current drain
Pin
VOH1
RD2 to 0, GD2 to 0, BD2 to 0,
and BLK outputs
VDD1 = 3.0 V
IOH1 = –8 mA
VDD1 – 0.8
—
—
V
VOH2
A0 to 17, CE, and OE
VDD3 = 3.0 V
IOH2 = –8 mA
VDD3 – 0.8
—
—
V
VOH3
A0 to 17, CE, and OE
VDD3 = 4.5 V
IOH3 = –8 mA
VDD3 – 0.8
—
—
V
VOL1
RD2 to 0, GD2 to 0, BD2 to 0,
and BLK outputs
VDD1 = 3.0 V
IOL1 = 8 mA
—
—
0.4
V
VOL2
A0 to 17, CE, and OE
VDD3 = 3.0 V
IOL2 = 8 mA
—
—
0.4
V
VOL3
A0 to 17, CE, and OE
VDD3 = 4.5 V
IOL3 = 8 mA
—
—
0.4
V
IIH1
CTRL1, TEST1, TEST2,
SCLK, SIN, CS, VSYNC,
HSYNC, RST
VIN = VDD1
—
—
10
µA
IIH2
D0 to 11
VIN = VDD3
—
—
10
µA
IIL1
CTRL1, TEST1, TEST2,
SCLK, SIN, CS, VSYNC,
HSYNC
VIN = VSS
–10
—
—
µA
IIL2
D0 to 11
VIN = VSS
–10
—
—
µA
IDD1
VDD1
All outputs open
OSCin: 40 MHz
—
—
37
mA
IDD2
VDD2
D/A on
IDD3
VDD3
CLK
D/A converter
Conditions
Ratings
Symbol
Clock frequency
min
typ
Unit
max
—
—
22
mA
—
—
20
mA
—
—
20
MHz
Vmax
Maximum output voltage
VDD2 = 3.3 V
0.25
—
1.5
V
Vmin
Minimum output voltage
VDD2 = 3.3 V
—
0
—
V
No. 7545-7/52
LC74735YW
Timing Characteristics
OSD Write (See figure 1.) at Ta = –30 to +70°C, VDD1 = 3.3 ± 0.3 V
Parameter
Symbol
tw (sclk)
Minimum input pulse width
Data setup time
Data hold time
min
SCLK
typ
max
Unit
200
—
—
1
—
—
µs
CS
200
—
—
ns
tsu (sin)
SIN
200
—
—
ns
th (cs)
CS
2
—
—
µs
th (sin)
SIN
200
—
—
ns
The time to write 8 bits of data
4.2
—
—
µs
1
—
—
µs
tw (cs)
CS (The period CS is high)
tsu (cs)
tword
One word write time
Ratings
Conditions
twt
RAM data write time
ns
Supplementary Materials
tw(cs)
CS
tsu(cs)
tw(sclk)
tw(sclk)
tsu(sin)
th(sin)
th(cs)
SCLK
SIN
CS
tword
twt
SCLK
0
1
5
6
7
0
1
4
5
6
7
Figure 1 OSD Serial Data Input Timing
No. 7545-8/52
LC74735YW
System Block Diagram
VDD1, VDD2,VDD3
CS
SIN
SCLK
Serial-toparallel
converter
VSS1,VSS2,VSS3
16-bits
latch
+
command
decoder
RST
Horizontal
direction
control register
HSYNC
HBLK
Address
control circuit
Horizontal
direction
counter
VRAM
Vertical
direction
control register
Address
control circuit
HSYNC
HBLK
OE, CE
External ROM
control circuit
A0-17
Vertical
direction
counter
RAM and ROM
read and write
control
D0-11
FROM
RD2-0
GD2-0
Output control circuit
Character
size control
BD2-0
BLK
OUTR
OSCin
OSCout
Timing
generator
ROUT
D/A
GOUT
BOUT
CTRL1
CCOMP
CVREF
RREF
No. 7545-9/52
LC74735YW
Display Control Commands
The display control commands have serial input format that consists of 8-bit units transmitted LSB first. A commands
consists of a command identification code in the first byte and data in the second and following bytes. Both a first byte
and a second byte (16 bits) must be transmitted for each command. Commands 10, 11, and 71 set the IC to continuous
write mode. (Continuous write mode is cleared by setting the CS pin high.)
Display Control Command Table
First byte
Command
Second byte
Command identification code
Data
Data
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Command00 (Write address)
Main
1
0
0
0
0
0
V3
V2
V1
V0
H5
H4
H3
H2
H1
H0
Command01 (Write address)
Sub (Wallpaper)
1
0
0
0
0
1
0
0
0
SV0
0
0
0
0
0
SH0
1
0
0
1
0
0
RM2 RM1(1)
0
(2) CB3
Command 10 (Character write)
Main
1
0
0
1
0
1
0
at
BXS
BXL
BXR
BXU
BXD
CB2
CB1
CB0
CC3
CC2
CC1
CC0
(3)
0
0
CT0
I/E
M/G
C10
C9
C8
(4)
C7
C6
C5
C4
C3
C2
C1
C0
RM2 RM1(1)
0
0
0
0
0
0
0
0
(2)
0
0
0
0
0
0
0
0
(3)
0
0
CT0
I/E
M/G
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
Command 11 (Character write)
Sub (Wallpaper)
(4)
Command20 (System control)
1
0
1
0
0
0
0
0
TSTMD2 TSTMD1 Q/W2 Q/W1 SYSRST CTERS SRMERS MRMERS
Command21 (Display control)
1
0
1
0
0
0
0
1
LCSOFF BK1
Command22 (I/O polarity control 1)
1
0
1
0
0
0
1
0
BLD1 BLO0 BLOP BLO1 BLO0 CKP
Command23 (Screen background color)
1
0
1
0
0
0
1
1
Command24 (I/O polarity control 2)
1
0
1
0
0
1
0
0
DSPMD1 DSPMD0 DASEL VBLKON HBLKON CKOP VBP
Command25 (Output control)
1
0
1
0
0
1
0
1
CEHSL TOKSL VIPSL OTM2 OTM1 OTM0 QRM1 QRM0
Command30
(Vertical display start position: main)
1
0
1
1
0
0
0
0
VPM7 VPM6 VPM5 VPM4 VPM3 VPM2 VPM1 VPM0
Command31
(Horizontal display start position: main)
1
0
1
1
0
0
1
Command32
(Vertical display start position: sub)
1
0
1
1
0
1
0
Command33
(Horizontal display start position: sub)
1
0
1
1
0
1
1
Command34
(Vertical display start position: screen)
1
0
1
1
1
0
0
Command35
(Horizontal display start position: screen)
1
0
1
1
1
0
1
Command40
(Character size control)
1
1
0
0
0
0
0
0
0
0
0
0
Command41
(Character size control: line setting U)
1
1
0
0
0
1
0
0
LSZ7
LSZ6
LSZ5
LSZ4
LSZ1
LSZ0
Command42
(Character size control: line setting D)
1
1
0
0
1
0
0
0
LSZ15 LSZ14 LSZ13 LSZ12 LSZ11 LSZ10 LSZ9
LSZ8
Command50
(Box control U)
1
1
0
1
0
0
0
0
BXUW BXLW
0
BXUCT0 BXUC3 BXUC2 BXUC1 BXUC0
Command51
(Box control D)
1
1
0
1
0
1
0
0
BXDW BXRW
0
BXDCT0 BXDC3 BXDC2 BXDC1 BXDC0
Command52
(Box control: line setting U)
1
1
0
1
1
0
0
0
LBX7
LBX1
LBX0
Command53
(Box control: line setting D)
1
1
0
1
1
1
0
0
LBX15 LBX14 LBX13 LBX12 LBX11 LBX10 LBX9
LBX8
Command60
(Border control)
1
1
1
0
0
0
BLK1
BLK0
0
0
0
Command61
(Border control: line setting U)
1
1
1
0
0
1
0
0
LFC7
LFC6
LFC5
LFC1
LFC0
Command62
(Border control: line setting D)
1
1
1
0
1
0
0
0
LFC15 LFC14 LFC13 LFC12 LFC11 LFC10 LFC9
LFC8
Command70 (Write address)
Color table
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
Command71 (Data write)
Color table
0
0
BK0 SBG1 SBG0 DSPBG DSPGS DSPGM
VIP
HIP
BGCT1 BGCT0 BGC3 BGC2 BGC1 BGC0
HBP
HPM8 HPM7 HPM6 HPM5 HPM4 HPM3 HPM2 HPM1 HPM0
0
VPS7 VPS6 VPS5 VPS4 VPS3 VPS2 VPS1 VPS0
HPS8 HPS7 HPS6 HPS5 HPS4 HPS3 HPS2 HPS1 HPS0
0
VPG7 VPG6 VPG5 VPG4 VPG3 VPG2 VPG1 VPG0
HPG8 HPG7 HPG6 HPG5 HPG4 HPG3 HPG2 HPG1 HPG0
LBX6
LBX5
0
LBX4
SZV1 SZV0 SZH1 SZH0
LSZ3
LBX3
LSZ2
LBX2
EGCT0 EGC3 EGC2 EGC1 EGC0
LFC4
LFC3
LFC2
0
0
CTN1 CTA3 CTA2 CTA1 CTA0
RMB(1)
0
0
0
0
TCK
TB2
TB1
TB0
(2)
0
0
TG2
TG1
TG0
TR2
TR1
TR0
No. 7545-10/52
LC74735YW
Command 00 (Main screen write address set command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 0 identification code
5
—
0
Main screen write address setting
4
—
0
State
3
—
0
2
—
0
1
V3
<MSB>
0
0
V2
Function
Notes
Sub-identification code: 0
1
0
1
• Second byte
DA0 to 7
Register
7
V1
Content
State
Function
0
Main screen memory line address
1
(0 to E, hexadecimal)
V0
<LSB>
0
QVGA mode: 13 lines
1
WVGA mode: 15 lines
5
H5
<MSB>
0
4
H4
3
H3
6
2
H2
1
H1
0
H0
<LSB>
Notes
1
0
1
0
Main screen memory character position address
1
(00 to 27, hexadecimal)
0
QVGA mode: 40 characters
1
WVGA mode: 33 characters
0
1
0
1
No. 7545-11/52
LC74735NW
Command 01 (Subscreen write address set command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 0 identification code
5
—
0
Subscreen memory write address setting
4
—
0
State
3
—
0
2
—
1
1
—
0
0
—
0
Function
Notes
Sub-identification code: 1
• Second byte
Content
DA0 to 7
Register
7
—
6
V0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
H0
<LSB>
0
Subscreen memory character address
1
(0 to 1, hexadecimal) 2 characters
State
Function
Notes
0
0
Subscreen memory line address
1
(0 to 1, hexadecimal) 2 lines
No. 7545-12/52
LC74735YW
Command 10 (Main screen display character data write setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 1 identification code
5
—
0
Display character data write setting
4
—
1
State
3
—
0
2
—
0
1
RM2
When this command has been issued, the IC
remains in display character data write mode until
the CS pin is set high.
Sub-identification code 0
0
RM2
RM1
1
0
0
(1)(2)(3)(4)
End
0
1
(1)(2)(3)(4)
Continuous
1
0
(3)(4)
Continuous
1
1
(2)(3)(4)
Continuous
0
0
Notes
Function
RM1
1
Mode
Continuous write mode selection
• Second byte (1)
Content
DA0 to 7
Register
7
—
0
6
—
0
5
at
4
BXS
3
BXL
2
BXR
1
BXU
0
BXD
State
Notes
Function
0
Blinking off
1
Blinking on
0
Raised
1
Recessed
0
None
1
Box displayed
0
None
1
Box displayed
0
None
1
Box displayed
0
None
1
Box displayed
Blinking specification
Box specification: raised/recessed
Box specification: left side
Box specification: right side
Box specification: upper
Box specification: lower
• Second byte (2)
DA0 to 7
Register
7
CB3
[MSB]
6
CB2
Content
State
1
0
1
0
CB1
4
CB0
[LSB]
0
3
CC3
[MSB]
0
2
CC2
CC1
0
CC0
<LSB>
Notes
0
5
1
Function
Character background color specification
0000 to 1111, or 0 to F (hexadecimal)
Character background color specification
When a character glyph is specified, 1 of 16 colors
may be selected.
Character color specification
0000 to 1111, or 0 to F (hexadecimal)
Character color specification
When a character glyph is specified, 1 of 16 colors
may be selected.
1
1
1
0
1
0
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-13/52
LC74735YW
• Second byte (3)
Content
DA0 to 7
Register
7
—
0
6
—
0
5
CT0
4
I/E
3
M/G
2
C10
[MSB]
1
C9
0
C8
State
Notes
Function
0
Color table number 1
1
Color table number 2
0
Internal ROM
1
External ROM
0
Character
1
Graphic
Color table selection
ROM selection
Character/graphic specification
0
1
0
Character code specification
1
0
1
• Second byte (4)
DA0 to 7
Register
7
C7
6
C6
5
C5
4
C4
3
C3
2
C2
1
C1
0
C0
[LSB]
Content
State
Function
Notes
0
1
0
1
0
1
Character code
Internal ROM: 512 characters
000 to 1FF (hexadecimal)
0 to 511
0
1
0
External ROM: 2048 characters
000 to 7FF (hexadecimal)
0 to 2047
Character code specification
1
0
1
0
* Transparent character specification
I/E = 0 (Internal ROM)
M/G = 0 (Character)
Code = 1FF (hexadecimal)
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-14/52
LC74735YW
Command 11 (Subscreen display character data write setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 1 identification code
5
—
0
Display character data write setting
4
—
1
State
3
—
0
2
—
1
1
RM2
When this command has been issued, the IC
remains in display character data write mode until
the CS pin is set high.
Sub-identification code 1
0
RM2
RM1
1
0
0
[1][2][3][4]
End
0
1
[1][2][3][4]
Continuous
1
0
[3][4]
Continuous
1
1
[2][3][4]
Continuous
0
0
Notes
Function
RM1
1
Mode
Continuous write mode selection
• Second byte (1)
Content
DA0 to 7
Register
7
—
0
6
—
0
State
5
0
4
0
3
0
2
0
1
0
0
0
Function
Notes
• Second byte (2)
DA0 to 7
Register
Content
State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Function
Notes
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-15/52
LC74735YW
• Second byte (3)
Content
DA0 to 7
Register
7
—
0
6
—
0
5
CT0
4
I/E
3
M/G
2
C10
[MSB]
1
C9
0
C8
State
Notes
Function
0
Color table number 1
1
Color table number 2
Color table selection
0
Internal ROM
1
External ROM
0
Only when transparent is selected
1
Graphic only
ROM selection
Graphic only
0
1
0
Character code specification
1
0
1
• Second byte (4)
DA0 to 7
Register
7
C7
6
C6
5
C5
4
C4
3
C3
2
C2
1
C1
0
C0
[LSB]
Content
State
Function
Notes
0
1
0
1
0
1
Character code
Internal ROM: 512 characters
000 to 1FF (hexadecimal)
0 to 511
0
1
0
External ROM: 2048 characters
000 to 7FF (hexadecimal)
0 to 2047
Character code specification
1
0
1
0
* Transparent character specification
I/E = 0 (Internal ROM)
M/G = 0 (Character)
Code = 1FF (hexadecimal)
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-16/52
LC74735YW
Command 20 (System control setting command)
• First byte
DA0 to 7
Register
7
—
6
—
Content
State
Notes
Function
1
0
Command 2 identification code
5
1
System control settings
4
0
3
0
2
0
1
0
0
0
Sub-identification code 0
• Second byte
DA0 to 7
Register
7
TSTMD2
6
TSTMD1
5
Q/W2
4
Q/W1
3
SYSRST
2
CTERS
1
SRMERS
0
MRMERS
Content
State
0
Normal operation
1
Test mode 2
0
Normal operation
1
Test mode 1
0
Normal mode
1
Independent mode
0
QVGA mode
D/A converter on, 40 characters × 13 lines
1
WVGA mode
D/A converter off, 33 characters × 15 lines
Do not use test mode. This bit must always be set
to 0.
Do not use test mode. This bit must always be set
to 0.
Normal / Independent
Specified by COM24.
0
1
QVGA / WVGA
Reset all registers (All bits set to 0.)
The registers are reset when the CS pin is low.
The reset state is cleared when the CS pin goes high.
Erase the color table. (Sets all values to 00.)
Applications must provide a wait time of about 1ms.
Use DSPOFF to execute this operation.
0
1
Notes
Function
0
1
Erase main RAM. (Sets all values to 00.)
Wallpaper
Applications must provide a wait time of about 1ms.
Use DSPOFF to execute this operation.
0
1
Erase sub-RAM. (Sets all values to 00.)
Main screen
Applications must provide a wait time of about 1ms.
Use DSPOFF to execute this operation.
No. 7545-17/52
LC74735YW
Command 21 (Display control setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 2 identification code
5
—
1
Display control
4
—
0
3
—
0
2
—
State
0
1
0
0
1
Notes
Function
Extended command 1 identification code
• Second byte
DA0 to 7
Register
7
LCSOFF
6
BK1
5
BK0
4
SBG1
3
SBG0
2
DSPBG
1
DSPGS
0
DSPGM
Content
State
Notes
Function
0
Enables stopping the LC oscillator
LC oscillator on/off control
1
Disables stopping the LC oscillator
Valid when the display is off.
0
1
0
1
BK1
0
0
1
BK0
0
1
0
Blinking period
1/16
1/32
1/64
0
Display after the main screen
1
Display before the main screen
0
Iterated display (wallpaper)
1
Horizontal 2-character x vertical 2-character display (sprite)
0
Display off
1
Display on
0
Display off
1
Display on
0
Display off
1
Display on
Blinking period
Specified for screen units.
Subscreen display specification
Subscreen display specification
Screen background color
Subscreen (wallpaper)
Main screen
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-18/52
LC74735YW
Command 22 (I/O polarity control setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 2 identification code
5
—
1
I/O polarity control 1
4
—
0
3
—
0
2
—
State
0
1
1
0
0
Notes
Function
Extended command 2 identification code
• Second byte
DA0 to 7
Register
7
BLD1
6
BLD0
5
BLOP
4
BLO1
3
BLO0
2
CKP
1
VIP
0
HIP
Content
State
0
1
0
1
BLD1
0
0
1
1
BLD0
0
1
0
1
BLY output delay
±0
+1
+2
+3
0
BLK output: positive polarity
1
BLK output: negative polarity
0
1
0
1
Notes
Function
BLO1
0
0
1
1
BLO0
0
1
0
1
BLK output
Text + character background + wallpaper + screen background
Text + character background + wallpaper
Text + character background
Text
0
Clock input: positive polarity
1
Clock input: negative polarity
0
VSYNC input: negative polarity
1
VSYNC input: positive polarity
0
HSYNC input: negative polarity
1
HSYNC input: positive polarity
BLK output delay setting
In dot clock units
BLK output polarity selection
BLK output control
Clock input polarity selection
VSYNC input polarity selection
HSYNC input polarity selection
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-19/52
LC74735YW
Command 23 (Screen background color setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 2 identification code
5
—
1
Screen background color
4
—
0
3
—
0
2
—
State
0
1
1
0
1
Notes
Function
Extended command 3 identification code
• Second byte
Content
DA0 to 7
Register
7
—
0
6
—
0
5
BGCT1
4
BGCT0
3
BGC3
2
BGC2
1
BGC1
0
BGC0
State
0
1
0
1
Notes
Function
T1
0
0
1
T0
0
1
X
Color table setting
Color table No. 2
Invalid setting
Color table No. 1
Screen background color
Color table setting
0
1
0
1
0
Screen background color
0000 to 1111
0 to F (hexadecimal)
Screen background color
Selects 1 of 16 values.
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-20/52
LC74735YW
Command 24 (I/O polarity control setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 2 identification code
5
—
1
I/O polarity control 2
4
—
0
3
—
0
2
—
State
1
1
0
0
0
Notes
Function
Extended command 4 identification code
• Second byte
DA0 to 7
Register
7
DSPMD1
6
DSPMD0
5
D/ASEL
4
VBLKON
3
HBLKON
2
CKOP
1
VBP
0
HBP
Content
State
0
1
0
1
Notes
Function
MD1
0
0
1
MD0
0
1
0
Main screen display area
40 characters × 13 lines
33 characters × 15 lines
40 characters × 16 lines
0
On
1
Off
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Clock output positive polarity
1
Clock output negative polarity
0
VBLK input negative polarity
1
VBLK input positive polarity
0
HBLK input negative polarity
1
HBLK input positive polarity
Main screen display area selection
Only valid in independent mode.
COM20 to COM2
*: In WVGA mode: fixed 33-character × 15-line
display
D/A converter used/unused selection
Only valid in independent mode. COM20 to COM2
VBLK input selection
HBLK input selection
Clock output polarity selection
VBLK input polarity selection
HBLK input polarity selection
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-21/52
LC74735YW
Command 25 (Output control 3 setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 2 identification code
5
—
1
Output control
4
—
0
3
—
0
2
—
State
1
1
0
0
1
Notes
Function
Extended command 5 identification code
• Second byte
DA0 to 7
Register
7
CEHSL
6
TOKSL
5
VIPSL
4
OTMD2
3
OTMD1
2
OTMD0
1
QRM1
Content
State
0
Normal operation
1
CE pin held fixed at the high level
0
Normal mode
1
Transmissive mode
The color specified at address 0 in color table No. 1 is displayed
in the transmissive state.
0
Falling edge detection
1
Rising edge detection
0
Output off state (always low)
1
Normal output
0
1
0
1
0
1
0
0
QRM0
1
Notes
Function
OTMD2
0
0
0
0
OTMD1
0
0
1
1
QRM1
0
0
1
1
QRM0
0
1
0
1
CE pin
Transmissive mode specification
Selects the detection polarity for the VSYNC signal.
OTMD0
0
1
0
1
CLKOUT pin (pin 18)
Output control
Output
Normal
RGB No. 1
RGB No. 2
High-impedance state
ROM selection
ROM1
ROM2
ROM3
ROM4
A0 to 17 output selection
ROM selection when character output is specified
in QVGA mode
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
• When RGB No. 1 or RGB No. 2 is selected:
The A17 to 9 output is set to the RD2 to BD0 three-value output. (Supported by connecting external resistors.)
* It will not be possible to use external ROM in this case. (Only internal ROM can be used.)
No. 1: RGB = 000 = Black only. Here the output will go to the high-impedance state giving the middle level due to the external resistor.
For areas other than the display area, the output will be at the low level.
No. 2: When any individual color is zero, the output will go to the high-impedance state giving the middle level due to the external resistor.
For areas other than the display area, the output will be at the low level.
No. 7545-22/52
LC74735YW
Command 30 (Main screen: vertical display start position setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 3 identification code
5
—
1
Main screen: vertical display start position setting
4
—
1
3
—
0
2
—
0
1
—
0
0
—
0
State
Notes
Function
Extended command 0 identification code
• Second byte
Register
7
VPM7
(MSB)
6
VPM6
5
VPM5
4
VPM4
3
VPM3
2
VPM2
1
VPM1
0
VPM0
(LSB)
Content
State
Notes
Function
0
1
0
1
The vertical display start position, VSM, is given by:
7
VSM = 1H × ( ∑ 2 n V P M n )
n=0
0
Main screen
HSYNC
1
The vertical display start position is specified by the
8 bits VPM7 to 0.
0
1
0
1
0
VSM
VSYNC
DA0 to 7
The weight of the LSB is 1H in QVGA mode, and
the weight of the LSB is 2H in WVGA mode
HSM
Main screen display area
This setting applies in screen units.
1
0
1
0
1
No. 7545-23/52
LC74735YW
Command 31 (Main screen: horizontal display start position setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 3 identification code
5
—
1
Main screen: horizontal display start position setting
4
—
1
3
—
0
2
—
0
1
—
1
0
HPM8
(MSB)
0
State
Notes
Function
Extended command 1 identification code
1
• Second byte
DA0 to 7
Register
7
HPM7
6
HPM6
5
4
HPM5
HPM4
3
HPM3
2
HPM2
1
HPM1
0
HPM0
(LSB)
Content
State
Notes
Function
0
1
0
1
0
1
The horizontal display start position, HSM, is given by:
8
HSM = 1Tc × ( ∑ 2 n H P M n ) + α
n=0
α = 57 Tc
0
1
Tc: The input clock frequency in operating mode.
Main screen
The horizontal display start position is specified by
the 9 bits HPM8:0.
The weight of the LSB is 1TC in QVGA mode, and
0
the weight of the LSB is 2TC in WVGA mode
1
0
• Setting disable range
1
QVGA : 00 to 07 HEX
0
WVGA : 00 to 07 HEX
This setting applies in screen units.
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-24/52
LC74735YW
Command 32 (Subscreen: vertical display start position setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 3 identification code
5
—
1
Subscreen: vertical display start position setting
4
—
1
3
—
0
2
—
1
1
—
0
0
—
0
State
Notes
Function
Extended command 2 identification code
• Second byte
Register
7
VPS7
(MSB)
6
VPS6
5
VPS5
4
VPS4
3
VPS3
2
VPS2
1
VPS1
0
VPS0
(LSB)
Content
State
Notes
Function
0
1
0
1
The vertical display start position, VSS, is given by:
7
VSS = 1H × ( ∑ 2 n V P S n )
n=0
0
Subscreen (wallpaper)
HSYNC
1
The vertical display start position is specified by the
8 bits VPS7 to 0.
0
VSS
1
0
1
0
VSYNC
DA0 to 7
The weight of the LSB is 1H in QVGA mode, and
the weight of the LSB is 2H in WVGA mode
HSS
Subscreen display area
This setting applies in screen units.
1
0
1
0
1
No. 7545-25/52
LC74735YW
Command 33 (Subscreen: horizontal display start position setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 3 identification code
5
—
1
Subscreen: horizontal display start position setting
4
—
1
3
—
0
2
—
1
0
State
1
Function
Notes
Extended command 3 identification code
1
HPS8
(MSB)
0
1
• Second byte
DA0 to 7
Register
7
HPS7
6
HPS6
5
4
HPS5
HPS4
3
HPS3
2
HPS2
1
HPS1
0
HPS0
(LSB)
Content
State
Function
Notes
0
1
0
1
0
1
The horizontal display start position, HSS, is given by:
8
HSS = 1Tc × ( ∑ 2 n H P S n ) + α
n=0
α = 14 Tc
0
1
Tc: The input clock frequency in operating mode.
Subscreen (wallpaper)
The horizontal display start position is specified by
the 9 bits HPS8 to 0.
The weight of the LSB is 1TC in QVGA mode, and
0
the weight of the LSB is 2TC in WVGA mode
1
0
1
This setting applies in screen units.
• Setting disable range
0
QVGA : 00 to 2F HEX
1
WVGA : 00 to 17 HEX
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-26/52
LC74735YW
Command 34 (Screen background color: vertical display start position setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 3 identification code
5
—
1
Screen background color: vertical display start position setting
4
—
1
3
—
1
2
—
0
1
—
0
0
—
0
State
Notes
Function
Extended command 4 identification code
• Second byte
Register
7
VPG7
(MSB)
6
VPG6
5
VPG5
4
VPG4
3
VPG3
2
VPG2
1
VPG1
0
VPG0
(LSB)
Content
State
Notes
Function
0
1
0
1
The vertical display start position, VSG, is given by:
7
VSG = 1H × ( ∑ 2 n V P G n )
n=0
0
Screen background color
HSYNC
1
The vertical display start position is specified by
the 8 bits VPG7 to 0.
0
VSG
1
0
1
0
VSYNC
DA0 to 7
The weight of the LSB is 1H in QVGA mode, and
the weight of the LSB is 2H in WVGA mode
HSG
Screen background
color display area
This setting applies in screen units.
1
0
1
0
1
No. 7545-27/52
LC74735YW
Command 35 (Screen background color: horizontal display start position setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
0
Command 3 identification code
5
—
1
Screen background color: horizontal display start position setting
4
—
1
3
—
1
2
—
1
0
State
0
Function
Notes
Extended command 5 identification code
1
HPS8
(MSB)
0
1
• Second byte
DA0 to 7
Register
7
HPG7
6
HPG6
5
HPG5
4
HPG4
3
HPG3
2
HPG2
1
HPG1
0
HPG0
(LSB)
Content
State
Function
Notes
0
1
0
1
The horizontal display start position, HSG, is given by:
8
0
HSG = 1Tc × ( ∑ 2 n H P G n )
1
Tc: The input clock frequency in operating mode.
n=0
0
Screen background color
1
The horizontal display start position is specified by
the 9 bits HPG8 to 0.
0
The weight of the LSB is 1TC in QVGA mode, and
1
the weight of the LSB is 2TC in WVGA mode
0
This setting applies in screen units.
1
0
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-28/52
LC74735YW
Command 40 (Character size control setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 4 identification code
5
—
0
Display character data write settings
4
—
0
3
—
0
2
—
0
State
1
0
0
0
Function
Notes
Extended command 0 identification code
• Second byte
Content
DA0 to 7
Register
7
—
0
6
—
0
5
—
0
4
—
0
3
SZV1
State
0
1
0
2
SZV0
1
SZH1
1
0
1
0
0
SZH0
1
Function
Notes
SZV1
0
0
1
1
SZV0
0
1
0
1
Character size
1×
2×
3×
4×
Specifies the character size in the vertical direction.
This setting applies in line units.
SZH1
0
0
1
1
SZH0
0
1
0
1
Character size
1×
2×
3×
4×
Specifies the character size in the horizontal
direction.
This setting applies in line units.
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-29/52
LC74735YW
Command 41 (Character size line U control setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 4 identification code
5
—
0
Character size line U control
4
—
0
State
3
—
0
2
—
1
1
—
0
0
—
0
Function
Notes
Extended command 1 identification code
• Second byte
DA0 to 7
Register
7
LSZ7
6
5
4
3
2
1
0
LSZ6
LSZ5
LSZ4
LSZ3
LSZ2
LSZ1
LSZ0
Content
State
Function
0
Do not set for line 8.
1
Set for line 8.
0
Do not set for line 7.
1
Set for line 7.
0
Do not set for line 6.
1
Set for line 6.
0
Do not set for line 5.
1
Set for line 5.
0
Do not set for line 4.
1
Set for line 4.
0
Do not set for line 3.
1
Set for line 3.
0
Do not set for line 2.
1
Set for line 2.
0
Do not set for line 1.
1
Set for line 1.
Notes
Character size line setting control
Upper lines
No. 7545-30/52
LC74735YW
Command 42 (Character size line D control setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 4 identification code
5
—
0
Character size line D control
4
—
0
State
3
—
1
2
—
0
1
—
0
0
—
0
Function
Notes
Extended command 2 identification code
• Second byte
DA0 to 7
Register
7
LSZ15
6
5
4
3
2
1
0
LSZ14
LSZ13
LSZ12
LSZ11
LSZ10
LSZ9
LSZ8
Content
State
Function
0
Do not set for line 16.
1
Set for line 16.
0
Do not set for line 15.
1
Set for line 15.
0
Do not set for line 14.
1
Set for line 14.
0
Do not set for line 13.
1
Set for line 13.
0
Do not set for line 12.
1
Set for line 12.
0
Do not set for line 11.
1
Set for line 11.
0
Do not set for line 10.
1
Set for line 10.
0
Do not set for line 9.
1
Set for line 9.
Notes
Character size line setting control
Lower lines
No. 7545-31/52
LC74735YW
Command 50 (Box control: U setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 5 identification code
5
—
0
Box control U settings
4
—
1
State
3
—
0
2
—
0
1
—
0
0
—
0
Function
Notes
Extended command 0 identification code
• Second byte
DA0 to 7
Register
7
BXUW
6
BXLW
5
—
4
BXUCT0
3
BXUC3
2
BXUC2
1
BXUC1
0
BXUC0
Content
State
Function
0
Box display: upper side is 1 dot.
1
Box display: upper side is 2 dots.
0
Box display: left side is 1 dot.
1
Box display: left side is 2 dots.
Notes
Box display: upper side
Dot width. This setting applies in line units.
Box display: left side
Dot width. This setting applies in line units.
0
0
Color table No. 1
1
Color table No. 2
Box display: upper side
Color table specification
This setting applies in line units.
Box display: upper side color specification
0000 to 1111
0 to F (hexadecimal)
Box display: upper side
Color specification
This setting applies in line units.
0
1
0
1
0
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-32/52
LC74735YW
Command 51 (Box control: D setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 5 identification code
5
—
0
Box control D settings
4
—
1
State
3
—
0
2
—
1
1
—
0
0
—
0
Function
Notes
Extended command 1 identification code
• Second byte
DA0 to 7
Register
7
BXDW
6
BXRW
5
—
4
BXDCT0
3
BXDC3
2
BXDC2
1
BXDC1
0
BXDC0
Content
State
Function
0
Box display: lower side is 1 dot.
1
Box display: lower side is 2 dots.
0
Box display: right side is 1 dot.
1
Box display: right side is 2 dots.
Notes
Box display: lower side
Dot width. This setting applies in line units.
Box display: right side
Dot width. This setting applies in line units.
0
0
Color table No. 1
1
Color table No. 2
Box display: lower side
Color table specification
This setting applies in line units.
Box display: lower side color specification
0000 to 1111
0 to F (hexadecimal)
Box display: lower side
Color specification
This setting applies in line units.
0
1
0
1
0
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-33/52
LC74735YW
Command 52 (Box control: U line setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 5 identification code
5
—
0
Box control U line setting
4
—
1
State
3
—
1
2
—
0
1
—
0
0
—
0
Function
Notes
Extended command 2 identification code
• Second byte
DA0 to 7
Register
7
LBX7
6
5
4
3
2
1
0
LBX6
LBX5
LBX4
LBX3
LBX2
LBX1
LBX0
Content
State
Function
0
Do not set for line 8.
1
Set for line 8.
0
Do not set for line 7.
1
Set for line 7.
0
Do not set for line 6.
1
Set for line 6.
0
Do not set for line 5.
1
Set for line 5.
0
Do not set for line 4.
1
Set for line 4.
0
Do not set for line 3.
1
Set for line 3.
0
Do not set for line 2.
1
Set for line 2.
0
Do not set for line 1.
1
Set for line 1.
Notes
Box control line setting control
Upper lines
No. 7545-34/52
LC74735YW
Command 53 (Box control: D line control setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 4 identification code
5
—
0
Box control D line setting
4
—
0
State
3
—
1
2
—
1
1
—
0
0
—
0
Function
Notes
Extended command 3 identification code
• Second byte
DA0 to 7
Register
7
LBX15
6
5
4
3
2
1
0
LBX14
LBX13
LBX12
LBX11
LBX10
LBX9
LBX8
Content
State
Function
0
Do not set for line 16.
1
Set for line 16.
0
Do not set for line 15.
1
Set for line 15.
0
Do not set for line 14.
1
Set for line 14.
0
Do not set for line 13.
1
Set for line 13.
0
Do not set for line 12.
1
Set for line 12.
0
Do not set for line 11.
1
Set for line 11.
0
Do not set for line 10.
1
Set for line 10.
0
Do not set for line 9.
1
Set for line 9.
Notes
Box control line setting control
Lower lines
No. 7545-35/52
LC74735YW
Command 60 (Border control setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 6 identification code
5
—
1
Border control setting
4
—
0
State
3
—
0
2
—
0
1
BLK1
0
BLK0
0
1
0
1
Function
Notes
Extended command 0 identification code
BLK1
0
0
1
1
BLK0
0
1
0
1
Border mode specification
Normal display
Border
Shadow 1 (lower side)
Shadow 2 (lower and right sides)
Border mode specification
This setting applies in line units.
• Second byte
Content
DA0 to 7
Register
7
—
0
6
—
0
5
—
0
4
EGCT0
3
EGC3
2
EGC2
1
EGC1
0
EGC0
State
Function
Notes
0
Color table No. 1
1
Color table No. 2
Border display
Color table specification
This setting applies in line units.
Border display: color specification
0000 to 1111
0 to F (hexadecimal)
Border display
color specification
This setting applies in line units.
0
1
0
1
0
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-36/52
LC74735YW
Command 61 (Border control U line setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 6 identification code
5
—
1
Border control U line setting
4
—
0
State
3
—
0
2
—
1
1
—
0
0
—
0
Function
Notes
Extended command 1 identification code
• Second byte
DA0 to 7
Register
7
LFC7
6
5
4
3
2
1
0
LFC6
LFC5
LFC4
LFC3
LFC2
LFC1
LFC0
Content
State
Function
0
Do not set for line 8.
1
Set for line 8.
0
Do not set for line 7.
1
Set for line 7.
0
Do not set for line 6.
1
Set for line 6.
0
Do not set for line 5.
1
Set for line 5.
0
Do not set for line 4.
1
Set for line 4.
0
Do not set for line 3.
1
Set for line 3.
0
Do not set for line 2.
1
Set for line 2.
0
Do not set for line 1.
1
Set for line 1.
Notes
Border control line settings control
Upper lines
No. 7545-37/52
LC74735YW
Command 62 (Border control D line setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 6 identification code
5
—
1
Border control D line setting
4
—
0
State
3
—
1
2
—
0
1
—
0
0
—
0
Function
Notes
Extended command 2 identification code
• Second byte
DA0 to 7
Register
7
LFC15
6
5
4
3
2
1
0
LFC14
LFC13
LFC12
LFC11
LFC10
LFC9
LFC8
Content
State
Function
0
Do not set for line 16.
1
Set for line 16.
0
Do not set for line 15.
1
Set for line 15.
0
Do not set for line 14.
1
Set for line 14.
0
Do not set for line 13.
1
Set for line 13.
0
Do not set for line 12.
1
Set for line 12.
0
Do not set for line 11.
1
Set for line 11.
0
Do not set for line 10.
1
Set for line 10.
0
Do not set for line 9.
1
Set for line 9.
Notes
Border control line settings control
Lower lines
No. 7545-38/52
LC74735YW
Command 70 (Color table write address setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 7 identification code
5
—
1
Color table write address setting
4
—
1
State
3
—
0
2
—
0
1
—
0
0
—
0
Notes
Function
Sub-identifier code 0
• Second byte
DA0 to 7
Register
7
—
6
—
5
—
4
CTN1
3
CTA3
<MSB>
2
CTA2
1
CTA1
0
CTA0
<LSB>
Content
State
Notes
Function
0
Color table No. 1 selected
1
Color table No. 2 selected
Color table selection
No. 1 or No. 2
0
1
0
1
0
Color table address
0 to 15
0 to F (hexadecimal) 16 values
Addresses of the color tables
1
0
1
No. 7545-39/52
LC74735YW
Command 71 (Color table data write setting command)
• First byte
Content
DA0 to 7
Register
7
—
1
6
—
1
Command 7 identification code
5
—
1
Display character data write setting
4
—
1
State
3
—
0
2
—
1
1
—
0
0
RM3
0
1
Notes
Function
When this command has been issued, the IC
remains in display character data write mode until
the CS pin is set high.
Sub-identifier code 1
RM3
0
1
[1][2]
[1][2]
Mode
End
Continuous
Continuous write mode selection
• Second byte (1)
Content
DA0 to 7
Register
7
—
0
6
—
0
5
—
0
4
—
0
3
TOK
2
TB2
1
TB1
0
TB0
State
Notes
Function
0
Color
1
Transparent (BLK output: low)
0
1
0
1
0
Color table
B output
000 to 111
0 to 7 (hexadecimal)
Color table setting B
1
• Second byte (2)
Content
DA0 to 7
Register
7
—
0
6
—
0
5
TG2
4
TG1
3
TG0
2
TR2
1
TR1
0
TR0
State
Notes
Function
0
1
0
1
0
Color table
G output
000 to 111
0 to 7 (hexadecimal)
Color table setting G
Color table
R output
000 to 111
0 to 7 (hexadecimal)
Color table setting R
1
0
1
0
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
When transparent is selected, the BLK output is set to the low level. (Transparent state)
The RGB outputs are values from the color table.
The transparent specification is best for color table 1, address 0000.
Since the data is set to all zeros by a RAM clear operation,
the RGB output will be 000 (black) and the BLK output will be 1.
Transparent is specified by setting the TOK bit to 1. (The BLK output will go to the low level.)
No. 7545-40/52
LC74735YW
Display Structure
The display screen consists of a 40-character × 15-line grid.
QVGA mode (12 × 18 dot characters)
40-character × 13-line QVGA panel (480 × 234)
WVGA mode (12 × 16 dot characters)
33-character × 15-line WVGA panel (800 × 480)
Up to a maximum of 600 characters can be displayed.
If the character size is increased, the number of characters that can be displayed will decrease to be fewer than 600
characters.
Display memory is addressed by specifying a line address (0 to 14 (decimal) and a character position address (0 to 39
(decimal)).
40 characters
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
15 rows
00
0
01
1
02
2
03
3
04
4
05
5
06
6
07
7
08
8
09
9
10
A
11
B
12
C
13
D
E HEX
14
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 HEX
Display Structure (Display memory address)
No. 7545-41/52
LC74735YW
Sample Application Circuits
• QVGA mode (analog output)
3.3VDC
3
4
GND
5
SCLK
6
SIN
7
CS
8
9
VSYNC
10
11
HSYNC
12
10 kΩ
16
15
17
GND
18
61
A15
63
64
62
A14
A13
A12
66
65
A11
67
A9
A10
69
70
68
A8
VSS3
VDD3
71
A7
73
74
72
A6
A5
A4
76
75
A3
A2
77
A1
78
79
A16
OSCin
A17
59
58
CE
OSCout
57
OE
CTRL1
SCLK
VDD3
SIN
VSS3
CS
D0
VDD1
D1
VSYNC
D2
LC74735YW
VBLK
D3
HSYNC
D4
HBLK
D5
TEST1
D6
TEST2
D7
RST
VDD1
VSS1
VSS1
VDD1
D8
D9
CLKOUT
55
GND
54
53
52
51
50
49
48
47
46
45
GND
44
43
42
VSS2
41
40
RREF
56
0.1 µF
39
38
CVREF
CCOMP
+
1 µF
37
BOUT
36
ROUT
GOUT
35
34
OUTR
68
33
VDD2
VSS1
32
BLK
31
30
+
GND
GND_A
GND_A
GND_A
GND_A
+
GND_A
GND_A
GND_A
GND_A
GND_A
+
GND_A
GND_A
+
GND_A
+
+
GND_A GND_A
TR3
A1392
BLK
GND_A
ROUT
BD0
29
BD1
BD2
28
27
26
25
RD0
24
21
RD2
GND
GD0
D11
GD1
VDD1
GD2
D10
23
20
VSS1
RD1
19
22
+
14
1 µF
13
60
VSS1
BOUT
2
GOUT
22 µF
1
GND
A0
GND
VDD3
GND
VSS3
80
+
No. 7545-42/52
LC74735YW
• WVGA mode (digital output)
3.3VDC
1
2
CLK
62
61
A15
A14
64
63
A13
A12
66
65
A11
A10
68
69
70
67
A9
A8
VSS3
71
A7
VDD3
72
A6
73
A5
75
74
A4
A3
77
76
A2
A1
79
78
A0
GND
VDD3
GND
VSS3
80
+
60
VSS1
A16
OSCin
A17
59
3
4
5
SCLK
6
SIN
CS
7
8
9
VSYNC
10
11
HSYNC
12
10 kΩ
13
14
16
17
GND
CE
CTRL1
OE
57
SCLK
VDD3
SIN
VSS3
CS
D0
VDD1
D1
VSYNC
D2
LC74735YW
VBLK
D3
HSYNC
D4
HBLK
D5
TEST1
D6
TEST2
D7
RST
VDD1
VSS1
VSS1
VDD1
D8
CLKOUT
D9
18
GND
GND
54
53
52
51
50
49
48
47
46
45
44
GND
43
42
41
VSS2
RREF
55
40
39
CCOMP
CVREF
38
37
GOUT
BOUT
36
35
ROUT
34
OUTR
33
VDD2
32
BLK
BD0
BD1
VSS1
31
30
29
28
GD0
BD2
27
26
GD1
25
24
23
21
GND
GD2
D11
RD0
D10
VDD1
RD1
VSS1
RD2
20
22
19
56
GND
GND_A
RD2
RD1
RD0
GD2
GD1
GD0
BD2
BD1
BD0
BLK
+
1 µF
15
58
OSCout
No. 7545-43/52
LC74735YW
Operational Description
Command transfer method
Overview
• Commands are transferred in 8-bit units, LSB first.
Always send a first byte and a second byte (16 bits).
• Command 10 (Main RAM write)
Command 11 (Wallpaper write)
Command 71 (Color table write)
When these commands specify continuous mode (RM2, 1 RM3), the IC is locked in continuous write mode.
(Continuous write mode is cleared by setting the CS pin high.)
Writing Data to VRAM
• Write start address specification
Use command 00 to set the write start address.
V3:0: Vertical direction, H5:0: Horizontal direction
• Data write
Continuous write mode differs depending on the write mode specification. (RM1, RM2)
1 Normal (RM2 = 0, RM1 = 0: initial state) *Continuous mode not used*
-- COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 command wait state -2 Write continuous (RM2 = 0, RM1 = 1): Mode 2
COM10-1 10-2-1 10-2-2 10-2-3 10-2-4
3 Write continuous (RM2 = 1, RM1 = 0): Mode 3
COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-3 10-2-4
4 Write continuous (RM2 = 1, RM1 = 1): Mode 4
COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-2 10-2-3 10-2-4
*: In modes 2, 3, and 4, the IC remains locked in continuous write mode until the CS pin is set high.
• The write address is automatically incremented.
• The write address is retained unless the IC is reset or a new write address is issued.
No. 7545-44/52
LC74735YW
Color Table write
• Write start address specification
Use command 70 to set the color table write start address.
CTN1: Color table specification (No.1, No.2), CTA3 to 0: Address specification
No.1
0000
No.2
R
G
B
XXX
XXX
XXX
0000
0001
0001
0010
0010
R
G
B
XXX
XXX
XXX
Address
1110
1110
1111
1111
• Data write
Continuous write mode differs depending on the write mode specification. (RM3)
1 Normal (RM3 = 0: initial state) *Continuous mode not used*
-- COM71-1 71-2-1 71-2-2 command wait state --2 Write continuous (RM3 = 1) mode
COM71-1 71-2-1 71-2-2
*: In mode 2, the IC remains locked in continuous write mode until the CS pin is set high.
• The write address is automatically incremented.
• The write address is retained unless the IC is reset or a new write address is issued.
No. 7545-45/52
LC74735YW
Display format
Color Specification Related Items
• When a character is specified
Specify color with the character color (character area) and character background color (outside the character area)
Character color: One of 16 colors
Character background color: One of 16 colors
Color tables: Table No. 1 or No. 2 specified by CT1 to CT0. (COM1-2-3: VRAM)
→ One of 32 types
Character color
Specified by CC0 to CC3: One of 16 colors
(COM1-2-2: VRAM)
Character background color
Specified by CB0 to CB3: One of 16 colors
(COM1-2-2: VRAM)
• When a graphic is specified
Specify color is in dot units (12 × 18 or 12 × 16)
One of 16 colors (FROM)
Color tables: Table No. 1 or No. 2 specified by CT1 to CT0. (COM1-2-3: VRAM)
→ One of 32 types
Specified by FROM: One of 16 types
No. 7545-46/52
LC74735YW
Display Control Related Items
• Blinking: In character units
Normal at1 = 0 (COM1-2-1: VRAM)
Blinking at1 = 1
Display alternates between normal and transparent with the blinking period. (COM21-2: BK1, 0)
• Border display: Only valid for font specified characters
Border color: One of 16 colors (COM60-2 EGC3 to 0)
Color table specification (COM60-2 EGCT0)
→ One of 32 types
Border mode control (COM60-1 BLK1, 0)
Border
Shadow 1: lower
Shadow 2: lower + right
• Character size: Specified in line units
The character size is specified as 1x to 4x independently for the vertical and horizontal directions.
(COM40-2)
No. 7545-47/52
LC74735YW
Box Display (raised/recessed)
Raised
12 dots
Recessed
18 dots
or
16 dots
•
•
•
•
•
•
Raised/recessed specification: In character units (COM10-2-1 BXS)
Left side - displayed/undisplayed specification: in character units (COM10-2-1 BXL)
Right side - displayed/undisplayed specification: in character units (COM10-2-1 BXR)
Upper side - displayed/undisplayed specification: in character units (COM10-2-1 BXU)
Lower side - displayed/undisplayed specification: in character units (COM10-2-1 BXD)
Color specification: In line units
COM50 (Upper side)
COM51 (Lower side)
BXUC3:0: One of 16 colors
BXDC3:0: One of 16 colors
Color table specification
BXUCT0
BXDCT0
’ One of 32 types
Dot width specification: 1 or 2 dots
Each of left, right, upper, and lower can be specified independently. (BXLW BXRW BXUW BXDW)
No. 7545-48/52
LC74735YW
Screen Structure
Screen background color
Wallpaper display screen
Main screen
• QVGA mode (12 × 18 dot characters)
40-character × 13-line QVGA panel
• WVGA mode (12 × 16 dot characters)
33-character × 15-line WVGA panel
• For each screen: Display on/off (transparent) can be specified independently.
• For each screen: The display start position can be specified independently.
The wallpaper display screen and the main screen require xxxx clocks before the horizontal start position is reached.
No. 7545-49/52
LC74735YW
Display Format
• QVGA
Character specification
12 dots
Graphic
12 dots
18H
• WVGA
Character specification
24 dots
Graphic
24 dots
Each dot is 2 × 2 pixels
(A 12 × 16 structure
magnified 2× in both
the horizontal and
vertical directions)
32H
ROM structure
Internal ROM (512 characters)
• Character font
QVGA: 12 × 18-dot structure
WVGA: 24 × 32-dot structure, i.e. 12 × 16 times 4
• Graphics
CQVGA: 12 × 18-dot structure
WVGA: 12 × 16-dot structure, i.e. displayed magnified 2× in both the horizontal and vertical directions.
Note that the contents of ROM differ for QVGA and WVGA.
(That is, different ROMs for QVGA and WVGA must be created.)
No. 7545-50/52
LC74735YW
External ROM (2048 characters)
• Conditions
Use a 16-bit 4M ROM with an access time less than 3 times the dot clock period
Example: DCLK = 50 MHz = 20 ns period × 3 = under 60 ns
DCLK = 10 MHz = 100 ns period × 3 = under 300 ns
• ROM map
• Address
A6 to A2
QVGA mode
18 dots
WVGA mode
16 dots
• Data
D15 to D12, D11 to D0
A1 to A0
00
12 dots
01
10
11
[1]
[2]
[3]
[4]
Unused
Used
A17 to A7 (10 bits) = 2048 characters = character codes
• Display appearance
QVGA: 1 character = 12 × 18 dots
Character font: [1]
Graphics: [1] + [2] + [3] + [4]
WVGA: 1 character = 12 × 16 dots
Character font: [1] [2]
[3] [4]
Graphics: ([1] + [2] + [3] + [4]) displayed magnified 2× in both the horizontal and vertical directions.
12
12
12
16
[1]
[2]
16
16
[3]
[4]
16
12
[1]+[2]
+[3]+[4]
×2
No. 7545-51/52
LC74735YW
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PS No.A2330-52/52
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