ENN6123 D

Ordering number : EN6123B
LC72722PM
CMOS IC
Single-Chip RDS
Signal-Processing System IC
http://onsemi.com
Overview
The LC72722PM is a single-chip system IC that implement the signal processing required by the European
Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee)
RBDS (Radio Broadcast Data System) standard. This IC include band-pass filter, demodulator, synchronization, and
error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision
error correction technique.
Functions
• Band-pass filter : switched capacitor filter (SCF)
• Demodulator : RDS data clock regeneration and demodulated data reliability information
• Synchronization : Block synchronization detection
(with variable backward and forward protection conditions)
• Error correction : Soft-decision/hard-decision error correction
• Buffer RAM : Adequate for 24 blocks of data (about 500ms) and flag memory
• Data I/O : CCB interface (power on reset)
Features
• Error correction capability improved by soft-decision error correction
• The load on the control microprocessor can be reduced by storing decoded data in the on-chip data buffer RAM.
• Two synchronization detection circuits provide continuous and stable detection of the synchronization.
• Data can be read out starting with the backward-protection block data after a synchronization reset.
• Fully adjustment free
Specifications
• Operating power-supply voltage :
• Operating temperature :
• Package :
4.5 to 5.5V
-40 to +85°C
MFP24(375mil)
•
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
•
CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
June, 2013
60612HK B8-9103,8341/51202AS(OT)/83199TH(OT) No. 6123-1/18
LC72722PM
Specifications
Absolute Maximum Ratings at Ta = 25°C, Vssd = Vssa = 0V
Parameter
Symbol
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Maximum output current
Allowable power dissipation
Pin Name
Ratings
Unit
Vddmax
Vddd, Vdda
-0.3 to +7.0
V
Vin1max
CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC
-0.3 to +7.0
V
Vin2max
XIN
-0.3 to Vddd+0.3
V
Vin3max
MPXIN, CIN
-0.3 to Vdda+0.3
V
Vo1max
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7
-0.3 to +7.0
V
Vo2max
XOUT
-0.3 to Vddd+0.3
V
Vo3max
FLOUT
-0.3 to Vdda+0.3
V
Io1max
DO, T3, T4, T5, T6, T7
+6.0
mA
Io2max
XOUT, FLOUT
+3.0
mA
Io3max
SYNC, RDS-ID
+20.0
mA
Pdmax
(Ta≤85°C)
175
mW
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-55 to +125
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to 85°C, Vssd = Vssa = 0V
Parameter
Pin Name
Symbol
Vdd1
Vddd, Vdda
Vdd2
Vddd
Conditions
Ratings
min
typ
max
4.5
5.0
5.5
Unit
V
Supply voltage
Input high-level
voltage
Input low-level voltage
Output voltage
VIH
VIL
VO
VIN1
Input amplitude
Guaranteed crystal
CL, DI, CE, SYR, T1, T2
CL, DI, CE, SYR, T1, T2
V
0.7Vddd
6.5
V
0
0.3Vddd
V
6.5
V
50
mVrms
T4, T5, T6, T7
MPXIN
f=57±2kHz
100% modulation composite
VIN2
VXIN
XIN
XTAL
XIN, XOUT
TXtal
2.0
DO, SYNC, RDS-ID, T3,
Oscillator frequencies
Crystal oscillator
frequency
deviation
Serial data hold voltage
XIN, XOUT
100
mVrms
400
1500
mVrms
CI≤120Ω (XS=0)
4.332
MHz
CI≤70Ω (XS=1)
8.664
MHz
±100
fo=4.332MHz, 8.664MHz
ppm
Data setup time
tSU
DI, CL
0.75
μs
Data hold time
tHD
DI, CL
0.75
μs
Clock low level time
tCL
CL
0.75
μs
Clock high level time
tCH
CL
0.75
μs
CE wait time
tEL
CE, CL
0.75
μs
CE setup time
tES
CE, CL
0.75
μs
0.75
CE hold time
tEH
CE, CL
CE high-level time
tCE
CE
Data latch change
tLC
μs
20
ms
1.15
μs
0.46
μs
0.46
μs
time
tDC
DO,CL
tDH
DO,CE
Data output time
Differs depending on the value
of the pull-up resistor used.
No. 6123-2/18
LC72722PM
Electrical Characteristics at Ta = -40 to 85°C, Vssd = Vssa = 0V
Parameter
Pin Name
Symbol
RMPXIN
Conditions
Ratings
min
typ
max
Unit
MPXIN-Vssa
f=57kHz
43.0
kΩ
CIN-Vssa
f=57kHz
100.0
kΩ
1.0
MΩ
Input resistance
Rcin
Internal feedback
Rf
XIN
Center frequency
fc
FLOUT
56.5
57.0
57.5
kHz
-3dB band width
BW-3dB
FLOUT
2.5
3.0
3.5
kHz
31
34
dB
resistance
Gain
Gain
MPXIN-FLOUT
f=57kHz
28
Att1
FLOUT
Δf=±7kHz
30
dB
Att2
FLOUT
f<45kHz, f>70kHz
40
dB
Att3
FLOUT
f<20kHz
50
dB
Vref
Vref
Vdda=5.0V
Hysteresis
VHIS
CL, DI, CE, SYR, T1, T2
Output low-level
VOL1
DO, T3, T4, T5, T6, T7
I=2mA
0.5
voltage
VOL2
Stop band
Attenuation
Reference voltage
2.5
V
0.1Vddd
V
output
V
SYNC, RDS-ID
I=8mA
0.5
V
Input high-level
IIH1
CL, DI, CE, SYR, T1, T2
VI= Vddd
5.0
μA
current
IIH2
XIN
VI=Vddd
11.0
μA
Input low-level
IIL1
CL, DI, CE, SYR, T1, T2
VI=0V
5.0
μA
current
IIL2
XIN
VI=0V
11.0
μA
DO, SYNC, RDS-ID, T3,
VO=6.5V
5.0
μA
Output off leakage
IOFF
current
Current drain
2.0
2.0
T4, T5, T6, T7
Idd
Vddd, Vdda
9
mA
No. 6123-3/18
LC72722PM
Package Dimensions
unit:mm
3045C
15.2
13
0.65
7.9
10.5
24
1
1.27
0.35
12
0.15
0.1
(2.15)
2.35max
(0.62)
SANYO : MFP24(375mil)
Pin Assignment
24 SYR
VREF 1
23 CE
MPXIN 2
Vdda 3
22 DI
Vssa 4
21 CL
FLOUT 5
20 DO
CIN 6
LC72722PM
19 RDS-ID
T1 7
18 SYNC
T2 8
17 T7 (CORREC/ARI-ID/TA/BEO)
T3 (RDCL) 9
16 T6 (ERROR/57K/TP/BE1)
T4 (RDDA) 10
15 Vssd
T5 (RSFT) 11
14 Vddd
13 XIN
XOUT 12
Top view
No. 6123-4/18
LC72722PM
Block Diagram
+5.0V
VREF
FLOUT
Vdda
Vssa
MPXIN
DO
CL
DI
CE
+
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
CCB
+5.0V
CIN
PLL
(57kHz)
VREF
57kHz
BPF
(SCF)
SMOOTHING
FILTER
RAM
(24 BLOCK DATA)
CLOCK
RECOVERY
(1187.5Hz)
DATA
DECODER
ERROR
CORRECTION
(SOFT DECISION)
SYNC/EC
CONTROLLER
Vddd
Vssd
RDS-ID
SYNC
SYR
CLK (4.332MHz)
T1
T2
T3 to T7
TEST
MEMORY
CONTROL
OSC/DIVIDER
XIN
SYNC
DETECT-1
SYNC
DETECT-2
XOUT
No. 6123-5/18
LC72722PM
Pin Functions
Pin No.
Pin name
Function
I/O
Pin circuit
Vdda
1
VREF
Reference voltage output (Vdda/2)
Output
Vssa
Vdda
2
MPXIN
Baseband (multiplexed) signal input
Input
Vssa
5
FLOUT
Subcarrier output (filter output)
Output
Vdda
7
CIN
Subcarrier input (comparator input)
Input
Vssa
VREF
3
Vdda
Analog system power supply (+5V)
−
−
4
Vssa
Analog system ground
−
−
12
XOUT
Crystal oscillator output (4.332/8.664MHz)
Vddd
Output
XIN
13
XIN
Crystal oscillator input (external reference signal input)
7
T1
Test input (This pin must always be connected to ground.)
XOUT
Input
S
Test input (standby control)
8
T2
Vssd
Vssd
0:Normal operation, 1:Standby state
(crystal oscillator stopped)
9
T3(RDCL)
Test I/O (RDS clock output)
10
T4(RDDA)
Test I/O (RDS data output)
11
T5(RSFT)
Test I/O (soft-decision control data output)
T6
16
(ERROR/57K/BE1)
Test I/O (error status, regenerated carrier, error block count)
T7
Test I/O
(CORREC/ARI-ID/BE0)
(error correction status, SK detection, error block count)
18
SYNC
Block synchronization detection output
19
RDS-ID
RDS detection output
20
DO
Data output
21
CL
Clock input
22
DI
Data input
17
I/O*
Output
Vssd
Vssd
Serial data interface (CCB)
S
Input
23
CE
Chip enable
24
SYR
Synchronization and RAM address reset (active high)
14
Vddd
Digital system power supply (+5V)
−
−
15
Vssd
Digital system ground
−
−
Vssd
Note : * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user
applications.
No. 6123-6/18
LC72722PM
CCB output data format
1. Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.
2. Any number of 32-bits output data blocks can be output consecutively.
3. When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data
consecutively.
4. If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted.
However, if only the last bit is remaining to be read, it will not be possible to re-read that whole block.
5. The check bits (10 bits) are not output.
6. The data valid (OWD) must not be referred to.
7. When the first leading bits are not “1010”, the read in data is in invalid, and read operation is cancelled.
CCB address 6C
B B B B A A A A
0 1 2 3 0 1 2 3
DI
0
0
1
1
0
1
1
0
Last bit
Output data / first bit
1
DO
0 1
O
R A S
D D D D D
B B R R
E E D
D D D D D D D D D
0 W B
F F R Y E
1 1 1 1 1 1 D
2
1
0
E
2
1
0
D
1 0 I C
5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
(8) RDS data
(7) Error information flags
(6) Synchronization established flag
(5) ARI(SK) detection flag
(4) RAM data remaining flags
(3) Consecutive RAM read out possible flag
(2) Offset word information flags
(1) Offset word detection flag
Fixed pattern (1010)
(1) Offset word detection flag (1bit) : OWD
OWD
Offset word detection
1
Detected
0
Not detected (protection function operating)
(2) Offset word information flag (3bit) : B0 to B2
B
2
B
1
B
0
Offset word
0
0
0
A
0
0
1
B
0
1
0
C
0
1
1
C’
1
0
0
D
1
0
1
E
1
1
0
Unused
1
1
1
Unused
No. 6123-7/18
LC72722PM
(3) Consecutive RAM read out possible flag (1bit) : RE
RE
RAM data information
1
The next data to be read out is in RAM
0
This data item is the last item in RAM, ant the next data is not present.
(4) RAM data remaining flag (2bits) : RF0,RF1
RF1
RF0
Remaining data in RAM (number of blocks)
0
0
1 to 7
0
1
8 to 15
1
0
16 to 23
1
1
24
Caution : This value is only meaningful when RE is 1. When RE is 0, there is no data in RAM, even if RF is 00.
If a synchronization reset was applied using SYR, then the backward protection block data that was written to memory
is also counted in this value.
(5) ARI(SK) detection flag (1bit) : ARI
ARI
SK signal
1
Detected
0
Not detected
(6) Synchronization established flag (1bit) : SYC
SYC
Synchronization detection
1
Synchronized
0
Not synchronized
Caution : This flag indicates the synchronization state of the circuit at the point when the data block being output was received.
On the other hand, the SYNC pin (pin18) output indicates the current synchronization state of the circuit.
(7) Error information flags (3bits) : E0 to E2
E
2
E
1
E
0
Number of bits corrected
0
0
0
0 (no errors)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
Correction not possible
1
1
1
Unused
Caution : If the number of errors exceeds the value of the EC0 to EC2 setting (see the section on the CCB input format),
the error information flags will be set to the “Correction not possible” value.
(8) RDS data (16bits) : D0 to D15
This data is output with the MSB first ant the LSB last.
Caution : When error correction was not possible, the input data is output without change.
No. 6123-8/18
LC72722PM
CCB Input data format
IN1 data, first bit
[1] CCB address 6A
DI
B B B B A A A A
0 1 2 3 0 1 2 3
F F F F
S
B
S S S S
Y
S
0 1 2 3
R
O E E E
W C C C
E 0 1 2
E E C
C C T
3 4 0
0 1 0 1 0 1 1 0
(12) Circuit control
(5) Error correction method setting
(4) RAM write control
(3) Synchronization and RAM address reset
(2) Synchronization detection method setting
(1) Synchronization protection method setting
IN2 data, first bit
[2] CCB address 6B
DI
B B B B A A A A
0 1 2 3 0 1 2 3
C
T
1
S S
P P P
P P
X
R
P P
T T T
L L
S
M
0 1
0 1 2
0 1
T T T T
S S S S
0 1 2 3
1 1 0 1 0 1 1 0
(11) Test mode settings
(10) Output pin settings
(9) RDS/RBDS selection
(8) Demodulation circuit phase control
(7) Crystal oscillator frequency selection
(6) Intermittent DO output setting
(12) Circuit control
Caution : The bits labeled with an asterisk must be set to 0.
(1) Synchronization protection (forward protection) method setting (4bits) : FS0 to FS3
FS3 = 0 : If offset words in the correct order could not be detected continuously during the number of blocks
specified by FS0 to FS2, take that to be a lost synchronization sate.
FS3 = 1 : If blocks with uncorrectable errors were received consecutively during the number of blocks specified by
FS0 to FS2, take that to be a lost synchronization state.
F
S
0
F
S
1
F
S
2
Condition for detecting lost synchronization
0
0
0
If 3 consecutive blocks matching the FS3 condition are received.
1
0
0
If 4 consecutive blocks matching the FS3 condition are received.
0
1
0
If 5 consecutive blocks matching the FS3 condition are received.
1
1
0
If 6 consecutive blocks matching the FS3 condition are received.
0
0
1
If 8 consecutive blocks matching the FS3 condition are received.
1
0
1
If 10 consecutive blocks matching the FS3 condition are received.
0
1
1
If 12 consecutive blocks matching the FS3 condition are received.
1
1
1
If 16 consecutive blocks matching the FS3 condition are received.
Initial value : FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0
(2) Synchronization detection method setting (1bit) : BS
BS
Synchronization detection conditions
0
If during 3 blocks, 2 blocks of offset words were detected in the correct order.
1
If the offset words were detected in the correct order in 2 consecutive blocks.
Initial value : BS = 0
No. 6123-9/18
LC72722PM
(3) Synchronization and RAM address reset (1bit) : SYR
SYR
0
Synchronization detection circuit
Normal operation (reset cleared)
1
Forced to the unsynchronized state
(synchronization reset)
RAM
Normal write (See the description of the OWE bit)
After the reset is cleared, start writing from the data prior
to the establishment of synchronization, i.e. the data in
backward protection.
Initial value : SYR = 0
Caution :
1. To apply a synchronization reset, set SYR to 1 temporarily using CCB, and then set it back to 0 again using CCB.
The circuit will start synchronization capture operation at the point SYR is set to 0.
2. The SYR pin (pin24) also provides an identical reset control operation. Applications can use either method.
However, the control method that is not used must be set to 0 at all times.
Any pulse with a width of over 250 ns will suffice.
3. A reset must be applied immediately after the reception channel is changed.
If a reset is not applied, reception data from the previous channel may remain in on-chip memory.
4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding
the establishment of synchronization.
(4) RAM write control (1bit) : OWE
OWE
RAM write conditions
0
Only data for which synchronization had been established is written.
Data for which synchronization not has been established (unsynchronized data) is also
written. (However, this applies when SYR = 0.)
1
Initial value : OWE = 0
(5) Error correction method setting (5bits) : EC0 to EC4
E
C
0
0
E
C
1
0
E
C
2
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
1
1
1
1
Number of bits corrected
0 (error detection only)
1 or fewer bits
2 or fewer bits
3 or fewer bits
4 or fewer bits
5 or fewer bits
Illegal value
Illegal value
E
C
3
0
E
C
4
0
MODE0 Hard decision
1
0
MODE1 Soft decision A
0
1
1
1
MODE2 Soft decision B
Illegal value
Soft-decision setting
Initial values : EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1
Caution : 1. If soft-decision A or soft-decision B is specified, soft-decision control will be performed even if the number
of bits corrected is set to 0 (error detection only). With these settings, data will be output for blocks with no errors.
2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction.
(6) Intermittent DO output setting
SP0
SP1
DO output state
0
0
DO goes low when one or more blocks of data are written to memory.
1
0
DO goes low when 4 or more blocks of data are written to memory.
0
1
DO goes low when 8 or more blocks of data are written to memory.
1
1
DO goes low when 12 or more blocks of data are written to memory.
Initial values : SP0 = 0, SP1 = 0
No. 6123-10/18
LC72722PM
(7) Crystal oscillator frequency selection (1bit) : XS
XS = 0 : 4.332MHz (Initial value : XS = 0)
XS = 1 : 8.664MHz
(8) Demodulation circuit phase control (2bits) : PL0, PL1
PL0
PL1
Demodulation circuit phase control
0
0/1
< Normal operation > when ARI presence or absence is unclear.
1
0
1
If the circuit determines that the ARI signal is absent : 90° phase
If the circuit determines that the ARI signal is present : 0° phase
Initial values : PL0 = 0, PL1 = 1
Caution : 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces
the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier.
However, the initial phase following a synchronization reset is set by PL1.
2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90° (PL1 = 0) or
0° (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the
RDS data is reproduced by detecting at a phase of 90° with respect to the reproduced carrier. When ARI is present,
PL1 should be set to 1, since detection is at 0°. In cases where the ARI presence is known in advance, more stable
reproduction can be achieved by fixing the demodulation phase in this manner.
(9) RDS/RBDS(MMBS) selection (1bit) : RM
RM
RBDS
0
None
1
Provided
Decoding method
Only RDS data is decoded correctly (Offset word E is not detected.)
RDS and MMBS data is decoded correctly (Offset word E is also detected.)
Initial value : RM=0
(10) Output pin settings (3bits) : PT0 to PT2
These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins
MODE
P
T
0
P
T
1
P
T
2
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
T3
T4
T5
T6
RDCL
RDDA
RSFT
ERROR
57K
−
−


−
−


−
−


−
−
−

−
−

−
−


−



−



−
−
−

−
−
−

−
T7
TP


BE1
CORREC
ARI-ID
TA
BE0
−
−
−
−

−
−
−

−
−

−

−
−
−
−

−
−
−
−
−
−

−
−
−

−
−
−
−

−
−
−
−
−
− : open, ,  : Output enabled ( = reverse polarity)
Initial value : PT0 = 1, PT1 = 1, PT2 = 0 (Mode 3)
Caution : 1. When PT2 is set to 1, the polarity of the T6(ERROR/57K/TP), T7(CORREC/ARI-ID/TA), SYNC,
and RDS-ID pins changes to active high.
2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors
to output data.
Mode1 (PT2 = 0)
TP = 0 detected
TP = 1 detected
TP = Traffic program code
Pin T6 (TP)
High (1)
Low (0)
No. 6123-11/18
LC72722PM
Mode1 (PT2 = 0)
Pin T7 (TA)
TA = 0 detected
High (1)
TA = 1 detected
TA = Traffic announcement code
Low (0)
Mode2 (PT2 = 0)
No SK
SK present
Pin T7 (ARI-ID)
High (1)
Low (0)
Mode3 (PT2 = 0)
Correction not possible
Errors corrected
No errors
Pin T6 (ERROR)
Low (0)
High (1)
High (1)
Pin T7 (CORREC)
Low (0)
Low (0)
High (1)
Pin T6 (BE1)
Pin T7 (BE0)
B=0
Low (0)
Low (0)
1 ≤ B ≤ 20
Low (0)
High (1)
20 < B ≤ 40
High (1)
Low (0)
Mode = 4
Number of error blocks (B)
40 < B ≤ 48
High (1)
High (1)
These pins indicate the number of blocks in a set of 48 blocks that had errors before correction.
The output polarity of these pins is fixed at the values listed in the table.
Mode (PT2 = 0)
The SYNC pin
When synchronized : Low (0), When unsynchronized: High (1)
When synchronized : Goes high for a fixed period (421 μs) at the
start of a block and then goes low.
When unsynchronized : High (1)
0 to 2
3
Caution : The output indicates the synchronization state for the previous block.
When PT2 = 0
The RDS-ID pin
No RDS
High (1)
RDS present
Low (0)
(11) Test mode settings (4bits) : TS0 to TS3
Initial values : TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0
(Applications must set these bits to the above values.)
Notes : The T1 and T2 pins (pins 7 and 8) are related to test mode as follows.
Pin T1
Pin T2
IC operation
0
0
Normal operating mode
0
1
Standby mode (crystal oscillator stopped)
1
0/1
The T1 pin must be tied to VSS (0V).
IC test mode
Notes
These states are user settable
Users cannot use this state
(12) Circuit control (2 bits) : CT0 and CT1
Item
CT0
RSFT control
CT1
RDS-ID detection condition
Control
When set to 1, soft-decision control data (RSFT) is
easier to generate.
When set to 1, the RDS-ID detection conditions are
made more restrictive.
Initial value : CT0 = 0, CT1 = 0
No. 6123-12/18
LC72722PM
RDCL / RDDA / RSFT and ERROR / CORREC / SYNC output timing
(1) Timing 1
421 μs 421 μs
Tp1
RDCL output
RDDA output
RSFT output
17 μs Tp2
17 μs
Note : When PT2 = 0, RDDA and RSFT must be acquired on the falling edge of RDCL.
Error crrection
Sync NG
Sync OK
Sync OK
Sync OK
Sync OK
Sync OK
Sync NG
Data
corrected
No
errors
No
errors
Data
corrected
Uncorrectable
Input data
Uncorrectable
(2) Timing 2 (mode 3, PT2 = 0)
Tp1
Tp1
Sync NG
SYNC output
ERROR output
CORREC output
No. 6123-13/18
LC72722PM
Serial Data Input and Output Methods
Data is input and output using the CCB (Computer Control Bus), which is Our audio IC serial bus format.
This IC adopts an 8-bit address CCB format.
I/O mode
(LSB)
B0
B1
Address
B2 B3
(MSB)
A0
A1
A2
A3
[1]
IN1 (6A)
0
1
0
1
0
1
1
0
[2]
IN2 (6B)
1
1
0
1
0
1
1
0
[3]
OUT (6C)
0
0
1
1
0
1
1
0
Comment
 Control data input mode, also referred to as
“ serial data input ” mode.
 16bit data input mode
 Data output mode
 The data for multiple blocks can be
output sequentially in this mode.
I/O mode determined
CE
1
CL
2
B0
DI
B1
B2
B3
A0
A1
A2
A3
First Data IN1/2
1
First Data OUT
DO
2
First Data OUT
1 For the CL normal high state
2 For the CL normal low state
No. 6123-14/18
LC72722PM
(1) Serial data input (IN1 / IN2)
tSU, tHD, tEL, tES, tEH ≥ 0.75μs tLC < 1.15μs tCE < 20 ms
 CL : Normal high
tEL
tCE
tES
tEH
CE
CL
tSU
tHD
B0
DI
B1
B2
B3
A0
A1
A2
FS0
CT1
A3
FS1
0
FS2
SP0
FS3
SP1
EC3
TS0
EC4
TS1
CT0
TS2
0
TS3
tLC
Internal data
 CL : Normal low
tEL
tCE
tES
tEH
CE
CL
tSU
tHD
B0
DI
B1
B2
B3
A0
A1
FS0
CT1
A3
A2
FS1
0
FS2
SP0
FS3
SP1
EC3
TS0
EC4
TS1
CT0
TS2
0
TS3
tLC
Internal data
(2) Serial data output (OUT)
tSU, tHD, tEL, tES, tEH ≥ 0.75μs tDC, tDH < 0.46μs tCE < 20 ms
 CL : Normal high
tEL
tCE
tES
tEH
CE
CL
tSU
tHD
B0
DI
B1
B2
B3
A0
A1
A2
A3
tDC
tDC
1
DO
 CL : Normal low
tEL
0
tDH
1
0
D3
D2
D1
tCE
tES
D0
tEH
CE
CL
tSU
DI
B0
tHD
B1 B2
B3
A0
A1
A2
A3
tDC
1
DO
tDH
tDC
0
1
0
D3
D2
D1
D0
Cautions : 1. Since the DO pin is an n-channel open-drain output, the transition times (tDC, tDH) will differ with the value of
the pull-up resistor used.
2. The CE, CL, DI, and DO pins can be connected to the corresponding pins on other ICs that use the CCB interface.
(However, we recommend connecting the DO and CE pins separately if the number of available microcontroller
ports allows it.)
3. Serial data I/O becomes possible after the crystal oscillator starts oscillation.
No. 6123-15/18
LC72722PM
(3) Serial data timing
 CL : Normal high
tCE
VIH
CE
tCL
tCH
VIH
VIL
CL
VIL
tES
tEL
VIH
VIL
DI
VIH
VIL
VIH
tEH
VIH
VIL
tSU
tHD
tDC
tDH
DO
tLC
Internal data latch
New
Old
 CL : Normal low
tCE
VIH
CE
tCH
tCL
VIH
VIL
CL
VIH
VIL
tEL
VIH
VIL
DI
tSU
VIL
VIL
VIL
tEH
tES
VIH
VIL
tHD
tDC
tDH
tDC
DO
tLC
Old
Internal data latch
Parameter
Symbol
Conditions
min
typ
max
New
Unit
Data setup time
tSU
DI, CL
0.75
μs
Data hold time
tHD
DI, CL
0.75
μs
Clock low level time
tCL
CL
0.75
μs
Clock high level time
tCH
CL
0.75
μs
CE wait time
tEL
CE, CL
0.75
μs
CE setup time
tES
CE, CL
0.75
μs
CE hold time
tEH
CE, CL
0.75
μs
CE high level time
tCE
CE
Data latch transition time
tLC
Data output time
tDC
DO, CL
tDH
DO, CE
Differs with the value of the pull-up
resistor used.
20
ms
1.15
μs
0.46
μs
0.46
μs
No. 6123-16/18
LC72722PM
DO pin operation
This IC incorporates a RAM data buffer that can hold up to 24 blocks of data. At the point when one block of data is
written to this RAM, the IC issues a read request by switching the DO pin from high to low.
The DO pin always goes high for a fixed period (Tdo = 265 μs) after a readout and CE goes low. When all the data in
the data buffer has been read out, the DO pin is held in the high state until a new block of data has been written to the
RAM. If there is data that has not yet been read remaining in the data buffer, the DO pin goes low after the Tdo time has
elapsed.
After a synchronization reset, the DO pin is held high until synchronization is established. It goes low at the point the IC
synchronizes.
 When the DO pin is high following the 265 μs period (Tdo) after data is read out.
Here, the buffer is in the empty state, i.e. the state where new data has not been written. After this, when the DO pin
goes low, applications are guaranteed to be able to read out that data without it being overwritten by new data if they
start a readout operation within 480 ms of DO going low.
Tdo
CE pin
T
DO pin
(Last data)-1
New data
Last data
DO check (Tdo < T)
 When DO goes low 265 μs after data is read out
Here, there is data that has not been read out remaining in the data buffer. In this case, applications are guaranteed to
be able to read out that data without it being overwritten by new data if they start a readout operation within 20 ms
of DO going low. (Note that this is the worst case condition.)
Tdo
CE pin
T
DO pin
(Last data)-2
Last data
(Last data)-1
DO check (Tdo < T)
Notes : 1. Although an application can determine whether or not there is data remaining in the buffer by checking the DO level
with the above timing, checking the RE and RF flags in the serial data is a preferable method.
2. Applications are not limited to reading out one block of data at a time, but rather can read out multiple blocks of data
continuously as described above. When using this method, if an application references the RE and RF flags in the data
while reading out data, it can determine the amount of data remaining. However, the length of the period for data readout
(the period the CE pin remains high) must be kept under 20 ms.
3. If the DO pin is shared with other ICs that use the CCB interface, the application must identify which IC issued the
readout request. One method is to read out data from the LC72722PM and either check whether meaningful data has
been read (if the LC72722PM is not requesting a read, data consisting of all zeros will be read out) or check whether the
DO level goes low within the 256 μs following the completion of the read (if the DO pin goes low, then the request was
from another IC).
No. 6123-17/18
LC72722PM
Sample Application circuit
10 μF
Vssa
+
MPXIN
330 pF
Vdda
0.1 μF
1
2
3
4
Vssa
5
560 pF
6
7
8
Vssd
NC
NC
NC
9
10
11
12
22 pF
VREF
SYR
MPXIN
CE
Vdda
DI
Vssa
CL
FLOUT
DO
CIN
RDS-ID
T1
SYNC
T2
T7
T3
T6
T4
Vssd
T5
Vddd
XOUT
XIN
4.332 MHz
Vssd
24 SYR
23
Vssd
CE
22
DI
21
20
19
18
17
16
Vddd
10 kΩ
Vddd
10 kΩ
Vddd
10 kΩ
DO
RDS-ID
SYNC
NC
NC
15
14
CL
Vssd
0.1 μF
Vddd
13
22 pF
Vssd
Caution : 1. Determine the value of the DO pin pull-up resistor based on the required serial data transfer speed.
2. If the SYR pin is unused, it must be connected to ground.
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PS
No. 6123-18/18
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