KAF 16200 D

KAF-16200
4500 (H) x 3600 (V) Full
Frame CCD Image Sensor
Description
The KAF−16200 is a single output, high performance CCD (charge
coupled device) image sensor with 4500 (H) x 3600 (V) photoactive
pixels designed for a wide range of color or monochrome image
sensing applications. Each pixel contains anti−blooming protection by
means of a lateral overflow drain thereby preventing image corruption
during high light level conditions. Each of the 6.0 mm square pixels of
the color version are selectively covered with red, green or blue
pigmented filters for color separation. Microlenses are added for
improved sensitivity on both color and monochrome sensors.
The sensor utilizes a transparent gate electrode to improve
sensitivity compared to the use of a standard front side illuminated
polysilicon electrode.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Figure 1. KAF−16200 CCD Image Sensor
Architecture
Full Frame CCD with Square Pixels
Total Number of Pixels
4641 (H) x 3695 (V) = 17.0 M
Number of Effective Pixels
4540 (H) x 3640 (V) = 16.5 M
Number of Active Pixels
4500 (H) x 3600 (V) = 16.2 M
Pixel Size
6.0 mm (H) x 6.0 mm (V)
Active Image Size
27.0 mm (H) x 21.6 mm (V)
34.6 mm Diag., APS−H Optical Format
Aspect Ratio
5:4
Output Sensitivity (Q/V)
31 mV/e−
Charge Capacity (24 MHz)
41 ke−
Read Noise (f = 24 MHz)
14 e− rms
Dark Current (60°C)
112 e−/s
Dynamic Range
69 dB linear
Quantum Efficiency (Peak)
Color (600, 549, 480 nm)
Monochrome (540 nm)
33%, 40%, 33%
56%
Maximum Frame Rate
1.23 fps
Maximum Data Rate
24 MHz
Blooming Protection
2000 X Saturation Exposure
Features
• Transparent Gate Electrode for High
•
•
•
•
Sensitivity
High Resolution, 35 mm Diagonal Format
Broad Dynamic Range
Low Noise
Large Image Area
Applications
• Astrophotography
• Scientific Imaging
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: Unless noted, all parameters are specified at 25°C.
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 1
1
Publication Order Number:
KAF−16200/D
KAF−16200
ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number
Description
KAF−16200−ABA−CD−B1
Monochrome, Microlens, CERDIP Package, Sealed Clear Cover
Glass with AR Coating (both sides), Grade 1
KAF−16200−ABA−CD−B2
Monochrome, Microlens, CERDIP Package, Sealed Clear Cover
Glass with AR Coating (both sides), Grade 2
KAF−16200−ABA−CD−AE
Monochrome, Microlens, CERDIP Package, Sealed Clear Cover
Glass with AR Coating (both sides), Engineering Grade
KAF−16200−FXA−CD−B1
Gen2 Color (Bayer RGB), Special Microlens, CERDIP Package,
Sealed Clear Cover Glass with AR Coating (both sides), Grade 1
KAF−16200−FXA−CD−B2
Gen2 Color (Bayer RGB), Special Microlens, CERDIP Package,
Sealed Clear Cover Glass with AR Coating (both sides), Grade 2
KAF−16200−FXA−CD−AE
Gen2 Color (Bayer RGB), Special Microlens, CERDIP Package,
Sealed Clear Cover Glass with AR Coating (both sides), Engineering
Grade
Marking Code
KAF−16200−ABA
Serial Number
KAF−16200−FXA
Serial Number
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−16200
DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram
Image Acquisition
Dark Reference Pixels
Surrounding the periphery of the device is a border of light
shielded pixels creating a dark region. Within this dark
region are light shielded pixels that include 36 leading dark
pixels on every line. There are also 30 full dark lines at the
start and 23 full dark lines at the end of every frame. Under
normal circumstances, these pixels do not respond to light
and may be used as a dark reference.
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the device. These
photon−induced electrons are collected locally by the
formation of potential wells at each photogate or pixel site.
The number of electrons collected is linearly dependent on
light level and exposure time and non−linearly dependent on
wavelength. When the pixel’s capacity is reached, excess
electrons are discharged into the lateral overflow drain to
prevent crosstalk or ‘blooming’. During the integration
period, the V1 and V2 register clocks are held at a constant
(low) level.
Dummy Pixels
Within each horizontal shift register there are 20 leading
additional shift phases 1 + 10 + 4 + 1 + 4 (See Figure 2).
These pixels are designated as dummy pixels and should not
be used to determine a dark reference level.
Charge Transport
Active Buffer Pixels
The integrated charge from each photogate (pixel) is
transported to the output using a two−step process. Each line
(row) of charge is first transported from the vertical CCDs
to a horizontal CCD register using the V1 and V2 register
clocks. The horizontal CCD is presented with a new line on
the falling edge of V2 while H1 is held high. The horizontal
CCDs then transport each line, pixel by pixel, to the output
structure by alternately clocking the H1 and H2 pins in a
complementary fashion. A separate connection to the last
H1 phase (H1L) is provided to improve the transfer speed of
charge to the floating diffusion output amplifier. On each
falling edge of H1L a new charge packet is dumped onto a
floating diffusion and sensed by the output amplifier.
Forming the outer boundary of the effective active pixel
region, there are 20 unshielded active buffer pixels between
the photoactive area and the dark reference. These pixels are
light sensitive but they are not tested for defects and
non−uniformities. For the leading 20 active column pixels,
the first 4 pixels are covered with blue pigment while the
remaining are arranged in a Bayer pattern (R, GR, GB, B).
CTE Monitor Pixels
Two CTE test columns, one on each of the leading and
trailing ends and one CTE test row are included for
manufacturing test purposes.
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3
KAF−16200
HORIZONTAL REGISTER
Output Structure
H2
H1
HCCD
Charge
Transfer
VDD
H1L
OG
RG
RD
Floating
Diffusion
VOUTX
X= L or R
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Note: Represents either the left or the right output. The designation is omitted in the figure.
Figure 3. Output Architecture (Left or Right)
the reset gate (RG) is clocked to remove the signal and FD
is reset to the potential applied by reset drain (RD).
Increased signal at the floating diffusion reduces the voltage
seen at the output pin. To activate the output structures, an
off−chip current source must be added to the VOUT pins of
the device. See Figure 4.
The output consists of a floating diffusion capacitance
connected to a three−stage source follower. Charge
presented to the floating diffusion (FD) is converted into a
voltage and is current amplified in order to drive off−chip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the FD.
Once the signal has been sampled by the system electronics,
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4
KAF−16200
Output Load
VDD = +15 V
Iout = 5 mA
0.1 μF
VOUT
2N3904
or Equiv.
140 W
1 kW
Buffered
Video
Output
Note: Component values may be revised based on operating conditions and other design considerations.
Figure 4. Recommended Output Structure Load Diagram
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KAF−16200
PHYSICAL DESCRIPTION
Pin Description and Device Orientation
Note: As viewed from the bottom.
Figure 5. Pinout Diagram
Table 3. PINOUT
Pin
Name
1
VSUB
Pin
Name
Substrate
17
VSUB
Substrate
Last Horizontal Phase
18
LODB
Lateral Overflow Drain, Bottom of Die
Description
Description
2
H1LAST
3
OG
Output Gate
19
V1
Vertical Phase 1
4
RG
Reset Gate
20
V1
Vertical Phase 1
V2
Vertical Phase 2
Vertical Phase 2
5
RD
Reset Drain
21
6
VSS
Amplifier Return
22
V2
Video Output
23
LODT
Lateral Overflow Drain, Top of Die
Amplifier Supply
24
VSUB
Substrate
Horizontal Phase 2
25
VSUB
Substrate
Horizontal Phase 1
26
LODT
Lateral Overflow Drain, Top of Die
7
VOUT
8
VDD
9
H2
10
H1
11
VSUB
Substrate
27
V2
Vertical Phase 2
12
VSUB
Substrate
28
V2
Vertical Phase 2
Substrate
29
V1
Vertical Phase 1
Vertical Phase 1
13
VSUB
14
H1
Horizontal Phase 1
30
V1
15
H2
Horizontal Phase 2
31
LODB
Lateral Overflow Drain, Bottom of Die
Substrate
32
VSUB
Substrate
16
VSUB
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KAF−16200
IMAGING PERFORMANCE
Table 4. TYPICAL OPERATIONAL CONDITIONS
Description
Condition
Readout Time (tREADOUT)
652 ms
Integration Time (tINT)
Varies per Test:
Horizontal Clock Frequency
24 MHz
Temperature
25°C
Mode
Integrate – Readout Cycle
Operation
Typical Operating Conditions
Notes
Includes Overclock Pixels
Bright Field 250 ms,
Dark Field 1 sec,
Saturation 250 ms,
Low Light 33 ms
Room Temperature
Table 5. SPECIFICATIONS
Description
Saturation Signal
Charge to Voltage Conversion
Symbol
Ne−SAT
Min
Nom.
35
Q/V
Max
41
ke−
31
mV/e−
Quantum Efficiency at Peak
Red
Green
Blue
QEMAX
Quantum Efficiency at Peak − Mono
QEMAX
56
Photo Response Non-Linearity
(10−90% Nsat)
PRNL
4
33
40
33
Green difference (Gr/Gb)
Units
10
2
Notes
Verification Plan
Design10
1
Design10
%
Design10
%
Design10
%
Die9
%
Design10
%p−p
2
Die9
50
pA/cm2
3
Die9
DSNU
4
mV p−p
5
Die9
Dark Signal Doubling Temperature
DT
4.7
°C
11
Design10
Read Noise
NR
14
e− rms
Dynamic Range
DR
69.3
dB
Photo Response Non-Uniformity
PRNU
10
Dark Current
Dark Signal Non-Uniformity
Horizontal Charge Transfer Efficiency
HCTE
0.999995
Vertical Charge Transfer Efficiency
VCTE
0.999999
25
Design10
4
Design10
5
Die9
Die9
0.999999
XAB
2000
x VSAT
6
Design10
DC Offset, Output Amplifier
VODC
7.7
V
7
Die9
Output Amplifier Bandwidth
f−3dB
220
MHz
Design10
Output Impedance, Amplifier
ROUT
132
W
Die9
Reset Feedthru
VRFT
0.5
V
Design10
Blooming Protection
1. Increasing output load currents to improve bandwidth will decrease the conversion factor (Q/V).
2. Difference between the maximum and minimum average signal levels of 168 × 168 blocks within the sensor on a per color basis as a % of
average signal level.
3. T = 60°C and tINT = 0, average non-illuminated signal with respect to over-clocked horizontal register signal.
4. 20log (Ne−SAT / NR). Specified at T = 60°C.
5. Measured per transfer above and below (∼70% VSAT min) saturation exposure levels. Typically, no degradation in HCCD CTE is observed
up to 24 MHz.
6. XAB is the number of times above the VSAT illumination level that the sensor will bloom by spot size doubling. The spot size is 10% of the
imager height. XAB is measured at 4 ms.
7. Video level offset with respect to ground.
8. Total dark signal = (VDARK,INT * tINT) + VDARK,READ * tREADOUT.
9. A parameter that is measured on every sensor during production testing.
10. A parameter that is quantified during the design verification activity.
11. This value is valid only near 25°C.
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KAF−16200
TYPICAL PERFORMANCE CURVES
0.7
Absolute Quantum Efficiency
0.6
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
900
1000
Illumination Wavelength (nm)
Figure 6. Typical Monochrome Quantum Efficiency
0.5
Absolute Quantum Efficiency
0.4
0.3
0.2
0.1
0
400
450
500
550
600
650
700
750
800
850
Illumination Wavelength (nm)
Figure 7. Typical Color Quantum Efficiency
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8
900
950
1000
KAF−16200
0.02
GR-GB
0.01
0.005
0
400
500
600
700
800
1000
900
−0.005
−0.01
Lambda (nm)
Figure 8. Typical Green (Red) − Green (Blue) Quantum Efficiency Difference
1.1
1
0.9
Vertical Angle Response
Absolute QE Difference
0.015
0.8
0.7
0.6
Blue Light
Green Light
0.5
Red Light
0.4
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
Angle
Figure 9. Typical Vertical Angular Dependance of Quantum Efficiency for Monochrome Devices
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9
KAF−16200
1.1
1
Horizontal Angle Response
0.9
0.8
0.7
0.6
Blue Light
Green Light
0.5
Red Light
0.4
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
Angle
Figure 10. Typical Horizontal Angular Dependance of Quantum Efficiency for Monochrome Devices
1.2
1
Vertical Angle Response
0.8
0.6
0.4
0.2
0
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
Angle
Figure 11. Typical Vertical Angular Dependance of Quantum Efficiency for Color Devices
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10
KAF−16200
1.2
Horizontal Angle Response
1
0.8
0.6
0.4
0.2
0
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
Angle
Figure 12. Typical Horizontal Angular Dependance of Quantum Efficiency for Color Devices
4500
4000
3500
3000
XAB
2500
2000
1500
1000
500
0
0
2
4
6
8
Exposure Time (ms)
Figure 13. Typical Anti-Blooming Performance: Signal vs. Exposure
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11
10
KAF−16200
1000
Integration Dark Current
Readout Dark Current
Dark Current (e/sec)
100
10
1
34.5
35
35.5
36
36.5
37
37.5
38
1000 e/kbT
Figure 14. Typical Dark Current Performance vs. Temperature
Integration Dark Current Doubling Temperature (5C)
7.00
6.00
5.00
4.00
3.00
2.00
−30
−20
−10
0
10
20
30
40
50
60
Temperature (5C)
Figure 15. Dark Current Doubling Temperature Dependence
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12
70
80
KAF−16200
50000
45000
40000
35000
Signal (e)
30000
25000
20000
15000
10000
5000
0
0
20
40
60
80
100
120
140
Integration Time (a.u)
Figure 16. Typical Linearity Performance
6
10%
5
90%
4
3
Linearity Error (%)
2
1
0
−1
0
10000
20000
30000
−2
−3
−4
−5
−6
Signal (e)
Figure 17. Typical Non-Linearity Plot
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40000
50000
KAF−16200
DEFECT DEFINITIONS
Operating Conditions
Bright defect tests performed at T = 25°C
Dark defect tests performed at T = 25°C
Table 6. SPECIFICATIONS
Classification
Points
Clusters
Columns
Class 1
≤ 2,000
≤ 40
0
Class 2
≤ 2,000
≤ 40
≤ 15
Column Defect
A grouping of more than 10 point defects along a single
column
−or−
A column that deviates by more than 1.2 mV above or
below neighboring columns under non−illuminated
conditions.
−or−
A column that deviates by more than 1.5% above or below
neighboring columns under illuminated conditions.
Column and cluster defects are separated by at least 4
good columns in the x direction. No multiple column defects
(double or more) will be permitted.
Point Defects
A pixel that deviates by more than 9 mV above
neighboring pixels under non−illuminated conditions.
−or−
A pixel that deviates by more than 7% above or 11%
below neighboring pixels under illuminated conditions.
Cluster Defect
A grouping of not more than 10 adjacent point defects.
Cluster defects are separated by no less than 4 good pixels
in any direction.
Saturated Columns
A column that deviates by more than 100 mV above
neighboring columns under non−illuminated conditions. No
saturated columns are allowed.
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KAF−16200
OPERATION
Table 7. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Diode Pin Voltages
Vdiode
–0.5
+20.0
V
1, 2
Gate Pin Voltages
Vgate1
−14.3
+14.5
V
1, 3
Reset Gate Pin Voltages
VRG
−0.5
+14.5
V
1
Overlapping Gate Voltages
V1−2
−14.3
+14.5
V
4
Non−Overlapping Gate Voltages
Vo−o
−14.3
+14.5
V
5
Output Bias Current
Iout
−30
mA
6
LOD Diode Voltage
VLOD
−0.5
+13.5
V
1
Operating Temperature
TOP
0
60
°C
7
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to pin SUB.
2. Includes pins: RD, VDD, VSS, VOUT.
3. Includes pins: V1, V2, H1, H1L, H2, H2L, OG.
4. Voltage difference between overlapping gates. Includes: V1 to V2, H1/H1L to H2, H1L to OG, V1 to H2.
5. Voltage difference between non−overlapping gates. Includes: V1 to H1/H1L.
6. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher currents and
lower load capacitance at the expense of reduced gain (sensitivity). Operation at these values will reduce MTTF (Mean Time to Failure).
7. Noise performance will degrade at higher temperatures.
Power−Up Sequence
The sequence chosen to perform an initial power−up is not
critical for device reliability. A coordinated sequence may
minimize noise and the following sequence is
recommended:
1. Connect the ground pins (VSUB).
2. Supply the appropriate biases and clocks to the
remaining pins.
Table 8. DC BIAS OPERATING CONDITIONS
Description
Symbol
Minimum
Nominal
Maximum
Units
Reset Drain
RD
11.3
11.5
11.7
V
Output Amplifier Return
VSS
Output Amplifier Supply
VDD
Substrate
SUB
14.5
0.7
V
15.0
V
0
V
Output Gate
OG
−2.3
−2.5
−2.7
V
Lateral Drain/Guard
LOD
10.8
11.0
11.2
V
Video Output Load Current
IOUT
−5
−10
mA
1. An output load sink must be applied to each of the four VOUT pins to activate output amplifier – see Figure 4.
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15
Notes
1
KAF−16200
AC Operating Conditions
Table 9. CLOCK LEVELS
Description
Symbol
Level
Minimum
Nominal
Maximum
Units
Vertical CCD Clock
−Phase 1
V1
Low
−8.8
−9.0
−9.2
V
High
2.3
2.5
2.7
V
Vertical CCD Clock
−Phase 2
V2
Low
−8.8
−9.0
−9.2
V
High
3.3
3.5
3.7
V
Horizontal CCD
Clock − Phase 1
H1
Horizontal CCD
Clock − Phase 2
H2
Horizontal CCD
Clock − Phase 1
(Last)
H1L
Reset Gate
RG
Low
−3.8
−4.0
−4.2
V
High
1.8
2.0
2.2
V
Low
−3.8
−4.0
−4.2
V
High
1.8
2.0
2.2
V
Low
−5.8
−6.0
−6.2
V
High
1.8
2.0
2.2
V
Low
0.8
1.0
1.2
V
High
7.8
8.0
8.2
V
1. All pins draw less than 10 A DC current.
2. Capacitance values relative to SUB (substrate).
3. Capacitance values of left and right pins combined where appropriate.
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Effective
Capacitance
Notes
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
KAF−16200
TIMING
Table 10. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
H1, H2 Clock Frequency
fH
V1, V2 Rise, Fall Times
tV1r, tV1f
Minimum
Nominal
Maximum
Units
Notes
24
MHz
1, 2
2
ms
V1 − V2 Cross−Over
VVCR
0
1
2
V
H1 − H2 Cross−Over
VHCR
−2
−1
0
V
H1L Rise − H2 Fall Crossover
VH1LCR
Vccd to Hccd Transfer
−1
V
Tvh
5
ms
V1, V2 Clock Pulse Width
tV
8
ms
Pixel Period (1 Count)
te
41.67
ns
Line Time
Readout Time
Frame Rate
tline
219
ms
treadout
0.81
s
tframe
1.23
fps
Integration Time
1.
2.
3.
4.
tint
2
3
4
50% duty cycle values.
CTE will degrade above the nominal frequency.
treadout = tline * 3695 lines
Integration time is user specified.
Edge Alignment
Tv-h = 2*Tvhigh+2*Tvrise+Tvcross+TvhCTE
Tvrise
Tvhigh
Tvcross
Tvhigh
Tvrise
Tvhcte
V2
V1
Vvcr
Hccd
clock
Hccd
clock
Figure 18. Detail of Vertical Clock Timing
The falling edge of V1 transfers charge between rows. The
falling edge of V2 transfers the Vccd charge packet from V2
into Hccd phase H1. To allow for full charge transfer from
the Vccd to the Hccd, a delay tvhcte is required between the
falling edge of V2 and the start of Hccd clocking.
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KAF−16200
Frame Timing
Row annotation: [row# transferred to Hccd] : row
assignment.
Row #3695 is the last row (optical injection). Any
overclock beyond that sends null values to the Hccd.
KAF−16200 Frame Timing
treadout
tint
Line
1:LOD
2: dark#1
3694:dk#60
3
Figure 19. Frame Timing
The integration of dark and photo−signal in the Vccd is
continuous, as there is no pixel reset mechanism. “tint” may
refer to the time the Vccd clocks are static, and therefore
avoid image smear during readout.
Line Timing
KAF−16200 Line Timing
tV
tV
tline
tvhcte
V1
V2
H1
4641 Cnts
H2
4641: no overclock of Hccd
Figure 20. Line Timing
Pixel Timing
H1
H2
RG
VOUT
Figure 21. Pixel Timing
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KAF−16200
REFERENCES
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
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19
KAF−16200
MECHANICAL INFORMATION
Completed Assembly
Figure 22. Completed Assembly Drawing
Figure 23. Die Placement
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20
KAF−16200
Cover Glass Specification
1. Scratch and dig: 20 micron max
2. Substrate material: Schott D263T eco @ 1 mm thickness
3. Multilayer anti−reflective coating.
ON Semiconductor and the
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at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
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