KAF 16803 D

KAF-16803
4096 (H) x 4096 (V) Full
Frame CCD Image Sensor
Description
The KAF−16803 image sensor is a redesigned version of the
popular KAF−16801 image sensor (4096 (H) × 4096 (V) pixel
resolution), with enhancements that specifically target the needs of
high performance digital radiography applications. Improvements
include enhanced quantum efficiency for improved DQE at higher
spatial frequencies, lower noise for improved contrast in areas of high
density, and anti-blooming protection to prevent image bleed from
over exposure in regions outside the patient.
The sensor utilizes the TRUESENSE Transparent Gate Electrode to
improve sensitivity compared to the use of a standard front side
illuminated polysilicon electrode, as well as microlenses to maximize
light sensitivity. When combined with large imaging area and small
pixel size, the KAF−16803 provides the sensitivity, resolution and
contrast necessary for high quality digital radiographs.
To simplify device integration, the KAF−16803 image sensor uses
the same pin-out and package as the KAF−16801 image sensor.
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Figure 1. KAF−16803 CCD Image Sensor
Table 1. GENERAL SPECIFICATIONS
Parameter
Features
Typical Value
Architecture
Full Frame CCD, Square Pixels
Total Number of Pixels
4145 (H) × 4128 (V) = 17.1 Mp
Number of Effective Pixels
4127 (H) × 4128 (V) = 17.0 Mp
Number of Active Pixels
4096 (H) × 4096 (V) = 16.8 Mp
Pixel Size
9.0 mm (H) × 9.0 mm (V)
Active Image Size
36.8 mm (H) × 36.8 mm (V)
52.1 mm Diagonal
645 1.3x Optical Format
Aspect Ratio
1:1
Horizontal Outputs
1
Saturation Signal
100,000 electrons
Output Sensitivity
22 mV/e−
Quantum Efficiency (550 nm)
60%
• TRUESENSE Transparent Gate Electrode
•
•
•
•
•
for High Sensitivity
High Resolution
Large Image Area
High Quantum Efficiency
Low Noise Architecture
Board Dynamic Range
Application
• Medical
• Scientific
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
V/mJ/cm2
Responsivity (550 nm)
28.7
Read Noise (f = 4 MHz)
9 e−
Dark Signal
3 e−/pix/sec
Dark Current Doubling
Temperature
6.3°C
Linear Dynamic Range
(f = 4 MHz)
80 dB
Blooming Protection
(4 ms Exposure Time)
> 100 X Saturation Exposure
Maximum Date Rate
10 MHz
Package
CERDIP (Sidebrazed, CuW)
Cover Glass
AR Coated, 2 Sides and Taped Clear
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 2
1
Publication Order Number:
KAF−16803/D
KAF−16803
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAF−16803 IMAGE SENSOR
Part Number
Description
KAF−16803−ABA−DD−BA
Monochrome, Microlens, CERDIP Package (Sidebrazed, CuW),
AR Coated 2 Sides, Standard Grade
KAF−16803−ABA−DD−AE
Monochrome, Microlens, CERDIP Package (Sidebrazed, CuW),
AR Coated 2 Sides, Engineering Sample
KAF−16803−ABA−DP−BA
Monochrome, Microlens, CERDIP Package (Sidebrazed, CuW),
Taped Clear Cover Glass, Standard Grade
KAF−16803−ABA−DP−AE
Monochrome, Microlens, CERDIP Package (Sidebrazed, CuW),
Taped Clear Cover Glass, Engineering Sample
Marking Code
KAF−16803−ABA
Serial Number
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−16803
DEVICE DESCRIPTION
Architecture
1 Test Row
9
1
V1
V2
4 13
20 1
KAF−16803
4096 (H) × 4096 (V)
9.0 × 9.0 mm Pixels
LOD
1 9 12 6
OG
RD
1
20 Dark
RG
VDD
VOUT
VSS
1 6 4 1 3
20 1
4096
SUB
H1
1 9 12
H2
Figure 2. Block Diagram
Each line is composed of dummy pixels, internal test
pixels, active buffer pixels, and valid photoactive pixels.
different from those in the imaging array and are not counted
in the active pixel count.
Dummy Pixels
Within each horizontal shift register the first pixels are 11
dummy pixels and should not be used to determine a dark
reference level.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the device. These photon-induced
electrons are collected locally by the formation of potential
wells at each pixel site. The number of electrons collected is
linearly dependent on light level and exposure time and
non-linearly dependent on wavelength. When the pixel’s
capacity is reached, excess electrons are discharged into the
lateral overflow drain to prevent crosstalk or ‘blooming’.
During the integration period, the V1 and V2 register clocks
are held at a constant (low) level.
Internal Test
The next 4 pixels are introduced into the design to
facilitate production testing. These behave differently than
the buffer and dark pixels and should not be used to establish
a dark reference. The last three pixels in each line are also
internal test pixels and should not be used to establish a dark
reference.
Dark Reference Pixels
Surrounding the periphery of the device is a border of light
shielded pixels creating a dark region. Within this dark
region, exist light shielded pixels that include 20 leading
dark pixels on every line. There are also 20 full dark lines at
the start and 9 full dark lines at the end of every frame. Under
normal circumstances, these pixels do not respond to light
and may be used as a dark reference.
Charge Transport
The integrated charge from each pixel is transported to the
output using a two-step process. Each line (row) of charge
is first transported from the vertical CCDs to a horizontal
CCD register using the V1 and V2 register clocks.
The horizontal CCD is presented a new line on the falling
edge of V2 while H1 is held high. The horizontal CCDs then
transport each line, pixel by pixel, to the output structure by
alternately clocking the H1 and H2 pins in a complementary
fashion.
Active Buffer Pixels
There is 1 photoactive buffer row and column adjacent to
the valid photoactive pixels. These may have signals levels
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3
KAF−16803
Horizontal Register
Output Structure
H2
H1
HCCD
Charge
Transfer
VDD
OG
RG
RD
Floating
Diffusion
VOUT
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 3. Output Architecture
the reset gate (RG) is clocked to remove the signal and FD
is reset to the potential applied by reset drain (RD).
Increased signal at the floating diffusion reduces the voltage
seen at the output pin. To activate the output structure, an
off-chip current source must be added to the VOUT pin of
the device. See Figure 4.
The output consists of a floating diffusion capacitance
connected to a three-stage source follower. Charge
presented to the floating diffusion (FD) is converted into
a voltage and is current amplified in order to drive off-chip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the FD.
Once the signal has been sampled by the system electronics,
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4
KAF−16803
Output Load
VDD = +15 V
0.1 mF
IOUT = |5 mA|
VOUT
2N3904 or
Equivalent
Buffered
Video
Output
140 W
1 kW
NOTE: Component values may be revised based on operating conditions and other design considerations.
Figure 4. Recommended Output Structure Load Diagram
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5
KAF−16803
Physical Description
Pin Description and Device Orientation
34 V2
SUB 1
33 V2
V2 2
(4096, 4096)
V2 3
32 V1
V1 4
31 V1
V1 5
30 SUB
LOD 6
29 N/C
N/C 7
28 N/C
N/C 8
27 N/C
SUB* 9
26 N/C
SUB* 10
25 SUB*
SUB 11
24 N/C
OG
12
23 N/C
VDD
13
22 N/C
VOUT 14
21 N/C
VSS 15
20 H2
Pixel (1, 1)
RD
16
19 H1
RG
17
18 SUB
Notes:
1. Pins with the same name are to be tied together on the circuit board and have the same timing.
2. Unlike the KAF−16801, pins 9, 10, and, 25 are internally connected to SUB. They may be connected to SUB on the printed circuit board
or otherwise must be left floating.
Figure 5. Device Orientation and Pinout
Table 3. PIN DESCRIPTION
Pin
Name
Substrate
18
SUB
V2
Vertical CCD Clock − Phase 2
19
H1
Horizontal CCD Clock − Phase 1
V2
Vertical CCD Clock − Phase 2
20
H2
Horizontal CCD Clock − Phase 2
Pin
Name
1
SUB
2
3
4
Description
Description
Substrate
V1
Vertical CCD Clock − Phase 1
21
N/C
No Connection
5
V1
Vertical CCD Clock − Phase 1
22
N/C
No Connection
6
LOD
Anti Blooming Drain
23
N/C
No Connection
N/C
No Connection
7
N/C
No Connection
24
8
N/C
No Connection
25
SUB*
Substrate or No Connection
9
SUB*
Substrate or No Connection
26
N/C
No Connection
10
SUB*
Substrate or No Connection
27
N/C
No Connection
11
SUB
Substrate
28
N/C
No Connection
12
OG
Output Gate
29
N/C
No Connection
13
VDD
Output Amplifier Supply
30
SUB
Substrate
14
VOUT
Video Output
31
V1
Vertical CCD Clock − Phase 1
15
VSS
Amplifier Supply Returen
32
V1
Vertical CCD Clock − Phase 1
16
RD
Reset Drain
33
V2
Vertical CCD Clock − Phase 2
17
RG
Reset Gate
34
V2
Vertical CCD Clock − Phase 2
*Unlike the KAF−16801, pins 9, 10, and, 25 are internally connected to SUB. They may be connected to SUB on the printed circuit board or must
be left floating
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KAF−16803
IMAGING PERFORMANCE
Table 4. TYPICAL OPERATIONAL CONDITIONS
Description
Condition − Unless Otherwise Noted
Integration Time (tINT)
Notes
Variable
Horizontal Clock Frequency
4 MHz
Temperature
25°C
Mode
Room Temperature
Integrate − Readout Cycle
Operation
Nominal Operating Voltages and Timing with Min. Vertical Pulse
Width tVw = 20 ms
Table 5. SPECIFICATIONS
Symbol
Min.
Nom.
Max.
Units
Notes
Verification
Plan
VSAT
Ne−SAT
1,900
85,000
2,200
100,000
−
−
mV
e−
1
Die11
QE(MAX)
−
60
−
%
1
Design12
Responsivity (550)
R(MAX)
−
28.7
−
V/mJ/cm2
Photoresponse Non-Linearity
PRNL
−
1
−
%
2
Design12
Photoresponse Non-Uniformity
PRNU
−
1
−
%
3
Design12
VDARK,INT
−
−
3
0.6
15
3
e−/pix/sec
pA/cm2
4
Die11
VDARK,READ
−
45
225
electrons
10
Die11
DSNU
−
3
15
e−/pix/sec
5
Die11
DT
−
6.3
−
Description
Saturation Signal
Quantum Efficiency (550 nm)
Integration Dark Signal
Readout Dark Signal
Dark Signal Non-Uniformity
Dark Signal Doubling Temperature
Design12
°C
Design12
6
Design12
dB
7
Design12
−
VSAT
8
Design12
22
−
mV/e−
−
VRD − 3.0
VRD − 2.0
V
f−3dB
−
100
−
MHz
Design12
ROUT
−
160
200
W
Die11
Read Noise
NR
−
9
15
Linear Dynamic Range
DR
−
80
−
Blooming Protection
XAB
100
−
Output Amplifier Sensitivity
VOUT/Ne−
20
DC Offset, Output Amplifier
VODC
Output Amplifier Bandwidth
Output Impedance, Amplifier
1.
2.
3.
4.
5.
6.
7.
e−
rms
Design12
9
Die11
Increasing output load currents to improve bandwidth will decrease these values.
Worst case deviation from straight line fit, between 1% and 90% of VSATmin.
One sigma deviation of a 128 × 128 sample when CCD illuminated uniformly.
Average of all pixels with no illumination at 25°C.
Average dark signal of any of 32 × 32 blocks within the sensor (Each block is 128 × 128 pixels).
Output amplifier noise at 25°C, operating at pixel frequency up to 4 MHz, bandwidth < 10 MHz, tINT = 0, and no dark current shot noise.
20log (VSAT / VN) − see Note 6 and Note 1.
VN = NR ⋅ Q / V.
8. XAB is the number of times above the VSAT illumination level that the sensor will bloom by spot size doubling. The spot size is 10% of the
imager height. XAB is measured at 4 ms.
9. Video level offset with respect to ground.
10. Readout dark current per pixel measured at 25°C and vertical CCD clock width = 20 ms.
11. A parameter that is measured on every sensor during production testing.
12. A parameter that is quantified during the design verification activity.
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7
KAF−16803
TYPICAL PERFORMANCE CURVES
KAF−16803 Spectral Response
(No Cover Glass)
1
0.9
Quantum Efficiency
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
400
500
600
700
800
900
1000
1100
Wavelength (nm)
Figure 6. Typical Spectral Response
KAF−16803 Angle Response
1.1
1
0.9
Normalized Angle Response
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Horizontal
0.1
Vertical
0
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
Degrees
Figure 7. Typical Angle Response
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8
20
25
30
35
40
KAF−16803
KAF−16803 Dark Current
1000
100
Electrons
10
1
−40
−20
0
20
40
60
0.1
Integration
Read out
0.01
Temperature (5C)
Figure 8. Dark Current
Noise Floor
KAF−16803 Noise Floor
System Noise = 6.9 electrons (10 MHz Bandwidth)
25
Noise (electrons)
20
15
10
5
0
−20
−10
0
10
20
Temperature (5C)
Total Noise (Dark current, amplifier, system)
CCD only (dark current, amplifier)
Figure 9. Noise Floor
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9
30
40
KAF−16803
DEFECT DEFINITIONS
Table 6. SPECIFICATIONS (All defect tests performed at T = 25°C)
Classification
Point
Cluster
Column
Standard Grade
< 200
< 20
< 10
Point Defects
Dark: A pixel which deviates by more than 6% from
neighboring pixels when illuminated to 70% of saturation.
Bright: A pixel with a dark current > 3,000 e−/pixel/sec at
25°C.
A column that does not meet the CTE specification for all
exposures less than the specified maximum saturation signal
level and greater than 2 ke−.
A column that contains a pixel which loses more than
250 e− under 2 ke− illumination (Trap defect).
Cluster Defect
A grouping of not more than 10 adjacent point defects.
Column defects are separated by no less than 4 good
columns. No multiple column defects (double or more) will
be permitted.
Cluster defects are separated by no less than 4 good pixels
in any direction.
Column and cluster defects are separated by at least 4
good columns in the x direction.
Column Defect
A grouping of more than 10 point defects along a single
column.
A column containing a pixel with dark current
> 15,000 e−/pixel/sec (Bright column).
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10
KAF−16803
OPERATION
Table 7. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Diode Pin Voltages
VDIODE
−0.5
20
V
1, 2
Gate Pin Voltages
VGATE1
−16
16
V
1, 3
Adjacent Gate Voltages
V1−2
−16
16
V
4
Output Bias Current
IOUT
−
−30
mA
5
LOD Diode Voltage
VLOD
−0.5
13.0
V
1
Operating Temperature
TOP
−60
60
°C
7
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to pin SUB.
2. Includes pins: RD, VDD, VSS, VOUT.
3. Includes pins: V1, V2, H1, H2, RG, VOG.
4. Voltage difference between adjacent gates. Includes: V1 to V2; H1 to H2; H1 to VOG; and V2 to H1.
5. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher currents and
lower load capacitance at the expense of reduced gain (sensitivity).
6. Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or condition
is exceeded, the device will be degraded and may be damaged.
7. Noise performance will degrade at higher temperatures.
Power-Up Sequence
The sequence chosen to perform an initial power-up is not
critical for device reliability. A coordinated sequence may
minimize noise and the following sequence is
recommended:
1. Connect the ground pins (SUB).
2. Supply the appropriate biases and clocks to the
remaining pins.
Table 8. DC BIAS OPERATING CONDITIONS
Description
Reset Drain
Symbol
Minimum
Nominal
Maximum
Units
Maximum DC
Current (mA)
VRD
12.75
13
13.625
V
IRD = 0.01
Output Amplifier Supply
VSS
1.75
2.0
2.25
V
ISS = 3.0
Output Amplifier Return
VDD
14.75
15.0
17.0
V
IOUT + ISS
Substrate
VSUB
0
0
0
V
0.01
Output Gate
VOG
1.0
2.0
2.5
V
0.01
Lateral Overflow Drain
VLOD
7.75
8.0
8.25
V
0.01
Video Output Current
IOUT
−3
−5
−7
mA
Notes
1
1. An output load sink must be applied to VOUT to activate output amplifier – see Figure 4.
AC Operating Conditions
Table 9. CLOCK LEVELS
Description
Symbol
Level
Minimum
Nominal
Maximum
Units
Notes
V1 Low Level
V1L
Low
−9.2
−9.0
−8.8
V
1
V1 High Level
V1H
High
2.3
2.5
2.7
V
1
V2 Low Level
V2L
Low
−9.2
−9.0
−8.8
V
1
V2 High Level
V2H
High
2.3
2.5
2.7
V
1
H1 Low Level
H1L
Low
−3.2
−3.0
−2.8
V
1
H1 High Level
H1H
High
6.8
7.0
7.2
V
1
1. All pins draw less than 10 mA DC current. Capacitance values relative to SUB (substrate).
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11
KAF−16803
Table 9. CLOCK LEVELS (continued)
Description
Symbol
Level
Minimum
Nominal
Maximum
Units
Notes
H2 Low Level
H2L
Low
−3.2
−3.0
−2.8
V
1
H2 High Level
H2H
High
6.8
7.0
7.2
V
1
RG Low Level
RGL
Low
5.8
6.0
6.2
V
1
RG High Level
RGH
High
10.8
11.0
11.2
V
1
1. All pins draw less than 10 mA DC current. Capacitance values relative to SUB (substrate).
Capacitance Equivalent Circuit
LOD
CLOD_V1
CLOD
CLOD_V2
CV1_V2
V2
V1
CV1
CV2
CVH
CH1_H2
H1
H2
CH2
CH1
CH1_OG
RG
OG
COG
CRG
Figure 10. Equivalent Circuit Model
Table 10.
Description
Label
Value
Unit
LOD−Sub Capacitance
CLOD
6.5
nF
LOD−V1 Capacitance
CLOD_V1
36
nF
LOD−V2 Capacitance
CLOD_V2
36
nF
V1−V2 Capacitance
CV1_V2
80
nF
V1−Sub Capacitance
CV1_SUB
250
nF
V2−Sub Capacitance
CV2_SUB
250
nF
V2−H1 Capacitance
CVH
36
pF
H1−H2 Capacitance
CH1_H2
75
pF
H1−Sub Capacitance
CH1_Sub
500
pF
H2−Sub Capacitance
CH2_Sub
300
pF
OG−Sub Capacitance
COG_Sub
5
pF
RG−Sub Capacitance
CRG_Sub
13
pF
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KAF−16803
TIMING
Table 11. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
H1, H2 Clock Frequency
fH
−
4
10
MHz
1
H1, H2 Rise, Fall Times
tH1r, tH1f
5
−
−
%
3
V1, V2 Rise, Fall Times
3
tV1r, tV1f
5
−
−
%
V1 − V2 Cross-Over
VVCR
−1
0
1
V
H1 − H2 Cross-Over
VHCR
1
2
5
V
tHS
5
10
−
ms
tRGw
5
10
−
ns
tVw
20
20
−
ms
ns
H1, H2 Setup Time
RG Clock Pulse Width
V1, V2 Clock Pulse Width
Pixel Period (1 Count)
4
te
100
250
−
Integration Time
tINT
−
−
−
Line Time
tLINE
0.460
1.08
−
ms
6
tREADOUT
1,897
4,450
−
ms
7
Readout Time
1.
2.
3.
4.
5.
6.
7.
5
50% duty cycle values.
CTE will degrade above the maximum frequency.
Relative to the pulse width (based on 50% of high/low levels).
RG should be clocked continuously.
Integration time is user specified.
(4145 ⋅ te) + tHS + (2 ⋅ tVw) = 1.08 ms
tREADOUT = tLINE ⋅ 4128 lines
Edge Alignment
H1
VHCR
H2
V1
V2
VVCR
V1, V2
Figure 11. Edge Alignment
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13
2
KAF−16803
Frame Timing
1 Frame = 4128 Lines
tREADOUT
tINT
V2
Line
V1
1
2
3
4127
4128
H2
H1
Figure 12. Frame Timing
Frame Timing Detail
90%
V1
10%
tVw
tV1r
tV1f
90%
V2
10%
tV2r
tV2f
Figure 13. Frame Timing Detail
Line Timing (Each Output)
Ä
ÇÇ
ÇÇ
Ä
tLINE
tV
V2
tHS
V1
tV
ÇÇ
ÇÇ
ÄÄ
ÄÄ
te
H2
4145
H1
Line Content
4096 Active Pixels/Line
36
16−35
12−15
1−11
37 − 4132
4143−4145
H1/H2 Count Values
Internal Test Pixels
Active Buffer Pixels
Dummy Pixels
Photoactive Pixels**
Dark Reference Pixels*
RG
Figure 14. Line Timing
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14
4133
4134−4142
Ç
Ç
KAF−16803
Pixel Timing
te
tRG
1 Count
RG
H1
H2
VDARK + VOF
tRV
VOUT
VVRG
VOD
VVSUB
VSAT
Figure 15. Pixel Timing
Pixel Timing Detail
90%
tRG
RGAMP
RG
10%
RGLOW
tRGr
tRGf
90%
H1, H2
50%
H1,H2AMP
10%
H1LOW
H2LOW
te / 2
tH1
Figure 16. Pixel Timing Detail
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15
tH2
KAF−16803
Example Waveforms
Video Waveform Horizontal CCD Clocks
Figure 17. Horizontal Clock Waveform
Figure 18. Video Waveform
NOTE: Video Waveform – The bottom curve was taken at the CCD output. The top curve is bandwidth limited and was measured at the
analog to digital converter.
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KAF−16803
Video Waveform and Clamp Clock
Figure 19. Video and Clamp
Video Waveform and Sample Clock
Figure 20. Video and Sample Clock
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17
KAF−16803
STORAGE AND HANDLING
Table 12. STORAGE CONDITIONS
Description
Storage Temperature
Symbol
Minimum
Maximum
Units
Notes
TST
−20
70
°C
1
1. Long-term storage toward the maximum temperature will accelerate color filter degradation (This condition applies to color parts only).
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
www.onsemi.com
18
KAF−16803
MECHANICAL INFORMATION
Completed Assembly
Figure 21. Completed Assembly (1 of 1)
www.onsemi.com
19
KAF−16803
Cover Glass Specification
1. Scratch and dig: 10 micron max
2. Substrate material Schott D263T eco or equivalent
3. Multilayer anti-reflective coating
Table 13.
Wavelength
Total Reflectance
420−450
≤ 2%
450−630
≤ 1%
630−680
≤ 2%
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KAF−16803/D