ENA2119 D

Ordering number : ENA2119A
LC75805PE
CMOS IC
1/1 to 1/4 Duty General-Purpose
LCD Display Driver with LED Driver
http://onsemi.com
Overview
LC75805PE is the 1/1 to 1/4 duty general-purpose LCD display driver with the LED driver to use for the instrument
panel display by control with the controller. In addition, LC75805PE is able to drive up to 48 LED and LCD of up to
140 segments directly, and has a built-in 7ch PWM function for brightness adjustment of LED. Furthermore, because
of built-in the oscillator circuit, it is possible to reduce external resister and capacitor for oscillation.
Features
 Switch of Static Drive, 1/2 Duty Drive, 1/3 Duty Drive and 1/4 Duty Drive can be controlled by serial data.
Static Drive (1/1 Duty Drive) : Capable of driving up to 38 segments.
1/2 Duty Drive
: Capable of driving up to 74 segments.
1/3 Duty Drive
: Capable of driving up to 108 segments.
1/4 Duty Drive
: Capable of driving up to 140 segments.
 Frame frequency of common and segment output waveform can be controlled by serial data.
 Turning on/off LED can be controlled by serial data. (Capable of driving up to 48 LED)
 Built-in 7ch PWM function for brightness adjustment of LED. (Resolution of 128 steps)
 Frame frequency of LED driver output waveform can be controlled by serial data.
 Serial data input supports CCB format communication with the system controller. (Support 5V operation)
 Backup function and forced turning off all segments by power-saving mode can be controlled by serial data.
 Switch of the internal oscillator operating mode and the external clock operating mode can be controlled by serial
data.
 High generality, since display data is displayed directly without the intervention of a decoder circuit.
 The INH pin allows the display to be forced to the off state.
 Built-in Oscillator circuit (Built-in resister and capacitor for oscillation)

CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
QIP100E(14X20)

CCB is a registered trademark of Semiconductor Components Industries, LLC.
ORDERING INFORMATION
See detailed ordering and shipping information on page 34 of this data sheet.
Semiconductor Components Industries, LLC, 2013
December, 2013
D0413HK/50113HKPC 20121031-S00003 No.A2119-1/34
LC75805PE
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter
Symbol
Conditions
Ratings
VDD max
Input voltage
VIN1
CE, CL, DI, INH, OSCI
Output voltage
VOUT1
S1 to S38, COM1 to COM4
VOUT2
LD1 to LD48
IOUT1
S1 to S38
IOUT2
COM1 to COM4
IOUT3
LD1 to LD48
Allowable power dissipation
Pd max
Ta=95C
Operating temperature
Topr
-40 to +95
C
Storage temperature
Tstg
-55 to +150
C
Output current
VDD
Unit
Maximum supply voltage
-0.3 to +6.5
V
-0.3 to +6.5
V
-0.3 to VDD+0.3
V
-0.3 to +35
A
300
3
mA
30
400
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +95C, VSS = 0V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Supply voltage
VDD
VDD
4.5
5.5
Input high-level voltage
VIH1
CE, CL, DI, INH
0.8VDD
5.5
VIH2
OSCI
0.8VDD
5.5
Input low-level voltage
VIL1
CE, CL, DI, INH
0
0.2VDD
VIL2
OSCI
0
0.2VDD
V
V
V
Output pull-up voltage
VOUP
LD1 to LD48, VDD = 4.5 to 5.5V
30
V
External clock operating frequency
fCK
OSCI, External clock operating mode
[Fig 3]
100
300
600
kHz
External clock duty
DCK
OSCI, External clock operating mode
[Fig 3]
30
50
70
%
Data setup time
tds
CL, DI
[Fig 1], [Fig 2]
160
ns
Data hold time
tdh
CL, DI
[Fig 1], [Fig 2]
160
ns
CE wait time
tcp
CE, CL
[Fig 1], [Fig 2]
160
ns
CE setup time
tcs
CE, CL
[Fig 1], [Fig 2]
160
ns
CE hold time
tch
CE, CL
[Fig 1], [Fig 2]
160
ns
High-level clock pulse width
tH
CL
[Fig 1], [Fig 2]
160
ns
Low-level clock pulse width
tL
CL
[Fig 1], [Fig 2]
160
Rise time
tr
CE, CL, DI
[Fig 1], [Fig 2]
160
ns
[Fig 1], [Fig 2]
160
ns
Fall time
tf
CE, CL, DI
INH switching time
tc
INH, CE
0
[Fig 4], [Fig 5], [Fig 6], [Fig 7]
10
ns
s
No.A2119-2/34
LC75805PE
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin
Conditions
Ratings
min
typ
Unit
max
Hysteresis
VH
CE, CL, DI, INH
Input high-level current
IIH1
CE, CL, DI, INH
VI = 5.5V
5.0
IIH2
OSCI
VI = 5.5V
5.0
Input low-level current
0.1VDD
IIL1
CE, CL, DI, INH
VI = 0V
-5.0
IIL2
OSCI
VI = 0V
-5.0
Output OFF leak current
IOFFH
LD1 to LD48
VO = 30V
Output high-level voltage
VOH1
S1 to S38
IO = -20A
VDD-0.9
VOH2
COM1 to COM4
IO = -100A
VDD-0.9
Output low-level voltage
Output middle-level
VOL1
S1 to S38
IO = 20A
VOL2
COM1 to COM4
IO = 100A
VOL3
LD1 to LD48
IO = 20mA
VMID1
S1 to S36
1/3 bias IO = ±20A
voltage
V
A
5.0
0.9
0.9
0.25
2/3VDD
2/3VDD
-0.9
+0.9
1/3VDD
1/3 bias IO = ±20A
1/3VDD
-0.9
+0.9
VMID3
COM1 to COM4
1/3 bias IO = ±100A
2/3VDD
2/3VDD
-0.9
+0.9
1/3VDD
1/3VDD
1/3 bias IO = ±100A
VMID5
COM1, COM2
1/2 bias IO = ±100A
Oscillator frequency
fosc
Oscillator circuit
Internal oscillator operating mode
Current drain
IDD1
VDD
Power save mode
IDD2
VDD
VDD = 5.5V
Output open,
-0.9
+0.9
1/2VDD
1/2VDD
-0.9
240
V
0.5
S1 to S36
COM1 to COM4
A
V
VMID2
VMID4
A
V
+0.9
300
360
kHz
15
750
1500
Internal oscillator operating mode
IDD3
VDD
VDD = 5.5V
Output open,
External clock operating mode
fCK = 300kHz
A
750
1500
VIH2 = 0.9VDD
VIL2 = 0.1VDD
* Electrical Characteristics might be changed for the improvement without notice.
No.A2119-3/34
LC75805PE

1. When CL is stopped at the low level.
VIH1
tH
VIH1
50%
VIL1
CL
tf
 
tr
VIH1
DI
VIL1
tds
tcp
  
tL
VIL1
 
CE
tcs
tch
tdh
[Fig 1]

2. When CL is stopped at the high level.
VIH1
VIL1

CE

tH
VIH1
50%
VIL1
tf
  
CL
tr
tcp
tcs
VIH1
DI
VIL1
tds
 
tL
tch
tdh
[Fig 2]
3. OSCI pin clock timing in external clock operating mode.
tCKH
OSCI
VIH2
50%
VIL2
tCKL
fCK =
1
[kHz]
tCKH + tCKL
tCKH
 100[%]
DCK=
tCKH + tCKL
[Fig 3]
No.A2119-4/34
LC75805PE
Package Dimensions
unit : mm
PQFP100 14x20 / QIP100E
CASE 122BV
ISSUE A
0.8±0.2
23.2±0.2
17.2±0.2
100
14.0±0.1
20.0±0.1
12
+0.15
0.65
0.3±0.05
0.1±0.1 (2.7)
3.0 MAX
(0.58)
0.15 −0.05
0.13
0~10°
0.10
SOLDERING FOOTPRINT*
22.30
GENERIC
MARKING DIAGRAM*
0.65
0.43
1.30
16.30
(Unit: mm)
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
XXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
No.A2119-5/34
LC75805PE
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
COM4/S36
COM3/S37
COM2/S38
COM1
VSS
LD48
LD47
LD46
Pin Assignment
51
80
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
VDD
VSS
OSCI
INH
CE
CL
DI
81
50
LC75805PE
(QIP100E)
31
100
1
LD45
LD44
LD43
LD42
LD41
LD40
LD39
LD38
LD37
LD36
LD35
LD34
LD33
VSS
VSS
LD32
LD31
LD30
LD29
LD28
VSS
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
LD16
VSS
VSS
LD17
LD18
LD19
LD20
LD21
LD22
LD23
LD24
LD25
LD26
LD27
30
Top view
SEGMENT DRIVER
COMMON
DRIVER
LD2
LD1
LD48
LD47
COM4/S36
COM3/S37
COM2/S38
COM1
S34
S35
S1
S2
S3
S4
S5
Block Diagram
LED DRIVER
INH
OSCI
CLOCK
GENERATOR
DISPLAY REGISTER
&
CONTROL REGISTER
VDD
SHIFT REGISTER
LCD DRIVE BIAS
VOLTAGE
STABILIZATION
CIRCUIT
2/3VDD
1/3VDD
1/2VDD
CCB INTERFACE
CE
CL
DI
VSS
No.A2119-6/34
LC75805PE
Pin Functions
Handling
Symbol
Pin No.
Function
Active
I/O
when
unused
LD1 to LD16
2 to 17
LD17 to LD32
20 to 35
LD33 to LD48
38 to 53
These are LED driver output pins that display the display data for LED transferred
by serial data input, and high- voltage open-drain output pins. (Pull-up voltage is
30[V] maximum.) In addition, brightness adjustment of LED is possible by PWM
55
These are common driver output pins, and Frame frequency is fo [Hz].
COM2/S38
56
COM2/S38, COM3/S37 and COM4/S36 are possible to be used as the segment
COM3/S37
57
output by control data.
COM4/S36
58
59 to 93
O
OPEN
-
O
OPEN
-
O
OPEN
-
I
GND
H
I
-
I
L
I
GND
-
-
-
-
-
-
function, too.
COM1
S35 to S1
-
These are segment output pins that display the display data for LCD transferred by
serial data input.
This is input pin for the external clock.
OSCI
96
Input the clock whose frequency (fCK) is between 100 and 600[kHz] at external
clock operating mode.
Furthermore, connect to GND at internal oscillator operating mode.
CE
98
CL
99
DI
100
These are input pins for serial data transfer, and connect to the controller.
CE: Chip enable
CL: Synchronized clock
DI: Transfer data
I
GND
Display off control input pin
• INH = Low-level (VSS) ...Display forced off
LD1 to LD48 = Z (High-impedance)
COM1 = L (VSS)
COM2/S38 to COM4/S36 = L (VSS)
INH
S1 to S35 = L (VSS)
Internal oscillator operation is stopped.
97
External clock input is forbidden.
• INH = High-level (VDD)...Display on
Internal oscillator operation is possible.
(At Internal oscillator operating mode)
External clock input is possible.
(At External clock operating mode)
However, serial data can be transferred during turn off.
VDD
94
This is power supply pin.
Supply the voltage between 4.5V and 5.5V.
1
18
19
VSS
36
37
These are power supply pins.
Connect to GND.
54
95
No.A2119-7/34
LC75805PE
Serial Data Transfer Format
1/4 Duty Drive
(1) When CL is stopped at the low level
CE
CL
DI
1
1
1
0
0
0
0
1
D133 D134 D135 D136 D137 D138 D139 D140 0
D1 D2
0
0
0
0
0
0
0 OC FC0 FC1 FC2 FC3 DT0 DT1 SC BU 0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data for LCD
140 bits
CCB address
8 bits
1
1
1
0
0
0
0
1 L1A L1B
Control data
17 bits
L45A L45B L45C L46A L46B L46C L47A L47B L47C L48A L48B L48C PF0 PF1 PF2 PF3 0
0
DD
3 bits
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Control data
148 bits
CCB address
8 bits
1
1
1
0
0
0
0
1 LT1 LT2
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
LT47 LT48 0
Display data
for LED
48 bits
0...
Fixed data
9 bits
DD
3 bits
0 W10 W11 W12 W13 W14 W15 W16 W20 W21 W22 W23 W24 W25 W26 W30 W31 W32 W33 W34 W35 W36
Fixed data
12 bits
Control data
49 bits
W40 W41 W42 W43 W44 W45 W46 W50 W51 W52 W53 W54 W55 W56 W60 W61 W62 W63 W64 W65 W66 W70 W71 W72 W73 W74 W75 W76 1
1
0
DD
3 bits
(Note 1) The input of serial data is taken in at the rising edge of CL, and latched at the falling edge of CE. In addition,
this IC has the function that counts the number of CL clock to receive the correct serial data. That is to say,
because it isn’t latched at the falling edge of CE when the number of the count of CL in each serial data is
wrong, receiving wrong serial data can be prevented.
(Note 2) DD • • • Direction Data
• CCB address .........................
• D1 to D140 ...........................
• OC ........................................
• FC0 to FC3 ...........................
• DT0, DT1 .............................
• SC .........................................
• BU ........................................
• L1A, L1B, L1C to L48A, ......
L48B, L48C
• PF0 to PF3 ............................
• LT1 to LT48 .........................
• W10 to W16, W20 to W26, ...
W30 to W36, W40 to W46,
W50 to W56, W60 to W66
W70 to W76
“87H”
Display data for LCD
Control data for switch of internal oscillator operating mode and external clock operating mode
Control data for setting of the frame frequency of common and segment output waveform
Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
Control data for turning on/off segments
Control data for switch of Normal mode and Power-saving mode
Control data for Ch settings of PWM circuits that adjust brightness of LED
Control data for setting of the frame frequency of LED driver output waveform
Display data for LED
PWM data of PWM circuits of LED driver output
No.A2119-8/34
LC75805PE
(2) When CL is stopped at the high level
CE
CL
DI
1
1
1
0
0
0
0
1
D133 D134 D135 D136 D137 D138 D139 D140 0
D1 D2
0
0
0
0
0
0
0 OC FC0 FC1 FC2 FC3 DT0 DT1 SC BU 0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data for LCD
140 bits
CCB address
8 bits
1
1
1
0
0
0
0
1
L1A L1B
Control data
17 bits
L45A L45B L45C L46A L46B L46C L47A L47B L47C L48A L48B L48C PF0 PF1 PF2 PF3 0
0
0
DD
3 bits
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Control data
148 bits
CCB address
8 bits
1
1
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
LT1 LT2
LT47 LT48 0
Display data
for LED
48 bits
0...
Fixed data
9 bits
DD
3 bits
0 W10 W11 W12 W13 W14 W15 W16 W20 W21 W22 W23 W24 W25 W26 W30 W31 W32 W33 W34 W35 W36
Fixed data
12 bits
Control data
49 bits
W40 W41 W42 W43 W44 W45 W46 W50 W51 W52 W53 W54 W55 W56 W60 W61 W62 W63 W64 W65 W66 W70 W71 W72 W73 W74 W75 W76 1
1
0
DD
3 bits
(Note 1) The input of serial data is taken in at the rising edge of CL, and latched at the falling edge of CE. In addition,
this IC has the function that counts the number of CL clock to receive the correct serial data. That is to say,
because it isn’t latched at the falling edge of CE when the number of the count of CL in each serial data is
wrong, receiving wrong serial data can be prevented.
(Note 2) DD • • • Direction Data
• CCB address .........................
• D1 to D140 ...........................
• OC ........................................
• FC0 to FC3 ...........................
• DT0, DT1 .............................
• SC .........................................
• BU ........................................
• L1A, L1B, L1C to L48A, ......
L48B, L48C
• PF0 to PF3 ............................
• LT1 to LT48 .........................
• W10 to W16, W20 to W26, ...
W30 to W36, W40 to W46,
W50 to W56, W60 to W66
W70 to W76
“87H”
Display data for LCD
Control data for switch of internal oscillator operating mode and external clock operating mode
Control data for setting of the frame frequency of common and segment output waveform
Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
Control data for turning on/off segments
Control data for switch of Normal mode and Power-saving mode
Control data for Ch settings of PWM circuits that adjust brightness of LED
Control data for setting of the frame frequency of LED driver output waveform
Display data for LED
PWM data of PWM circuits of LED driver output
No.A2119-9/34
LC75805PE
1/3 Duty Drive
(1) When CL is stopped at the low level
CE
CL
DI
1
1
1
0
0
0
0
1
D1 D2
D101 D102 D103 D104 D105 D106 D107 D108 0
0
0
0
0
0
0
0 OC FC0 FC1 FC2 FC3 DT0 DT1 SC BU 0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data for LCD
108 bits
CCB address
8 bits
1
1
1
0
0
0
0
1 L1A L1B
Control data
17 bits
L45A L45B L45C L46A L46B L46C L47A L47B L47C L48A L48B L48C PF0 PF1 PF2 PF3 0
DD
3 bits
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Control data
148 bits
CCB address
8 bits
1
1
1
0
0
0
0
1 LT1 LT2
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
LT47 LT48 0
Display data
for LED
48 bits
0...
DD
3 bits
Fixed data
9 bits
0 W10 W11 W12 W13 W14 W15 W16 W20 W21 W22 W23 W24 W25 W26 W30 W31 W32 W33 W34 W35 W36
Fixed data
12 bits
Control data
49 bits
W40 W41 W42 W43 W44 W45 W46 W50 W51 W52 W53 W54 W55 W56 W60 W61 W62 W63 W64 W65 W66 W70 W71 W72 W73 W74 W75 W76 1
1
0
DD
3 bits
(Note 1) The input of serial data is taken in at the rising edge of CL, and latched at the falling edge of CE. In addition,
this IC has the function that counts the number of CL clock to receive the correct serial data. That is to say,
because it isn’t latched at the falling edge of CE when the number of the count of CL in each serial data is
wrong, receiving wrong serial data can be prevented.
(Note 2) DD • • • Direction Data
• CCB address .........................
• D1 to D108 ...........................
• OC ........................................
• FC0 to FC3 ...........................
• DT0, DT1 .............................
• SC .........................................
• BU ........................................
• L1A, L1B, L1C to L48A, ......
L48B, L48C
• PF0 to PF3 ............................
• LT1 to LT48 .........................
• W10 to W16, W20 to W26, ...
W30 to W36, W40 to W46,
W50 to W56, W60 to W66
W70 to W76
“87H”
Display data for LCD
Control data for switch of internal oscillator operating mode and external clock operating mode
Control data for setting of the frame frequency of common and segment output waveform
Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
Control data for turning on/off segments
Control data for switch of Normal mode and Power-saving mode
Control data for Ch settings of PWM circuits that adjust brightness of LED
Control data for setting of the frame frequency of LED driver output waveform
Display data for LED
PWM data of PWM circuits of LED driver output
No.A2119-10/34
LC75805PE
(2) When CL is stopped at the high level
CE
CL
DI
1
1
1
0
0
0
0
1
D1 D2
D101 D102 D103 D104 D105 D106 D107 D108 0
0
0
0
0
0
0
0 OC FC0 FC1 FC2 FC3 DT0 DT1 SC BU 0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data for LCD
108 bits
CCB address
8 bits
1
1
1
0
0
0
0
1
L1A L1B
Control data
17 bits
L45A L45B L45C L46A L46B L46C L47A L47B L47C L48A L48B L48C PF0 PF1 PF2 PF3 0
DD
3 bits
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Control data
148 bits
CCB address
8 bits
1
1
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
LT1 LT2
LT47 LT48 0
Display data
for LED
48 bits
0...
Fixed data
9 bits
DD
3 bits
0 W10 W11 W12 W13 W14 W15 W16 W20 W21 W22 W23 W24 W25 W26 W30 W31 W32 W33 W34 W35 W36
Fixed data
12 bits
Control data
49 bits
W40 W41 W42 W43 W44 W45 W46 W50 W51 W52 W53 W54 W55 W56 W60 W61 W62 W63 W64 W65 W66 W70 W71 W72 W73 W74 W75 W76 1
1
0
DD
3 bits
(Note 1) The input of serial data is taken in at the rising edge of CL, and latched at the falling edge of CE. In addition,
this IC has the function that counts the number of CL clock to receive the correct serial data. That is to say,
because it isn’t latched at the falling edge of CE when the number of the count of CL in each serial data is
wrong, receiving wrong serial data can be prevented.
(Note 2) DD • • • Direction Data
• CCB address .........................
• D1 to D108 ...........................
• OC ........................................
• FC0 to FC3 ...........................
• DT0, DT1 .............................
• SC .........................................
• BU ........................................
• L1A, L1B, L1C to L48A, ......
L48B, L48C
• PF0 to PF3 ............................
• LT1 to LT48 .........................
• W10 to W16, W20 to W26, ...
W30 to W36, W40 to W46,
W50 to W56, W60 to W66
W70 to W76
“87H”
Display data for LCD
Control data for switch of internal oscillator operating mode and external clock operating mode
Control data for setting of the frame frequency of common and segment output waveform
Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
Control data for turning on/off segments
Control data for switch of Normal mode and Power-saving mode
Control data for Ch settings of PWM circuits that adjust brightness of LED
Control data for setting of the frame frequency of LED driver output waveform
Display data for LED
PWM data of PWM circuits of LED driver output
No.A2119-11/34
LC75805PE
1/2 Duty Drive
(1) When CL is stopped at the low level
CE
CL
DI
1
1
1
0
0
0
0
1
D1 D2
D70 D71 D72 D73 D74 0
0
0
0
0
0
0
0
0
0 OC FC0 FC1 FC2 FC3 DT0 DT1 SC BU 0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data for LCD
74 bits
CCB address
8 bits
1
1
1
0
0
0
0
1 L1A L1B
Control data
19 bits
L45A L45B L45C L46A L46B L46C L47A L47B L47C L48A L48B L48C PF0 PF1 PF2 PF3 0
DD
3 bits
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Control data
148 bits
CCB address
8 bits
1
1
1
0
0
0
0
1 LT1 LT2
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
LT47 LT48 0
Display data
for LED
48 bits
0...
Fixed data
9 bits
DD
3 bits
0 W10 W11 W12 W13 W14 W15 W16 W20 W21 W22 W23 W24 W25 W26 W30 W31 W32 W33 W34 W35 W36
Fixed data
12 bits
Control data
49 bits
W40 W41 W42 W43 W44 W45 W46 W50 W51 W52 W53 W54 W55 W56 W60 W61 W62 W63 W64 W65 W66 W70 W71 W72 W73 W74 W75 W76 1
1
0
DD
3 bits
(Note 1) The input of serial data is taken in at the rising edge of CL, and latched at the falling edge of CE. In addition,
this IC has the function that counts the number of CL clock to receive the correct serial data. That is to say,
because it isn’t latched at the falling edge of CE when the number of the count of CL in each serial data is
wrong, receiving wrong serial data can be prevented.
(Note 2) DD • • • Direction Data
• CCB address .........................
• D1 to D74 .............................
• OC ........................................
• FC0 to FC3 ...........................
• DT0, DT1 .............................
• SC .........................................
• BU ........................................
• L1A, L1B, L1C to L48A, ......
L48B, L48C
• PF0 to PF3 ............................
• LT1 to LT48 .........................
• W10 to W16, W20 to W26, ...
W30 to W36, W40 to W46,
W50 to W56, W60 to W66
W70 to W76
“87H”
Display data for LCD
Control data for switch of internal oscillator operating mode and external clock operating mode
Control data for setting of the frame frequency of common and segment output waveform
Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
Control data for turning on/off segments
Control data for switch of Normal mode and Power-saving mode
Control data for Ch settings of PWM circuits that adjust brightness of LED
Control data for setting of the frame frequency of LED driver output waveform
Display data for LED
PWM data of PWM circuits of LED driver output
No.A2119-12/34
LC75805PE
(2) When CL is stopped at the high level
CE
CL
DI
1
1
1
0
0
0
0
1
D1 D2
D70 D71 D72 D73 D74 0
0
0
0
0
0
0
0
0
0 OC FC0 FC1 FC2 FC3 DT0 DT1 SC BU 0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data for LCD
74 bits
CCB address
8 bits
1
1
1
0
0
0
0
1
L1A L1B
Control data
19 bits
L45A L45B L45C L46A L46B L46C L47A L47B L47C L48A L48B L48C PF0 PF1 PF2 PF3 0
DD
3 bits
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Control data
148 bits
CCB address
8 bits
1
1
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
LT1 LT2
LT47 LT48 0
Display data
for LED
48 bits
0...
Fixed data
9 bits
DD
3 bits
0 W10 W11 W12 W13 W14 W15 W16 W20 W21 W22 W23 W24 W25 W26 W30 W31 W32 W33 W34 W35 W36
Fixed data
12 bits
Control data
49 bits
W40 W41 W42 W43 W44 W45 W46 W50 W51 W52 W53 W54 W55 W56 W60 W61 W62 W63 W64 W65 W66 W70 W71 W72 W73 W74 W75 W76 1
1
0
DD
3 bits
(Note 1) The input of serial data is taken in at the rising edge of CL, and latched at the falling edge of CE. In addition,
this IC has the function that counts the number of CL clock to receive the correct serial data. That is to say,
because it isn’t latched at the falling edge of CE when the number of the count of CL in each serial data is
wrong, receiving wrong serial data can be prevented.
(Note 2) DD • • • Direction Data
• CCB address .........................
• D1 to D74 .............................
• OC ........................................
• FC0 to FC3 ...........................
• DT0, DT1 .............................
• SC .........................................
• BU ........................................
• L1A, L1B, L1C to L48A, ......
L48B, L48C
• PF0 to PF3 ............................
• LT1 to LT48 .........................
• W10 to W16, W20 to W26, ...
W30 to W36, W40 to W46,
W50 to W56, W60 to W66
W70 to W76
“87H”
Display data for LCD
Control data for switch of internal oscillator operating mode and external clock operating mode
Control data for setting of the frame frequency of common and segment output waveform
Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
Control data for turning on/off segments
Control data for switch of Normal mode and Power-saving mode
Control data for Ch settings of PWM circuits that adjust brightness of LED
Control data for setting of the frame frequency of LED driver output waveform
Display data for LED
PWM data of PWM circuits of LED driver output
No.A2119-13/34
LC75805PE
Static Drive (1/1 Duty Drive)
(1) When CL is stopped at the low level
CE
CL
DI
1
1
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
1
1
0
0
0
0
D1 D2
D38 0
0
0
0
0
0
0
Display data
for LCD
38 bits
1 L1A L1B
0
0
0
0
0
0
0 OC FC0 FC1 FC2 FC3 DT0 DT1 SC BU 0
Control data
23 bits
L45A L45B L45C L46A L46B L46C L47A L47B L47C L48A L48B L48C PF0 PF1 PF2 PF3 0
0
1
DD
3 bits
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Control data
148 bits
CCB address
8 bits
1
1
1
0
0
0
0
1 LT1 LT2
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
LT47 LT48 0
Display data
for LED
48 bits
0...
Fixed data
9 bits
DD
3 bits
0 W10 W11 W12 W13 W14 W15 W16 W20 W21 W22 W23 W24 W25 W26 W30 W31 W32 W33 W34 W35 W36
Fixed data
12 bits
Control data
49 bits
W40 W41 W42 W43 W44 W45 W46 W50 W51 W52 W53 W54 W55 W56 W60 W61 W62 W63 W64 W65 W66 W70 W71 W72 W73 W74 W75 W76 1
1
0
DD
3 bits
(Note 1) The input of serial data is taken in at the rising edge of CL, and latched at the falling edge of CE. In addition,
this IC has the function that counts the number of CL clock to receive the correct serial data. That is to say,
because it isn’t latched at the falling edge of CE when the number of the count of CL in each serial data is
wrong, receiving wrong serial data can be prevented.
(Note 2) DD • • • Direction Data
• CCB address .........................
• D1 to D38 .............................
• OC ........................................
• FC0 to FC3 ...........................
• DT0, DT1 .............................
• SC .........................................
• BU ........................................
• L1A, L1B, L1C to L48A, ......
L48B, L48C
• PF0 to PF3 ............................
• LT1 to LT48 .........................
• W10 to W16, W20 to W26, ...
W30 to W36, W40 to W46,
W50 to W56, W60 to W66
W70 to W76
“87H”
Display data for LCD
Control data for switch of internal oscillator operating mode and external clock operating mode
Control data for setting of the frame frequency of common and segment output waveform
Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
Control data for turning on/off segments
Control data for switch of Normal mode and Power-saving mode
Control data for Ch settings of PWM circuits that adjust brightness of LED
Control data for setting of the frame frequency of LED driver output waveform
Display data for LED
PWM data of PWM circuits of LED driver output
No.A2119-14/34
LC75805PE
(2) When CL is stopped at the high level
CE
CL
DI
1
1
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
1
1
0
0
0
0
1
D1 D2
D38 0
0
0
0
0
0
0
0
Display data
for LCD
38 bits
L1A L1B
0
0
0
0
0
0 OC FC0 FC1 FC2 FC3 DT0 DT1 SC BU 0
Control data
23 bits
L45A L45B L45C L46A L46B L46C L47A L47B L47C L48A L48B L48C PF0 PF1 PF2 PF3 0
0
1
DD
3 bits
0
0
0
0
0
0
0
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Control data
148 bits
CCB address
8 bits
1
1
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
LT1 LT2
LT47 LT48 0
Display data
for LED
48 bits
0...
Fixed data
9 bits
DD
3 bits
0 W10 W11 W12 W13 W14 W15 W16 W20 W21 W22 W23 W24 W25 W26 W30 W31 W32 W33 W34 W35 W36
Fixed data
12 bits
Control data
49 bits
W40 W41 W42 W43 W44 W45 W46 W50 W51 W52 W53 W54 W55 W56 W60 W61 W62 W63 W64 W65 W66 W70 W71 W72 W73 W74 W75 W76 1
1
0
DD
3 bits
(Note 1) The input of serial data is taken in at the rising edge of CL, and latched at the falling edge of CE. In addition,
this IC has the function that counts the number of CL clock to receive the correct serial data. That is to say,
because it isn’t latched at the falling edge of CE when the number of the count of CL in each serial data is
wrong, receiving wrong serial data can be prevented.
(Note 2) DD • • • Direction Data
• CCB address .........................
• D1 to D38 .............................
• OC ........................................
• FC0 to FC3 ...........................
• DT0, DT1 .............................
• SC .........................................
• BU ........................................
• L1A, L1B, L1C to L48A, ......
L48B, L48C
• PF0 to PF3 ............................
• LT1 to LT48 .........................
• W10 to W16, W20 to W26, ...
W30 to W36, W40 to W46,
W50 to W56, W60 to W66
W70 to W76
“87H”
Display data for LCD
Control data for switch of internal oscillator operating mode and external clock operating mode
Control data for setting of the frame frequency of common and segment output waveform
Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
Control data for turning on/off segments
Control data for switch of Normal mode and Power-saving mode
Control data for Ch settings of PWM circuits that adjust brightness of LED
Control data for setting of the frame frequency of LED driver output waveform
Display data for LED
PWM data of PWM circuits of LED driver output
No.A2119-15/34
LC75805PE
Control data Functions
(1) OC … Control data for switch of internal oscillator operating mode and external clock operating mode
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
OC
Fundamental clock operating mode
0
Internal oscillator operating mode
1
Input pin (OSCI) state
Connect to GND
Input the clock (fCK = 100 to 600 [kHz])
External clock operating mode
from the outside
(2) FC0 to FC3 … Control data for setting of the frame frequency of common and segment output waveform
These control data bits set the frame frequency of common and segment output waveform.
Frame frequency of common and segment output waveform fo [Hz]
FC0
FC1
FC2
FC3
Internal oscillator operating mode
External clock operating mode
(Control data OC =“0”,
(Control data OC =“1”,
fosc = 300 [kHz] typ)
fCK = 300 [kHz] typ)
0
0
0
0
fosc/4992
fCK/4992
1
0
0
0
fosc/4608
fCK/4608
0
1
0
0
fosc/4224
fCK/4224
1
1
0
0
fosc/3840
fCK/3840
0
0
1
0
fosc/3456
fCK/3456
1
0
1
0
fosc/3072
fCK/3072
0
1
1
0
fosc/2688
fCK/2688
1
1
1
0
fosc/2496
fCK/2496
0
0
0
1
fosc/2448
fCK/2448
1
0
0
1
fosc/2304
fCK/2304
0
1
0
1
fosc/2112
fCK/2112
1
1
0
1
fosc/1920
fCK/1920
0
0
1
1
fosc/1728
fCK/1728
1
0
1
1
fosc/1536
fCK/1536
0
1
1
1
fosc/1344
fCK/1344
1
1
1
1
fosc/1152
fCK/1152
(3) DT0, DT1 … Control data for setting of drive scheme (setting of 1/1 to 1/4 Duty Drive scheme) of LCD
These control bits select 1/4-Duty 1/3-Bias Drive, 1/3-Duty 1/3-Bias Drive, 1/2-Duty 1/2-Bias Drive,
or Static Drive (1/1-Duty Drive) of LCD.
DT0
DT1
Drive scheme for LCD
0
0
1
0
0
1
Each pin state
COM2/S38
COM3/S37
COM4/S36
1/4-Duty 1/3-Bias Drive
COM2
COM3
COM4
1/3-Duty 1/3-Bias Drive
COM2
COM3
S36
1
1/2-Duty 1/2-Bias Drive
COM2
S37
S36
1
Static Drive (1/1-Duty Drive)
S38
S37
S36
Note) COM2 to COM4: Common output / S38 to S36: Segment output
(4) SC … Control data for turning on/off segments
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
1
Off
Note that when the segments are turned off by setting SC to 1, the segments are turning off by outputting
segment off waveforms from the segment output pins.
No.A2119-16/34
LC75805PE
(5) BU … Control data for switch of Normal mode and Power-saving mode
This control data bit selects either Normal mode or Power-saving mode.
BU
0
Mode
Normal mode
Power-saving mode
The oscillation of internal oscillator circuit is stopped when internal oscillator operating mode (OC = [0]), and the receiving of external
1
clock isn’t admitted when external clock operating mode (OC = [1]). In addition, common and segment output pins are VSS level, and
LED driver output pins are High impedance.
(6) L1A, L1B, L1C to L48A, L48B, L48C … Control data for Ch settings of PWM circuits that adjust brightness of LED
These control data bits set the Ch of PWM circuit for LED driver output pins, LD1 to LD48.
LnA
LnB
LnC
Ch of PWM circuit for LED driver output LDn
0
0
0
1
0
0
PWM circuit (Ch1) is selected.
0
1
0
PWM circuit (Ch2) is selected.
1
1
0
PWM circuit (Ch3) is selected.
0
0
1
PWM circuit (Ch4) is selected.
1
0
1
PWM circuit (Ch5) is selected.
0
1
1
PWM circuit (Ch6) is selected.
1
1
1
PWM circuit (Ch7) is selected.
PWM circuit is not selected.
(The setting of turning on/off of the duty 100% by Display data LTn for LED is possible.)
Note) LnA, LnB, LnC (n = 1 to 48) data are control data that set the Ch of PWM circuit for LED driver output pins
LDn (n = 1 to 48).
For example, if (L1A, L1B, L1C) = (1, 0, 0), (L11A, L11B, L11C) = (1, 1, 0) and (L21A, L21B, L21C) = (0,
1, 1) is set, LED driver output pin LD1 select PWM circuit (Ch1) and LED driver output pin LD11 select
PWM circuit (Ch3) and LED driver output pin LD21 select PWM circuit (Ch6).
(7) PF0 to PF3 … Control data for setting of the frame frequency of LED driver output waveform
These control data bits set the frame frequency of LED driver output waveform of LED output pin setting
PWM circuit (Ch1 to Ch7).
Frame frequency of LED driver output waveform fp [Hz]
PF0
PF1
PF2
PF3
Internal oscillator operating mode
External clock operating mode
(Control data OC =“0”,
(Control data OC =“1”,
fosc = 300 [kHz] typ)
fCK = 300 [kHz] typ)
0
0
0
0
fosc/1664
fCK/1664
1
0
0
0
fosc/1536
fCK/1536
0
1
0
0
fosc/1408
fCK/1408
1
1
0
0
fosc/1280
fCK/1280
0
0
1
0
fosc/1152
fCK/1152
1
0
1
0
fosc/1024
fCK/1024
0
1
1
0
fosc/896
fCK/896
1
1
1
0
fosc/768
fCK/768
0
0
0
1
fosc/640
fCK/640
1
0
0
1
fosc/512
fCK/512
Note) If (PF0, PF1, PF2, PF3) = (X, 1, 0, 1), (X, X, 1, 1) are set, the frame frequency (fosc/1408, fCK/1408) of
setting (PF0, PF1, PF2, PF3) = (0, 1, 0, 0) is selected.
No.A2119-17/34
LC75805PE
(8) W10 to W16, W20 to W26, W30 to W36, W40 to W46, W50 to W56, W60 to W66, W70 to W76
… PWM data of PWM circuit for LED driver output
These control data bits set LED lighting time per 1 frame of LED driver output waveform of LED driver
output pin setting PWM circuit (Ch1 to Ch7).
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
Wn6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LED lighting time
per 1 frame
(1/128)  Tp
(2/128)  Tp
(3/128)  Tp
(4/128)  Tp
(5/128)  Tp
(6/128)  Tp
(7/128)  Tp
(8/128)  Tp
(9/128)  Tp
(10/128)  Tp
(11/128)  Tp
(12/128)  Tp
(13/128)  Tp
(14/128)  Tp
(15/128)  Tp
(16/128)  Tp
(17/128)  Tp
(18/128)  Tp
(19/128)  Tp
(20/128)  Tp
(21/128)  Tp
(22/128)  Tp
(23/128)  Tp
(24/128)  Tp
(25/128)  Tp
(26/128)  Tp
(27/128)  Tp
(28/128)  Tp
(29/128)  Tp
(30/128)  Tp
(31/128)  Tp
(32/128)  Tp
(33/128)  Tp
(34/128)  Tp
(35/128)  Tp
(36/128)  Tp
(37/128)  Tp
(38/128)  Tp
(39/128)  Tp
(40/128)  Tp
(41/128)  Tp
(42/128)  Tp
(43/128)  Tp
(44/128)  Tp
(45/128)  Tp
(46/128)  Tp
(47/128)  Tp
(48/128)  Tp
(49/128)  Tp
(50/128)  Tp
(51/128)  Tp
(52/128)  Tp
(53/128)  Tp
(54/128)  Tp
(55/128)  Tp
(56/128)  Tp
(57/128)  Tp
(58/128)  Tp
(59/128)  Tp
(60/128)  Tp
(61/128)  Tp
(62/128)  Tp
(63/128)  Tp
(64/128)  Tp
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
Wn6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LED lighting time
per 1 frame
(65/128)  Tp
(66/128)  Tp
(67/128)  Tp
(68/128)  Tp
(69/128)  Tp
(70/128)  Tp
(71/128)  Tp
(72/128)  Tp
(73/128)  Tp
(74/128)  Tp
(75/128)  Tp
(76/128)  Tp
(77/128)  Tp
(78/128)  Tp
(79/128)  Tp
(80/128)  Tp
(81/128)  Tp
(82/128)  Tp
(83/128)  Tp
(84/128)  Tp
(85/128)  Tp
(86/128)  Tp
(87/128)  Tp
(88/128)  Tp
(89/128)  Tp
(90/128)  Tp
(91/128)  Tp
(92/128)  Tp
(93/128)  Tp
(94/128)  Tp
(95/128)  Tp
(96/128)  Tp
(97/128)  Tp
(98/128)  Tp
(99/128)  Tp
(100/128)  Tp
(101/128)  Tp
(102/128)  Tp
(103/128)  Tp
(104/128)  Tp
(105/128)  Tp
(106/128)  Tp
(107/128)  Tp
(108/128)  Tp
(109/128)  Tp
(110/128)  Tp
(111/128)  Tp
(112/128)  Tp
(113/128)  Tp
(114/128)  Tp
(115/128)  Tp
(116/128)  Tp
(117/128)  Tp
(118/128)  Tp
(119/128)  Tp
(120/128)  Tp
(121/128)  Tp
(122/128)  Tp
(123/128)  Tp
(124/128)  Tp
(125/128)  Tp
(126/128)  Tp
(127/128)  Tp
(128/128)  Tp
Note) W10 to W16 : PWM data of PWM circuit (Ch1) / W20 to W26 : PWM data of PWM circuit (Ch2)
W30 to W36 : PWM data of PWM circuit (Ch3) / W40 to W46 : PWM data of PWM circuit (Ch4)
W50 to W56 : PWM data of PWM circuit (Ch5) / W60 to W66 : PWM data of PWM circuit (Ch6)
W70 to W76 : PWM data of PWM circuit (Ch7)
Tp=
1
fp
No.A2119-18/34
LC75805PE
Descriptions of Display data for LCD
(1) Correspondence of output pins to display data for LCD at 1/4 Duty Drive
Output Pin
COM1
COM2
COM3
COM4
Output Pin
COM1
COM2
COM3
COM4
S1
D1
D2
D3
D4
S19
D73
D74
D75
D76
S2
D5
D6
D7
D8
S20
D77
D78
D79
D80
S3
D9
D10
D11
D12
S21
D81
D82
D83
D84
S4
D13
D14
D15
D16
S22
D85
D86
D87
D88
S5
D17
D18
D19
D20
S23
D89
D90
D91
D92
S6
D21
D22
D23
D24
S24
D93
D94
D95
D96
S7
D25
D26
D27
D28
S25
D97
D98
D99
D100
S8
D29
D30
D31
D32
S26
D101
D102
D103
D104
S9
D33
D34
D35
D36
S27
D105
D106
D107
D108
S10
D37
D38
D39
D40
S28
D109
D110
D111
D112
S11
D41
D42
D43
D44
S29
D113
D114
D115
D116
S12
D45
D46
D47
D48
S30
D117
D118
D119
D120
S13
D49
D50
D51
D52
S31
D121
D122
D123
D124
S14
D53
D54
D55
D56
S32
D125
D126
D127
D128
S15
D57
D58
D59
D60
S33
D129
D130
D131
D132
S16
D61
D62
D63
D64
S34
D133
D134
D135
D136
S17
D65
D66
D67
D68
S35
D137
D138
D139
D140
S18
D69
D70
D71
D72
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D81
D82
D83
D84
0
0
0
0
The LCD segments corresponding to COM1, COM2, COM3 and COM4 are off.
0
0
0
1
The LCD segment corresponding to COM4 is on.
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segments corresponding to COM3 and COM4 are on.
0
1
0
0
The LCD segment corresponding to COM2 is on.
0
1
0
1
The LCD segments corresponding to COM2 and COM4 are on.
0
1
1
0
The LCD segments corresponding to COM2 and COM3 are on.
0
1
1
1
The LCD segments corresponding to COM2, COM3 and COM4 are on.
1
0
0
0
The LCD segment corresponding to COM1 is on.
1
0
0
1
The LCD segments corresponding to COM1 and COM4 are on.
1
0
1
0
The LCD segments corresponding to COM1 and COM3 are on.
1
0
1
1
The LCD segments corresponding to COM1, COM3 and COM4 are on.
1
1
0
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
0
1
The LCD segments corresponding to COM1, COM2 and COM4 are on.
1
1
1
0
The LCD segments corresponding to COM1, COM2 and COM3 are on.
1
1
1
1
The LCD segments corresponding to COM1, COM2, COM3 and COM4 are on.
No.A2119-19/34
LC75805PE
(2) Correspondence of output pins to display data for LCD at 1/3 Duty Drive
Output Pin
COM1
COM2
COM3
Output Pin
COM1
COM2
COM3
S1
D1
D2
D3
S20
D58
D59
D60
S2
D4
D5
D6
S21
D61
D62
D63
S3
D7
D8
D9
S22
D64
D65
D66
S4
D10
D11
D12
S23
D67
D68
D69
S5
D13
D14
D15
S24
D70
D71
D72
S6
D16
D17
D18
S25
D73
D74
D75
S7
D19
D20
D21
S26
D76
D77
D78
S8
D22
D23
D24
S27
D79
D80
D81
S9
D25
D26
D27
S28
D82
D83
D84
S10
D28
D29
D30
S29
D85
D86
D87
S11
D31
D32
D33
S30
D88
D89
D90
S12
D34
D35
D36
S31
D91
D92
D93
S13
D37
D38
D39
S32
D94
D95
D96
S14
D40
D41
D42
S33
D97
D98
D99
S15
D43
D44
D45
S34
D100
D101
D102
S16
D46
D47
D48
S35
D103
D104
D105
S17
D49
D50
D51
S36/COM4
D106
D107
D108
S18
D52
D53
D54
S19
D55
D56
D57
Note) S36/COM4 pin is selected segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D61
D62
D63
0
0
0
The LCD segments corresponding to COM1, COM2 and COM3 are off.
0
0
1
The LCD segment corresponding to COM3 is on.
0
1
0
The LCD segment corresponding to COM2 is on.
0
1
1
The LCD segments corresponding to COM2 and COM3 are on.
1
0
0
The LCD segment corresponding to COM1 is on.
1
0
1
The LCD segments corresponding to COM1 and COM3 are on.
1
1
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
1
The LCD segments corresponding to COM1, COM2 and COM3 are on.
No.A2119-20/34
LC75805PE
(3) Correspondence of output pins to display data for LCD at 1/2 Duty Drive
Output Pin
COM1
COM2
Output Pin
COM1
COM2
S1
D1
D2
S20
D39
D40
S2
D3
D4
S21
D41
D42
S3
D5
D6
S22
D43
D44
S4
D7
D8
S23
D45
D46
S5
D9
D10
S24
D47
D48
S6
D11
D12
S25
D49
D50
S7
D13
D14
S26
D51
D52
S8
D15
D16
S27
D53
D54
S9
D17
D18
S28
D55
D56
S10
D19
D20
S29
D57
D58
S11
D21
D22
S30
D59
D60
S12
D23
D24
S31
D61
D62
S13
D25
D26
S32
D63
D64
S14
D27
D28
S33
D65
D66
S15
D29
D30
S34
D67
D68
S16
D31
D32
S35
D69
D70
S17
D33
D34
S36/COM4
D71
D72
S18
D35
D36
S37/COM3
D73
D74
S19
D37
D38
Note) S36/COM4 and S37/COM3 pins are selected segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D41
D42
0
0
The LCD segments corresponding to COM1 and COM2 are off.
0
1
The LCD segment corresponding to COM2 is on.
1
0
The LCD segment corresponding to COM1 is on.
1
1
The LCD segment corresponding to COM1 and COM2 are on.
No.A2119-21/34
LC75805PE
(4) Correspondence of output pins to display data for LCD at Static Drive (1/1 Duty Drive)
Output Pin
COM1
Output Pin
COM1
S1
D1
S21
D21
S2
D2
S22
D22
S3
D3
S23
D23
S4
D4
S24
D24
S5
D5
S25
D25
S6
D6
S26
D26
S7
D7
S27
D27
S8
D8
S28
D28
S9
D9
S29
D29
S10
D10
S30
D30
S11
D11
S31
D31
S12
D12
S32
D32
S13
D13
S33
D33
S14
D14
S34
D34
S15
D15
S35
D35
S16
D16
S36/COM4
D36
S17
D17
S37/COM3
D37
S18
D18
S38/COM2
D38
S19
D19
S20
D20
Note) S36/COM4, S37/COM3 and S38/COM2 pins are selected segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
D21
Output pin (S21) state
0
The LCD segment to COM1 is off.
1
The LCD segment to COM1 is on.
No.A2119-22/34
LC75805PE
Correspondence of output pins to display data for LED
Output Pin
Display data
Output Pin
Display data
LD1
LT1
LD25
LT25
LD2
LT2
LD26
LT26
LD3
LT3
LD27
LT27
LD4
LT4
LD28
LT28
LD5
LT5
LD29
LT29
LD6
LT6
LD30
LT30
LD7
LT7
LD31
LT31
LD8
LT8
LD32
LT32
LD9
LT9
LD33
LT33
LD10
LT10
LD34
LT34
LD11
LT11
LD35
LT35
LD12
LT12
LD36
LT36
LD13
LT13
LD37
LT37
LD14
LT14
LD38
LT38
LD15
LT15
LD39
LT39
LD16
LT16
LD40
LT40
LD17
LT17
LD41
LT41
LD18
LT18
LD42
LT42
LD19
LT19
LD43
LT43
LD20
LT20
LD44
LT44
LD21
LT21
LD45
LT45
LD22
LT22
LD46
LT46
LD23
LT23
LD47
LT47
LD24
LT24
LD48
LT48
For example, the table below lists the output states for the LD21 output pin.
Display
data
Output pin (LD21) state
LT21
0
LED is off. (High impedance output)
LED is on.
Note) If (L21A, L21B, L21C) = (0, 0, 0) is set, the LED by 100% duty is on.
If (L21A, L21B, L21C) = (1, 0, 0) is set, the LED depending on the contents of PWM data,
W10 to W16, of PWM circuit (Ch1) is on.
If (L21A, L21B, L21C) = (0, 1, 0) is set, the LED depending on the contents of PWM data,
W20 to W26, of PWM circuit (Ch2) is on.
If (L21A, L21B, L21C) = (1, 1, 0) is set, the LED depending on the contents of PWM data,
1
W30 to W36, of PWM circuit (Ch3) is on.
If (L21A, L21B, L21C) = (0, 0, 1) is set, the LED depending on the contents of PWM data,
W40 to W46, of PWM circuit (Ch4) is on.
If (L21A, L21B, L21C) = (1, 0, 1) is set, the LED depending on the contents of PWM data,
W50 to W56, of PWM circuit (Ch5) is on.
If (L21A, L21B, L21C) = (0, 1, 1) is set, the LED depending on the contents of PWM data,
W60 to W66, of PWM circuit (Ch6) is on.
If (L21A, L21B, L21C) = (1, 1, 1) is set, the LED depending on the contents of PWM data,
W70 to W76, of PWM circuit (Ch7) is on.
No.A2119-23/34
LC75805PE
LCD drive waveform (1/4-Duty 1/3-Bias drive, Frame inversion drive)
fo [Hz]
COM1
COM2
COM3
COM4
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3 and
COM4 are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM1, COM2 and COM3 are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3 and
COM4 are on.
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
No.A2119-24/34
LC75805PE
LCD drive waveform (1/3-Duty 1/3-Bias drive, Frame inversion drive)
fo [Hz]
COM1
VDD
2/3VDD
1/3VDD
0V
COM2
VDD
2/3VDD
1/3VDD
0V
COM3
VDD
2/3VDD
1/3VDD
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2 and COM3
are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VDD
2/3VDD
1/3VDD
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VDD
2/3VDD
1/3VDD
0V
VDD
LCD driver output when only LCD segments
corresponding to COM3 are on.
2/3VDD
1/3VDD
0V
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VDD
2/3VDD
1/3VDD
0V
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VDD
2/3VDD
1/3VDD
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2 and COM3
are on.
VDD
2/3VDD
1/3VDD
0V
No.A2119-25/34
LC75805PE
LCD drive waveform (1/2-Duty 1/2-Bias drive, Frame inversion drive)
fo [Hz]
VDD
1/2VDD
VSS
VDD
1/2VDD
VSS
COM1
COM2
VDD
LCD driver output when all LCD segments
corresponding to COM1 and COM2 are off.
VSS
VDD
LCD driver output when only LCD segments
corresponding to COM1 are on.
VSS
VDD
LCD driver output when only LCD segments
corresponding to COM2 are on.
VSS
VDD
LCD driver output when all LCD segments
corresponding to COM1 and COM2 are on.
VSS
LCD drive waveform (Static Drive)
fo [Hz]
VDD
COM1
VSS
VDD
LCD driver output when LCD segments
are off.
VSS
VDD
LCD driver output when LCD segments
are on.
VSS
Frame frequency of common and segment output waveform fo [Hz]
FC0
FC1
FC2
FC3
Internal oscillator operating mode
External clock operating mode
(Control data OC = “0”,
(Control data OC = “1”,
fosc = 300 [kHz] typ)
fCK = 300 [kHz] typ)
0
0
0
0
fosc/4992
fCK/4992
1
0
0
0
fosc/4608
fCK/4608
0
1
0
0
fosc/4224
fCK/4224
1
1
0
0
fosc/3840
fCK/3840
0
0
1
0
fosc/3456
fCK/3456
1
0
1
0
fosc/3072
fCK/3072
0
1
1
0
fosc/2688
fCK/2688
1
1
1
0
fosc/2496
fCK/2496
0
0
0
1
fosc/2448
fCK/2448
1
0
0
1
fosc/2304
fCK/2304
0
1
0
1
fosc/2112
fCK/2112
1
1
0
1
fosc/1920
fCK/1920
0
0
1
1
fosc/1728
fCK/1728
1
0
1
1
fosc/1536
fCK/1536
0
1
1
1
fosc/1344
fCK/1344
1
1
1
1
fosc/1152
fCK/1152
No.A2119-26/34
LC75805PE
LED drive waveform
VOUP
< Lighting period >
LD1 to LD6 (PWM Ch1)
(112/128)  Tp
VSS
(112/128)  Tp
VOUP
< Lighting period >
LD7 to LD12 (PWM Ch2)
(96/128)  Tp
VSS
(96/128)  Tp
VOUP
< Lighting period >
LD13 to LD18 (PWM Ch3)
(80/128)  Tp
VSS
(80/128)  Tp
VOUP
< Lighting period >
LD19 to LD24 (PWM Ch4)
(16/128)  Tp
VSS
(16/128)  Tp
VOUP
< Lighting period >
LD25 to LD30 (PWM Ch5)
(32/128)  Tp
VSS
(32/128)  Tp
VOUP
< Lighting period >
LD31 to LD36 (PWM Ch6)
VSS
(48/128)  Tp
(48/128)  Tp
VOUP
< Lighting period >
LD37 to LD42 (PWM Ch7)
(64/128)  Tp
VSS
(64/128)  Tp
VOUP
< Continuous lights out >
LD43 to LD45
VSS
LD46 to LD48
VOUP
< Continuous lighting >
VSS
Tp
Tp=
Tp
1
fp
LT1 to LT6
L1A to L6A
L1B to L6B
L1C to L6C
W10
W11
W12
W13
W14
W15
W16
PWM (Ch)
1
1
0
0
1
1
1
1
0
1
1
PWM Ch1, (112/128) x Tp
LT7 to LT12
L7A to L12A
L7B to L12B
L7C to L12C
W20
W21
W22
W23
W24
W25
W26
PWM (Ch)
1
0
1
0
1
1
1
1
1
0
1
PWM Ch2, (96/128) x Tp
LT13 to LT18
L13A to L18A
L13B to L18B
L13C to L18C
W30
W31
W32
W33
W34
W35
W36
PWM (Ch)
1
1
1
0
1
1
1
1
0
0
1
PWM Ch3, (80/128) x Tp
LT19 to LT24
L19A to L24A
L19B to L24B
L19C to L24C
W40
W41
W42
W43
W44
W45
W46
PWM (Ch)
1
0
0
1
1
1
1
1
0
0
0
PWM Ch4, (16/128) x Tp
LT25 to LT30
L25A to L30A
L25B to L30B
L25C to L30C
W50
W51
W52
W53
W54
W55
W56
PWM (Ch)
1
1
0
1
1
1
1
1
1
0
0
PWM Ch5, (32/128) x Tp
LT31 to LT36
L31A to L36A
L31B to L36B
L31C to L36C
W60
W61
W62
W63
W64
W65
W66
PWM (Ch)
1
0
1
1
1
1
1
1
0
1
0
PWM Ch6, (48/128) x Tp
LT37 to LT42
L37A to L42A
L37B to L42B
L37C to L42C
W70
W71
W72
W73
W74
W75
W76
PWM (Ch)
1
1
1
1
1
1
1
1
1
1
0
PWM Ch7, (64/128) x Tp
LT43 to LT45
L43A to L45A
L43B to L45B
L43C to L45C
PWM (Ch)
0
0
0
0
No select PWM, Turning off
LT46 to LT48
L46A to L48A
L46B to L48B
L46C to L48C
PWM (Ch)
1
0
0
0
No select PWM, Turning on
No.A2119-27/34
LC75805PE
Frame frequency of LED driver output waveform fp [Hz]
PF0
PF1
PF2
PF3
Internal oscillator operating mode
External clock operating mode
(Control data OC =“0”,
(Control data OC =“1”,
fosc = 300 [kHz] typ)
fCK = 300 [kHz] typ)
0
0
0
0
fosc/1664
fCK/1664
1
0
0
0
fosc/1536
fCK/1536
0
1
0
0
fosc/1408
fCK/1408
1
1
0
0
fosc/1280
fCK/1280
0
0
1
0
fosc/1152
fCK/1152
1
0
1
0
fosc/1024
fCK/1024
0
1
1
0
fosc/896
fCK/896
1
1
1
0
fosc/768
fCK/768
0
0
0
1
fosc/640
fCK/640
1
0
0
1
fosc/512
fCK/512
Note) If (PF0, PF1, PF2, PF3) = (X, 1, 0, 1) or (X, X, 1, 1) are set, frame frequency (fosc/1408, fCK/1408) of setting
(PF0, PF1, PF2, PF3) = (0, 1, 0, 0) is selected.
No.A2119-28/34
LC75805PE
Display Control and the INH Pin
Since the LSI internal data (1/4 Duty Drive: LCD display data D1 to D140 + LED display data LT1 to LT48 + control
data, 1/3 Duty Drive: LCD display data D1 to D108 + LED display data LT1 to LT48 + control data, 1/2 Duty Drive:
LCD display data D1 to D74 + LED display data LT1 to LT48 + control data, Static Drive: LCD display data D1 to
D38 + LED display data LT1 to LT48 + control data) is undefined when power is first applied, applications should set
the INH pin low at the same time as power is applied to turn off the display of LCD and LED (LD1 to LD48    High
impedance, COM1 and COM2/S38 to COM4/S36 and S35 to S1    VSS level). The serial data is transferred from the
controller during this period, and then input INH =“H” after the serial data is transferred. This procedure prevents
meaningless display at power on.
(See [Fig 4], [Fig 5], [Fig 6], [Fig 7])
(1) 1/4 Duty Drive
t1
t2
VDD
INH
VIL1
tc
CE
VIL1
Display data for LCD,
Display data for LED and Control data transfer
Internal data
D1 to D140, OC,
FC0 to FC3, DT0, DT1,
SC, BU
Undefined
Defined
Undefined
Internal data
L1A, L1B, L1C to L48A,
L48B, L48C, PF0 to PF3
Undefined
Defined
Undefined
Internal data
LT1 to LT48, W10 to W16,
W20 to W26, W30 to W36,
W40 to W46, W50 to W56,
W60 to W66, W70 to W76
Undefined
Defined
Undefined
Notes: t110s
t20
tc…10s min
[Fig 4]
(2) 1/3 Duty Drive
t1
t2
VDD
INH
VIL1
tc
CE
VIL1
Display data for LCD,
Display data for LED and Control data transfer
Internal data
D1 to D108, OC,
FC0 to FC3, DT0, DT1,
SC, BU
Undefined
Defined
Undefined
Internal data
L1A, L1B, L1C to L48A,
L48B, L48C, PF0 to PF3
Undefined
Defined
Undefined
Internal data
LT1 to LT48, W10 to W16,
W20 to W26, W30 to W36,
W40 to W46, W50 to W56,
W60 to W66, W70 to W76
Undefined
Defined
Undefined
[Fig 5]
Notes: t110s
t20
tc…10s min
No.A2119-29/34
LC75805PE
(3) 1/2 Duty Drive
t1
t2
VDD
INH
VIL1
tc
CE
VIL1
Display data for LCD,
Display data for LED and Control data transfer
Internal data
D1 to D74, OC,
FC0 to FC3, DT0, DT1,
SC, BU
Undefined
Defined
Undefined
Internal data
L1A, L1B, L1C to L48A,
L48B, L48C, PF0 to PF3
Undefined
Defined
Undefined
Internal data
LT1 to LT48, W10 to W16,
W20 to W26, W30 to W36,
W40 to W46, W50 to W56,
W60 to W66, W70 to W76
Undefined
Defined
Undefined
Notes: t110s
t20
tc…10s min
[Fig 6]
(4) Static Drive (1/1 Duty Drive)
t1
t2
VDD
INH
VIL1
tc
CE
VIL1
Display data for LCD,
Display data for LED and Control data transfer
Internal data
D1 to D38, OC,
FC0 to FC3, DT0, DT1,
SC, BU
Undefined
Defined
Undefined
Internal data
L1A, L1B, L1C to L48A,
L48B, L48C, PF0 to PF3
Undefined
Defined
Undefined
Internal data
LT1 to LT48, W10 to W16,
W20 to W26, W30 to W36,
W40 to W46, W50 to W56,
W60 to W66, W70 to W76
Undefined
Defined
Undefined
[Fig 7]
Notes: t110s
t20
tc…10s min
No.A2119-30/34
LC75805PE
OSCI pin Peripheral Circuit
(1) Internal oscillator operating mode (Control data OC =”0”)
Connect OSCI pin to GND if internal oscillator operating mode is selected.
OSCI
(2) External clock operating mode (Control data OC =”1”)
Input the external clock (fCK = 100 to 600 [kHz]) to OSCI pin if external clock operating mode is selected.
External clock output pin
OSCI
Rg
External oscillator
No.A2119-31/34
LC75805PE
Application Circuit Example 1
1/4-Duty, 1/3-Bias
+5.0V
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
External clock input
OSCI *2
From the controller
*1
INH
CE
CL
DI
COM1
S38/COM2
S37/COM3
S36/COM4
S35
S34
S5
S4
S3
S2
S1
LCD panel
(Display of up to
140 segments)
*3
LED Power supply
(12V)
LD48
LD47
LD3
LD2
LD1
*1 Pins (CE, CL, DI, INH) connected to the controller are supported 5V.
*2 External clock input pin OSCI is supported 5V. Connect to GND at internal oscillator operating mode, and input the
external clock (fCK = 100 to 600 [kHz]) to OSCI pin at external clock operating mode.
(See “OSCI pin peripheral circuit”)
*3 Load capacity of the LCD panel is recommended 9000 [pF] or less.
Application Circuit Example 2
1/3-Duty, 1/3-Bias
+5.0V
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
External clock input
OSCI *2
From the controller
*1
INH
CE
CL
DI
COM1
S38/COM2
S37/COM3
COM4/S36
S35
S34
S5
S4
S3
S2
S1
LCD panel
(Display of up to
108 segments)
*3
LED Power supply
(12V)
LD48
LD47
LD3
LD2
LD1
*1 Pins (CE, CL, DI, INH) connected to the controller are supported 5V.
*2 External clock input pin OSCI is supported 5V. Connect to GND at internal oscillator operating mode, and input the
external clock (fCK = 100 to 600 [kHz]) to OSCI pin at external clock operating mode.
(See “OSCI pin peripheral circuit”)
*3 Load capacity of the LCD panel is recommended 9000 [pF] or less.
No.A2119-32/34
LC75805PE
Application Circuit Example 3
1/2-Duty, 1/2-Bias
+5.0V
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
External clock input
OSCI *2
From the controller
*1
INH
CE
CL
DI
COM1
S38/COM2
COM3/S37
COM4/S36
S35
S34
S5
S4
S3
S2
S1
LCD panel
(Display of up to
74 segments)
*3
LED Power supply
(12V)
LD48
LD47
LD3
LD2
LD1
*1 Pins (CE, CL, DI, INH) connected to the controller are supported 5V.
*2 External clock input pin OSCI is supported 5V. Connect to GND at internal oscillator operating mode, and input the
external clock (fCK = 100 to 600 [kHz]) to OSCI pin at external clock operating mode.
(See “OSCI pin peripheral circuit”)
*3 Load capacity of the LCD panel is recommended 9000 [pF] or less.
Application Circuit Example 4
Static (1/1-Duty)
+5.0V
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
External clock input
OSCI *2
From the controller
*1
INH
CE
CL
DI
COM1
COM2/S38
COM3/S37
COM4/S36
S35
S34
S5
S4
S3
S2
S1
LCD panel
(Display of up to
38 segments)
*3
LED Power supply
(12V)
LD48
LD47
LD3
LD2
LD1
*1 Pins (CE, CL, DI, INH) connected to the controller are supported 5V.
*2 External clock input pin OSCI is supported 5V. Connect to GND at internal oscillator operating mode, and input the
external clock (fCK = 100 to 600 [kHz]) to OSCI pin at external clock operating mode.
(See “OSCI pin peripheral circuit”)
*3 Load capacity of the LCD panel is recommended 9000 [pF] or less.
No.A2119-33/34
LC75805PE
ORDERING INFORMATION
Device
LC75805PEH-3H
Package
QIP100E(14X20)
(Pb-Free / Halogen Free)
LC75805PES-3H
QIP100E(14X20)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
250 / Tray Foam
250 / Tray Foam
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PS No.A2119-34/34
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