ENA1976 D

Ordering number : ENA1976
LC75809PT
CMOS IC
1/4 and 1/3-Duty General-Purpose
LCD Display Driver
http://onsemi.com
Overview
The LC75809PT is the 1/4 duty and 1/3 duty general-purpose microprocessor-controlled LCD driver that can be used
in applications such as frequency display in products with electronic tuning. In addition to being able to drive up to
352 segments directly, the LC75809PT can also control up to 12 general-purpose output ports. Because it has the
PWM output of a maximum of 6ch, the brightness control of the LED backlight of RGB×2 can be done.
Incorporation of an oscillation circuit helps to reduce the number of external resistors and capacitors required.
Features
• Support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under serial data control.
When 1/4-duty : Capable of driving up to 352 segments
When 1/3-duty : Capable of driving up to 267 segments
• Serial data input supports CCB format communication with the system controller. (Support 3.3V and 5V operation)
• Serial data control of the power-saving mode based backup function and the all segments forced off function.
• Serial data control of switching between the segment output port and general-purpose output port function.
(Support for up to 12 general-purpose output ports)
• Support for the PWM output function of a maximum of 6ch. (It can output from the general-purpose output port).
• Support for clock output function of 1ch. (It can output from the general-purpose output port).
• Serial data control of the frame frequency of the common and segment output waveforms.
• Serial data control of switching between the internal oscillator operating mode and external clock operating mode.
• High generality, since display data is displayed directly without the intervention of a decoder circuit.
• Built-in display contrast adjustment circuit.
• The INH pin allows the display to be forced to the off state.
• Incorporation of an oscillator circuit. (Incorporation of resistor and capacitor for an oscillation)
•
•
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
July, 2013
11812HKPC 20110826-S00008 No.A1976-1/43
LC75809PT
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Symbol
VDD max
Conditions
Ratings
VDD
Unit
-0.3 to +6.8
V
VIN1
CE, CL, DI, INH
VIN2
OSCI, VDD1, VDD2
-0.3 to VDD+0.3
VOUT
S1 to S89, COM1 to COM4, P1 to P12
-0.3 to VDD+0.3
V
IOUT1
S1 to S88
300
μA
IOUT2
COM1 to COM4, S89
3
IOUT3
P1 to P12
5
Pd max
Ta=85°C
-0.3 to +6.8
200
V
mA
mW
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-55 to +125
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Supply voltage
VDD
VDD
Input voltage
VDD1
VDD1
2/3VDD0
VDD0
*1
VDD2
VDD2
1/3VDD0
VDD0
Input high level voltage
VIH1
CE, CL, DI, INH
0.4VDD
6.3
VIH2
OSCI: External clock operating mode
0.4VDD
VDD
VIL1
CE, CL, DI, INH
0
0.2VDD
VIL2
OSCI: External clock operating mode
0
0.2VDD
fCK
OSCI: External clock operating mode
Input low level voltage
External clock
operating frequency
External clock duty cycle
4.5
[Figure4]
DCK
OSCI: External clock operating mode
[Figure4]
6.3
V
V
V
V
10
300
600
kHz
30
50
70
%
Data setup time
tds
CL, DI
[Figure2], [Figure3]
160
ns
Data hold time
tdh
CL, DI
[Figure2], [Figure3]
160
ns
CE wait time
tcp
CE, CL
[Figure2], [Figure3]
160
ns
CE setup time
tcs
CE, CL
[Figure2], [Figure3]
160
ns
CE hold time
tch
CE, CL
[Figure2], [Figure3]
160
ns
High level clock pulse width
tφH
CL
[Figure2], [Figure3]
160
ns
Low level clock pulse width
tφL
CL
[Figure2], [Figure3]
160
tr
CE, CL, DI
[Figure2], [Figure3]
160
ns
Fall time
tf
CE, CL, DI
[Figure2], [Figure3]
160
ns
INH switching time
tc
INH, CE
[Figure5], [Figure6]
Rise time
[Figure7], [Figure8]
10
ns
μs
Note : *1. VDD0=0.70VDD to VDD
No.A1976-2/43
LC75809PT
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin
Ratings
Conditions
min
typ
Unit
max
Hysteresis
VH
CE, CL, DI, INH
Input high level current
IIH1
CE, CL, DI, INH
VI=6.3V
5.0
IIH2
OSCI
VI=VDD: External
clock operating mode
5.0
IIL1
CE, CL, DI, INH
VI=0V
-5.0
IIL2
OSCI
VI=0V: External
clock operating mode
-5.0
S1 to S89
IO=-20μA
VDD0-0.9
VDD0-0.9
Input low level current
Output high level
voltage *1
VOH1
0.03VDD
V
μA
VOH2
COM1 to COM4
IO=-100μA
VOH3
P1 to P12
IO=-1mA
Output low level
VOL1
S1 to S89
IO=20μA
0.9
voltage
VOL2
COM1 to COM4
IO=100μA
0.9
VOL3
P1 to P12
IO=1mA
0.9
VMID1
S1 to S89
1/3 bias IO=±20μA
Output middle level
2/3VDD0
Current drain
+0.9
1/3VDD0
S1 to S89
1/3 bias IO=±20μA
1/3VDD0
-0.9
+0.9
VMID3
COM1 to COM4
1/3 bias IO=±100μA
2/3VDD0
2/3VDD0
-0.9
+0.9
VMID4
COM1 to COM4
1/3 bias IO=±100μA
1/3VDD0
1/3VDD0
-0.9
+0.9
Internal
Internal oscillator
oscillator circuit
operating mode
IDD1
VDD
Power-saving mode
IDD2
VDD
VDD=6.3V
Output open
fosc
240
V
2/3VDD0
-0.9
VMID2
*2
Oscillator frequency
V
VDD-0.9
voltage
*1
μA
300
360
V
kHz
100
1000
Internal oscillator
2000
operating mode
IDD3
VDD
VDD=6.3V
Output open
μA
External clock
1000
operating mode
2000
fCK=300kHz
VIH2=0.5VDD
VIL2=0.1VDD
Note: *1. VDD0=0.70VDD to VDD
Note: *2. Excluding the bias voltage generation divider resistors built in the VDD1 and VDD2. (See Figure 1.)
VDD
CONTRAST
ADJUSTER
VDD0
VDD1
To the common and segment drivers
VDD2
VSS
Except these resistors.
[Figure 1]
No.A1976-3/43
LC75809PT
≈
1. When CL is stopped at the low level
VIH1
VIH1
50%
VIL1
CL
tf
≈ ≈
tr
VIH1
DI
VIL1
tds
tcp
≈ ≈ ≈
tφH
tφL
VIL1
≈ ≈
CE
tcs
tch
tdh
[Figure 2]
≈
2. When CL is stopped at the high level
VIH1
VIL1
≈
CE
≈
tφH
VIH1
50%
VIL1
tf
≈ ≈ ≈
CL
tr
tcp
tcs
VIH1
DI
VIL1
tds
≈ ≈
tφL
tch
tdh
[Figure 3]
3. OSCI pin clock timing in external clock operating mode
tCKH
OSCI
VIH2
50%
VIL2
tCKL
fCK =
1
[kHz]
tCKH + tCKL
tCKH
× 100[%]
DCK=
tCKH + tCKL
[Figure 4]
No.A1976-4/43
LC75809PT
Package Dimensions
unit : mm (typ)
3274
75
0.5
16.0
14.0
51
50
100
26
14.0
16.0
76
1
0.5
0.2
25
0.125
1.2max
0.1
(1.0)
(1.0)
SANYO : TQFP100(14X14)
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
Pin Assignment
75
51
76
50
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87/COM4
COM3
COM2
COM1
S88
VDD
VDD1
VDD2
VSS
S89/OSCI
INH
CE
CL
DI
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
LC75809PT
(TQFP100)
100
26
25
P1/S1
P2/S2
P3/S3
P4/S4
P5/S5
P6/S6
P7/S7
P8/S8
P9/S9
P10/S10
P11/S11
P12/S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
1
Top view
No.A1976-5/43
LC75809PT
COMMON
DRIVER
S1/P1
S2/P2
S12/P12
S13
S86
S88
COM3
COM4/S87
COM2
COM1
Block Diagram
SEGMENT DRIVER & LATCH
INH
CLOCK
GENERATOR
S89/OSCI
CONTROL
REGISTER
VDD
CONTRAST
ADJUSTER
SHIFT REGISTER
VDD0
VDD1
CCB INTERFACE
VDD2
CE
CL
DI
VSS
No.A1976-6/43
LC75809PT
Pin Functions
Handling
Pin
Pin No.
Function
Active
I/O
when
unused
S1/P1 to
1 to 12
Segment outputs for displaying the display data transferred by serial data
input. The S1/P1 to S12/P12 pins can be used as general-purpose output
S12/P12
S13 to S86
13 to 86
S88
91
COM1 to COM3
90 to 88
COM4/S87
87
S89/OSCI
96
CE
98
ports under serial data control.
-
O
OPEN
-
O
OPEN
-
I/O
OPEN
H
I
Common driver outputs
The frame frequency is fo[Hz].
The COM4/S87 pin can be used as a segment output in 1/3 duty.
Segment output. This pin can also be used as the external clock input pin
when the external clock operating mode is selected by control data.
Serial data transfer inputs. Must be connected to the controller.
CE : Chip enable
CL
99
CL : Synchronization clock
I
GND
DI : Transfer data
DI
100
-
I
L
I
GND
-
I
OPEN
OPEN
Display off control input
•INH=low(VSS)….Display forced off S1/P1 to S12/P12=low (VSS)
(These pins are forcibly set to the general-purpose output
port function and held at the VSS level.)
S13 to S86, S88=low(VSS)
COM1 to COM3=low(VSS)
COM4/S87=low(VSS)
S89/OSCI=low(VSS)
(This pin is forcibly set to the segment output port function
INH
97
and held at the VSS level.)
Stops the internal oscillator. Inhibits external clock input.
Display contrast adjustment circuit stopped.
•INH=high(VDD)…Display on
Enables the internal oscillator circuit.
(Internal oscillator operating mode)
Enables external clock input.
(External clock operating mode)
Display contrast adjustment circuit operation is enabled.
However, serial data transfer is possible when the display is forced off.
VDD1
93
Used to apply the LCD drive 2/3 bias voltage externally.
VDD2
94
Used to apply the LCD drive 1/3 bias voltage externally.
-
I
VDD
92
Power supply pin. A power voltage of 4.5 to 6.3V must be applied to this pin.
-
-
-
VSS
95
Ground pin. Must be connected to ground.
-
-
-
No.A1976-7/43
LC75809PT
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
• When the display data is transferred
CL
0
0
0
0
0
0
1
0
D1
D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
88 bits
DD
3 bits
0
0
0
0
0
0
1
0
D89
D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
88 bits
Fixed data
5 bits
DD
3 bits
∼ ∼ ∼
∼ ∼
∼
CCB address
8 bits
∼ ∼ ∼
∼ ∼ ∼
∼
Fixed data
5 bits
∼
CCB address
8 bits
0
0
0
0
0
0
1
0 D177
D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Fixed data
9 bits
DD
3 bits
∼ ∼ ∼
∼
Display data
84 bits
∼ ∼
DI
∼ ∼ ∼
∼
CE
0
0
0
0
0
0
1
0 D261
D332 D333 D334 D335 D336 D337 D338 D339 D340 D341 D342 D343 D344 D345 D346 D347 D348 D349 D350 D351 D352 0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
92 bits
DD
Fixed 3 bits
data
1 bits
No.A1976-8/43
LC75809PT
• When the control data is transferred
CE
CL
DI
0
0
0
0
0
0
1
0 P1A P1B P1C P1D P2A P2B P2C P3A P3B P3C P4A P4B P4C P5A P5B P5C P6A P6B P6C P7A P7B P7C P8A P8B P8C P9A P9B P9C
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
P10A P10B P10C P11A P11B P11C P12A P12B P12C PF0 PF1 PF2 PF3 FC0 FC1 FC2 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN EXF SC BU 0
0
0
0
1
0
0
∼ ∼ ∼
∼
Control data
61 bits
∼ ∼ ∼
∼
DD
3 bits
0
0
0
0
0
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
45 bits
W40 W41 W42 W43 W44 W45 W50 W51 W52 W53 W54 W55 W60 W61 W62 W63 W64 W65 0
0
0
0
0
0
0
0
0
1
0
1
DD
3 bits
Note: DD is the direction data.
No.A1976-9/43
LC75809PT
(2) When CL is stopped at the high level
• When the display data is transferred
∼ ∼
CE
0
0
0
0
0
1
0
D1
D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 0
0
0
0
0
0
0
0
Fixed data
5 bits
Display data
88 bits
DD
3 bits
∼ ∼
0
∼ ∼
∼ ∼
CCB address
8 bits
0
0
0
0
0
1
0
D89
D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
88 bits
Fixed data
5 bits
DD
3 bits
∼ ∼
0
0
0
0
0
1
0
D177
D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 0
0
0
0
0
0
0
0
0
0
1
0
∼ ∼
0
1
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
84 bits
Fixed data
9 bits
DD
3 bits
∼ ∼
∼ ∼
CCB address
8 bits
0
∼ ∼
0
B0 B1 B2 B3 A0 A1 A2 A3
∼ ∼
DI
∼ ∼
CL
0
0
0
0
0
1
0
D261
D332 D333 D334 D335 D336 D337 D338 D339 D340 D341 D342 D343 D344 D345 D346 D347 D348 D349 D350 D351 D352 0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
92 bits
DD
Fixed 3 bits
data
1 bits
No.A1976-10/43
LC75809PT
• When the control data is transferred
CE
CL
0
DI
0
0
0
0
0
1
0
P1A P1B P1C P1D P2A P2B P2C P3A P3B P3C P4A P4B P4C P5A P5B P5C P6A P6B P6C P7A P7B P7C P8A P8B P8C P9A P9B P9C
B0 B1 B2 B3 A0 A1 A2 A3
Control data
61 bits
P10A P10B P10C P11A P11B P11C P12A P12B P12C PF0 PF1 PF2 PF3 FC0 FC1 FC2 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN EXF SC BU 0
0
0
0
1
0
0
∼ ∼
∼ ∼
CCB address
8 bits
∼ ∼
∼ ∼
DD
3 bits
0
0
0
0
0
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
45 bits
W40 W41 W42 W43 W44 W45 W50 W51 W52 W53 W54 W55 W60 W61 W62 W63 W64 W65 0
0
0
0
0
0
0
0
0
1
0
1
DD
3 bits
Note: DD is the direction data
• CCB address .........................
• D1 to D352 ...........................
• P1A, P1B, P1C, P1D ............
• P2A, P2B, P2C to P12A,.......
P12B, P12C
• PF0 to PF3 ............................
• FC0 to FC2 ...........................
• OC ........................................
• CT0 to CT2 ..........................
• P0 to P3 ................................
• DT ........................................
• DN ........................................
• EXF ......................................
• SC .........................................
• BU ........................................
• W10 to W15, W20 to W25,...
W30 to W35, W40 to W45,
W50 to W55, W60 to W65
“40H”
Display data
General-purpose output port (P1) function setting control data
General-purpose output port (P2 to P12) function setting control data
PWM output waveform frame frequency setting control data
Common/segment output waveform frame frequency setting control data
Internal oscillator operating mode/external clock operating mode switching control data
Display contrast setting control data
Segment output port/general-purpose output port switching control data
1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
S88 pin and S89/OSCI pin state setting control data
External clock operating frequency setting control data
Segment on/off control data
Normal mode/power-saving mode control data
PWM data of the PWM output
No.A1976-11/43
LC75809PT
2. 1/3 duty
(1) When CL is stopped at the low level
• When the display data is transferred
CL
0
0
0
0
0
0
1
0
D1
D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Fixed data
6 bits
DD
3 bits
∼ ∼ ∼
∼
Display data
87 bits
∼
CCB address
8 bits
0
0
0
0
0
0
1
0 D88
D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
Fixed
data
3 bits
0
1
DD
3 bits
∼ ∼ ∼
∼
Display data
90 bits
0
∼ ∼ ∼
DI
∼ ∼ ∼
∼
CE
0
0
0
0
0
0
1
0 D178
D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
90 bits
0
Fixed
data
3 bits
0
0
1
0
DD
3 bits
No.A1976-12/43
LC75809PT
• When the control data is transferred
CE
CL
0
DI
0
0
0
0
0
1
0 P1A P1B P1C P1D P2A P2B P2C P3A P3B P3C P4A P4B P4C P5A P5B P5C P6A P6B P6C P7A P7B P7C P8A P8B P8C P9A P9B P9C
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
P10A P10B P10C P11A P11B P11C P12A P12B P12C PF0 PF1 PF2 PF3 FC0 FC1 FC2 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN EXF SC BU 0
0
0
0
1
0
0
∼ ∼ ∼
∼
Control data
61 bits
∼ ∼ ∼
∼
DD
3 bits
0
0
0
0
0
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
45 bits
W40 W41 W42 W43 W44 W45 W50 W51 W52 W53 W54 W55 W60 W61 W62 W63 W64 W65 0
0
0
0
0
0
0
0
0
1
0
1
DD
3 bits
Note: DD is the direction data.
No.A1976-13/43
LC75809PT
(2) When CL is stopped at the high level
• When the display data is transferred
∼ ∼
CE
0
0
0
0
0
1
0
D1
D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 0
0
0
0
0
0
0
0
0
∼ ∼
0
DI
1
∼ ∼
CL
B0 B1 B2 B3 A0 A1 A2 A3
Display data
87 bits
Fixed data
6 bits
DD
3 bits
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
0
0
0
0
0
0
1
0
D88
D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
90 bits
0
0
Fixed
data
3 bits
0
DD
3 bits
∼ ∼
∼ ∼
CCB address
8 bits
0
0
0
0
0
0
0
1
0
D178
D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
90 bits
0
Fixed
data
3 bits
0
0
1
0
DD
3 bits
No.A1976-14/43
LC75809PT
• When the control data is transferred
CE
CL
0
DI
0
0
0
0
0
1
0
P1A P1B P1C P1D P2A P2B P2C P3A P3B P3C P4A P4B P4C P5A P5B P5C P6A P6B P6C P7A P7B P7C P8A P8B P8C P9A P9B P9C
B0 B1 B2 B3 A0 A1 A2 A3
Control data
61 bits
P10A P10B P10C P11A P11B P11C P12A P12B P12C PF0 PF1 PF2 PF3 FC0 FC1 FC2 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN EXF SC BU 0
0
0
0
1
0
0
∼ ∼
∼ ∼
CCB address
8 bits
∼ ∼
∼ ∼
DD
3 bits
0
0
0
0
0
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
45 bits
W40 W41 W42 W43 W44 W45 W50 W51 W52 W53 W54 W55 W60 W61 W62 W63 W64 W65 0
0
0
0
0
0
0
0
0
1
0
1
DD
3 bits
Note: DD is the direction data
• CCB address .........................
• D1 to D267 ...........................
• P1A, P1B, P1C, P1D ............
• P2A, P2B, P2C to P12A,.......
P12B, P12C
• PF0 to PF3 ............................
• FC0 to FC2 ...........................
• OC ........................................
• CT0 to CT2 ..........................
• P0 to P3 ................................
• DT ........................................
• DN ........................................
• EXF ......................................
• SC .........................................
• BU ........................................
• W10 to W15, W20 to W25,...
W30 to W35, W40 to W45,
W50 to W55, W60 to W65
“40H”
Display data
General-purpose output port (P1) function setting control data
General-purpose output port (P2 to P12) function setting control data
PWM output waveform frame frequency setting control data
Common/segment output waveform frame frequency setting control data
Internal oscillator operating mode/external clock operating mode switching control data
Display contrast setting control data
Segment output port/general-purpose output port switching control data
1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
S88 pin and S89/OSCI pin state setting control data
External clock operating frequency setting control data
Segment on/off control data
Normal mode/power-saving mode control data
PWM data of the PWM output
No.A1976-15/43
LC75809PT
3. 1/4 duty (Simple mode transfer)
(1) When CL is stopped at the low level
CL
0
0
0
0
0
1
0
D1 D2
D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 0 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN FC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
88 bits
Control data
14 bits
DD
2 bits
∼ ∼ ∼
0
∼
∼
CCB address
8 bits
0
0
0
0
0
1
0 D89 D90
D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
88 bits
Fixed data
14 bits
DD
2 bits
∼
0
0
0
0
0
0
1
0 D177 D178
D255 D256 D257 D258 D259 D260 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
84 bits
Fixed data
18 bits
DD
2 bits
∼ ∼ ∼
∼
CCB address
8 bits
0
0
0
0
0
0
1
0 D261 D262
D339 D340 D341 D342 D343 D344 D345 D346 D347 D348 D349 D350 D351 D352 0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
92 bits
Fixed data
10 bits
DD
2 bits
Note: DD is the direction data.
No.A1976-16/43
∼ ∼ ∼
∼ ∼ ∼
∼
CCB address
8 bits
∼ ∼ ∼
0
DI
∼ ∼ ∼
∼
CE
LC75809PT
(2) When CL is stopped at the high level
∼ ∼
CE
0
0
0
0
0
0
1
0
D1 D2
D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 0 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN FC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
88 bits
Control data
14 bits
DD
2 bits
∼ ∼
0
0
0
0
0
0
1
0
D89 D90
D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
88 bits
Fixed data
14 bits
DD
2 bits
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
0
0
0
0
0
0
1
0
D177 D178
D255 D256 D257 D258 D259 D260 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
84 bits
Fixed data
18 bits
DD
2 bits
∼ ∼
CCB address
8 bits
∼ ∼
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
0
0
0
0
0
0
1
0
D261 D262
D339 D340 D341 D342 D343 D344 D345 D346 D347 D348 D349 D350 D351 D352 0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Note: DD is the direction data
• CCB address .........................
• D1 to D352 ...........................
• OC ........................................
• CT0 to CT2 ..........................
• P0 to P3 ................................
• DT ........................................
• DN ........................................
• FC .........................................
• SC .........................................
• BU ........................................
Display data
92 bits
Fixed data
10 bits
DD
2 bits
“40H”
Display data
Internal oscillator operating mode/external clock operating mode switching control data
Display contrast setting control data
Segment output port/general-purpose output port switching control data
1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
S88 pin and S89/OSCI pin state setting control data
Common/segment output waveform frame frequency setting control data
Segment on/off control data
Normal mode/power-saving mode control data
No.A1976-17/43
∼ ∼
DI
∼ ∼
CL
LC75809PT
4. 1/3 duty (Simple mode transfer)
(1) When CL is stopped at the low level
CL
0
0
0
0
0
0
1
0
D1 D2
D79 D80 D81 D82 D83 D84 D85 D86 D87 0
0 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN FC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
87 bits
Control data
15 bits
DD
2 bits
∼ ∼ ∼
∼
∼
CCB address
8 bits
0
0
0
0
0
0
1
0 D88 D89
D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
90 bits
Fixed data
12 bits
DD
2 bits
∼ ∼ ∼
∼
CCB address
8 bits
0
0
0
0
0
0
1
0 D178 D179
D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
90 bits
Fixed data
12 bits
DD
2 bits
Note: DD is the direction data.
No.A1976-18/43
∼ ∼ ∼
DI
∼ ∼ ∼
∼
CE
LC75809PT
(2) When CL is stopped at the high level
CL
0
0
0
0
0
0
1
0
D1 D2
D79 D80 D81 D82 D83 D84 D85 D86 D87 0
0 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN FC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
87 bits
Control data
15 bits
DD
2 bits
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
0
0
0
0
0
0
1
0
D88 D89
D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
90 bits
Fixed data
12 bits
DD
2 bits
∼ ∼
∼ ∼
CCB address
8 bits
0
0
0
0
0
0
1
0
D178 D179
D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Note: DD is the direction data
• CCB address .........................
• D1 to D267 ...........................
• OC ........................................
• CT0 to CT2 ..........................
• P0 to P3 ................................
• DT ........................................
• DN ........................................
• FC .........................................
• SC .........................................
• BU ........................................
Display data
90 bits
Fixed data
12 bits
DD
2 bits
“40H”
Display data
Internal oscillator operating mode/external clock operating mode switching control data
Display contrast setting control data
Segment output port/general-purpose output port switching control data
1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
S88 pin and S89/OSCI pin state setting control data
Common/segment output waveform frame frequency setting control data
Segment on/off control data
Normal mode/power-saving mode control data
No.A1976-19/43
∼ ∼
DI
∼ ∼
∼ ∼
CE
LC75809PT
Serial Data Transfer Example
1. 1/4 duty
• When 261 or more segments are used
All 496 bits of serial data must be sent.
8 bits
0
0
0
0
0
64 bits
0
1
0
P1A P1B P1C P1D P2A P2B P2C P3A P3B P3C P4A P4B P4C P5A P5B P5C P6A P6B P6C P7A P7B P7C P8A P8B P8C P9A P9B P9C P10A P10B P10C P11A
B0 B1 B2 B3 A0 A1 A2 A3
P11B P11C P12A P12B P12C PF0 PF1 PF2 PF3 FC0 FC1 FC2 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN EXT SC BU 0
8 bits
0
0
0
0
0
0
0
0
1
0
0
48 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 W40 W41 W42 W43 W44 W45
B0 B1 B2 B3 A0 A1 A2 A3
W50 W51 W52 W53 W54 W55 W60 W61 W62 W63 W64 W65 0
0
0
8 bits
0
0
0
0
0
0
0
0
0
0
0
1
0
1
96 bits
0
1
0
D1 D2
D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 0
0
0
0
0
0
0
0
D89 D90
D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 0
0
0
0
0
0
0
1
D177 D178
D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 0
0
0
0
0
0
1
0
D261 D262
D328 D329 D330 D331 D332 D333 D334 D335 D336 D337 D338 D339 D340 D341 D342 D343 D344 D345 D346 D347 D348 D349 D350 D351 D352 0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 261 segments are used
The serial data shown below (the control data) must always be sent.
8 bits
0
0
0
0
0
64 bits
0
1
0
P1A P1B P1C P1D P2A P2B P2C P3A P3B P3C P4A P4B P4C P5A P5B P5C P6A P6B P6C P7A P7B P7C P8A P8B P8C P9A P9B P9C P10A P10B P10C P11A
B0 B1 B2 B3 A0 A1 A2 A3
P11B P11C P12A P12B P12C PF0 PF1 PF2 PF3 FC0 FC1 FC2 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN EXT SC BU 0
8 bits
0
0
0
0
0
0
0
0
1
0
48 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 W40 W41 W42 W43 W44 W45
B0 B1 B2 B3 A0 A1 A2 A3
W50 W51 W52 W53 W54 W55 W60 W61 W62 W63 W64 W65 0
0
0
0
0
0
0
0
0
1
0
1
No.A1976-20/43
0
LC75809PT
2. 1/3 duty
• When 178 or more segments are used
All 400 bits of serial data must be sent.
8 bits
0
0
0
0
0
64 bits
0
1
0
P1A P1B P1C P1D P2A P2B P2C P3A P3B P3C P4A P4B P4C P5A P5B P5C P6A P6B P6C P7A P7B P7C P8A P8B P8C P9A P9B P9C P10A P10B P10C P11A
B0 B1 B2 B3 A0 A1 A2 A3
P11B P11C P12A P12B P12C PF0 PF1 PF2 PF3 FC0 FC1 FC2 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN EXT SC BU 0
8 bits
0
0
0
0
0
0
0
0
1
0
0
48 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 W40 W41 W42 W43 W44 W45
B0 B1 B2 B3 A0 A1 A2 A3
W50 W51 W52 W53 W54 W55 W60 W61 W62 W63 W64 W65 0
0
0
8 bits
0
0
0
0
0
0
0
0
0
0
0
1
0
1
96 bits
0
1
0
D1 D2
D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 0
0
0
0
0
0
0
0
D88 D89
D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 0
0
0
0
0
1
D178 D179
D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 0
0
0
0
1
0
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 178 segments are used
The serial data shown below (the control data) must always be sent.
8 bits
0
0
0
0
0
64 bits
0
1
0
P1A P1B P1C P1D P2A P2B P2C P3A P3B P3C P4A P4B P4C P5A P5B P5C P6A P6B P6C P7A P7B P7C P8A P8B P8C P9A P9B P9C P10A P10B P10C P11A
B0 B1 B2 B3 A0 A1 A2 A3
P11B P11C P12A P12B P12C PF0 PF1 PF2 PF3 FC0 FC1 FC2 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN EXT SC BU 0
8 bits
0
0
0
0
0
0
0
0
1
0
48 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 W40 W41 W42 W43 W44 W45
B0 B1 B2 B3 A0 A1 A2 A3
W50 W51 W52 W53 W54 W55 W60 W61 W62 W63 W64 W65 0
0
0
0
0
0
0
0
0
1
0
1
No.A1976-21/43
0
LC75809PT
3. 1/4 duty (Simple mode transfer)
• When 261 or more segments are used
All 416 bits of serial data must be sent.
8 bits
0
0
0
0
0
104 bits
0
1
0
D1 D2
D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 0 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN FC SC BU 0
0
D89 D90
D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D177 D178
D252 D253 D254 D255 D256 D257 D258 D259 D260 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
D261 D262
D336 D337 D338 D339 D340 D341 D342 D343 D344 D345 D346 D347 D348 D349 D350 D351 D352 0
0
0
0
0
0
0
0
0
0
1
1
D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 0 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN FC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 261 segments are used
Either 104, 208 or 312 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D88 display data and the control data) must always be sent.
8 bits
0
0
0
0
0
104 bits
0
1
0
D1 D2
B0 B1 B2 B3 A0 A1 A2 A3
4. 1/3duty (Simple mode transfer)
• When 178 or more segments are used
All 312 bits of serial data must be sent.
8 bits
0
0
0
0
0
104 bits
0
1
0
D1 D2
D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 0
0 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN FC SC BU 0
0
D88 D89
D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 0
0
0
0
0
0
0
0
0
0
0
0
0
1
D178 D179
D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 0
0
0
0
0
0
0
0
0
0
0
0
1
0
0 OC CT0 CT1 CT2 P0 P1 P2 P3 DT DN FC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 178 segments are used
Either 104 or 208 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D87 display data and the control data) must always be sent.
8 bits
0
0
0
0
0
104 bits
0
1
0
D1 D2
D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 0
B0 B1 B2 B3 A0 A1 A2 A3
No.A1976-22/43
LC75809PT
Control Data Functions
(1) P1A,P1B,P1C,P1D …………………. General-purpose output port (P1) function setting control data
P2A,P2B,P2C to P12A,P12B,P12C … General-purpose output port (P2 to P12) function setting control data
These control data bits set the general-purpose output function (High or low level output), PWM output function or
clock output function of the P1 output pin, and the general-purpose output function (High or low level output) or
PWM output function of the P2 to P12 output pins.
However, be careful of being unable to set a PWM output function when the external clock operating frequency is
set the fCK2=38[kHz]typ (EXF="1") in external clock operating mode (OC= "1").
In addition, be careful of setting of the general-purpose output function (High or low level output) in the case of the
simple mode transfer forcibly.
P1A
P1B
P1C
P1D
General-purpose output port (P1) function
0
0
0
0
General-purpose output function (High or low level output)
1
0
0
0
PWM output function (Ch1) (Support for PWM data W10 to W15)
0
1
0
0
PWM output function (Ch2) (Support for PWM data W20 to W25)
1
1
0
0
PWM output function (Ch3) (Support for PWM data W30 to W35)
0
0
1
0
PWM output function (Ch4) (Support for PWM data W40 to W45)
1
0
1
0
PWM output function (Ch5) (Support for PWM data W50 to W55)
0
1
1
0
PWM output function (Ch6) (Support for PWM data W60 to W65)
1
1
1
0
Clock output function (Clock frequency : fosc/2, fCK/2)
0
0
0
1
Clock output function (Clock frequency : fosc/8, fCK/8)
Note : When are setting (P1A,P1B,P1C,P1D)=(1,X,X,1), (X,1,X,1), and (X,X,1,1), the function of general-purpose
output ports P1 is set the general-purpose output function (High or low level output).
X: don’t care
PnA
PnB
PnC
General-purpose output port (P2 to P12) function
0
0
0
General-purpose output function (High or low level output)
1
0
0
PWM output function (Ch1) (Support for PWM data W10 to W15)
0
1
0
PWM output function (Ch2) (Support for PWM data W20 to W25)
1
1
0
PWM output function (Ch3) (Support for PWM data W30 to W35)
0
0
1
PWM output function (Ch4) (Support for PWM data W40 to W45)
1
0
1
PWM output function (Ch5) (Support for PWM data W50 to W55)
0
1
1
PWM output function (Ch6) (Support for PWM data W60 to W65)
Note1 : The data PnA, PnB and PnC (Note : n=2 to 12) are the control data switching the general-purpose output
function or PWM output function of the general-purpose output ports Pn (Note : n=2 to 12).
For example, if the S10/P10 output pin is set the general-purpose output port, the general-purpose output
port P10 pin is selected the PWM output function (Ch1)
when (P10A,P10B,P10C)=(1,0,0).
Note2 : When are setting (PnA,PnB,PnC)=(1,1,1) / (Note : n=2 to 12), the function of general-purpose output ports
Pn (Note : n=2 to 12) is set the general-purpose output function (High or low level output).
No.A1976-23/43
LC75809PT
(2) PF0 to PF3 … PWM output waveform frame frequency setting control data
These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output
function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency
is set the fCK2=38[kHz]typ (EXF="1") in external clock operating mode (OC= "1") or when the serial data transfer
is the simple mode transfer, these control data bits become invalid.
Control data
PF0
PF1
PF2
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
External clock operating mode
(The control data OC is 0,
(The control data OC is 1 and EXF is 0,
fosc=300[kHz] typ)
fCK1=300[kHz] typ)
PF3
0
0
0
0
fosc/1536
fCK1/1536
1
0
0
0
fosc/1408
fCK1/1408
0
1
0
0
fosc/1280
fCK1/1280
1
1
0
0
fosc/1152
fCK1/1152
0
0
1
0
fosc/1024
fCK1/1024
1
0
1
0
fosc/896
fCK1/896
0
1
1
0
fosc/768
fCK1/768
1
1
1
0
fosc/640
fCK1/640
0
0
0
1
fosc/512
fCK1/512
1
0
0
1
fosc/384
fCK1/384
0
1
0
1
fosc/256
fCK1/256
Note : When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame
frequency at the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, fCK1/896).
X: don’t care
(3) FC0 to FC2 … Common/segment output waveform fram frequency control data
These control data bits set the frame frequency of the common and segment output waveforms.
Control data
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator
FC0
FC1
FC2
operating mode
(The control data OC is 0,
fosc=300[kHz] typ)
External clock
External clock
operating mode
operating mode
(The control data OC is 1
(The control data OC is 1
and EXF is 0,
and EXF is 1,
fCK1=300[kHz] typ)
fCK2=38[kHz] typ)
0
0
0
fosc/6144
fCK1/6144
fCK2/768
0
0
1
fosc/4608
fCK1/4608
fCK2/576
0
1
0
fosc/3072
fCK1/3072
fCK2/384
0
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
fosc/1536
fCK1/1536
fCK2/192
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
0
fosc/768
fCK1/768
fCK2/96
Note : When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384).
However, in the case of the simple mode transfer, the frame frequency of the common and segment output
waveforms is set as following by the control data FC.
Control data
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator operating mode
External clock operating mode
(The control data OC is 0,
(The control data OC is 1
fosc=300[kHz] typ)
fCK1=300[kHz] typ)
0
fosc/3072
fCK1/3072
1
fosc/1536
fCK1/1536
FC
No.A1976-24/43
LC75809PT
(4) OC … Internal oscillator operating mode/external clock operating mode switching control data
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
OC
Fundamental clock operating mode
0
Internal oscillator operating mode
I/O pin (S89/OSCI) state
S89
1
External clock operating mode
OSCI
Note : S89 : Segment output
OSCI : External clock input
(5) CT0 to CT2 … Display contrast setting control data
These control data bits set display contrast.
CT0 to CT2 : Sets the display contrast (7 steps)
CT0
CT1
CT2
LCD drive 3/3 bias voltage VDD0 level
0
0
0
1.00VDD=VDD-(0.05VDD×0)
1
0
0
0.95VDD=VDD-(0.05VDD×1)
0
1
0
0.90VDD=VDD-(0.05VDD×2)
1
1
0
0.85VDD=VDD-(0.05VDD×3)
0
0
1
0.80VDD=VDD-(0.05VDD×4)
1
0
1
0.75VDD=VDD-(0.05VDD×5)
0
1
1
0.70VDD=VDD-(0.05VDD×6)
Note : When is setting (CT0,CT1,CT2)=(1,1,1), the LCD drive 3/3 bias voltage VDD0 level is 1.00VDD.
Note that although the display contrast can be adjusted by operating the built-in display contrast
adjustment circuit, it can also be adjusted by modifying the supply pin VDD voltage level.
(6) P0 to P3 … Segment output port/general-purpose output port switching control data
These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to
S12/P12 output pins.
Control data
Output pin state
P0
P1
P2
P3
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9/P9
0
0
0
0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10/P10 S11/P11 S12/P12
S10
S11
S12
0
0
0
1
P1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
0
0
1
0
P1
P2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
0
0
1
1
P1
P2
P3
S4
S5
S6
S7
S8
S9
S10
S11
S12
0
1
0
0
P1
P2
P3
P4
S5
S6
S7
S8
S9
S10
S11
S12
0
1
0
1
P1
P2
P3
P4
P5
S6
S7
S8
S9
S10
S11
S12
0
1
1
0
P1
P2
P3
P4
P5
P6
S7
S8
S9
S10
S11
S12
0
1
1
1
P1
P2
P3
P4
P5
P6
P7
S8
S9
S10
S11
S12
1
0
0
0
P1
P2
P3
P4
P5
P6
P7
P8
S9
S10
S11
S12
1
0
0
1
P1
P2
P3
P4
P5
P6
P7
P8
P9
S10
S11
S12
1
0
1
0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
S11
S12
1
0
1
1
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
S12
1
1
0
0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
Note1 : Sn(n=1 to 12) : Segment output ports
Pn(n=1 to 12) : General-purpose output ports
Note2 : When are setting (P0,P1,P2,P3)=(1,1,0,1), (1,1,1,0), and (1,1,1,1), the all P1/S1 to P12/S12 output
pins selects the segment output port.
No.A1976-25/43
LC75809PT
The table below lists the correspondence between the display data and the output pins when these pins are selected to be
general-purpose output ports (general-purpose output function).
Correspondence display data
Output pin
1/4 duty
1/3 duty
S1/P1
D1
D1
S2/P2
D5
D4
S3/P3
D9
D7
S4/P4
D13
D10
S5/P5
D17
D13
S6/P6
D21
D16
S7/P7
D25
D19
S8/P8
D29
D22
S9/P9
D33
D25
S10/P10
D37
D28
S11/P11
D41
D31
S12/P12
D45
D34
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port and is set general-purpose output function, the S4/P4 output pin will output a high (VDD) level when the
display data D13 is 1, and will output a low (VSS) level when D13 is 0.
(7) DT … 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
This control data bit selects either 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive.
DT
Drive scheme
The COM4/S87 pin state
0
1/4-duty 1/3-bias drive
COM4
1
1/3-duty 1/3-bias drive
S87
Note : COM4 : Common output
S87 : Segment output
(8) DN … S88 pin and S89/OSCI pin state setting control data
This control data bit sets state of the S88 pin and the S89/OSCI pin.
Number of display segments
DN
Pin state
1/4 duty
1/3 duty
S88
S89/OSCI
0
Up to 344 segments
Up to 261 segments
“L”(VSS)
“L”(VSS)/OSCI
1
Up to 352 segments
Up to 267 segments
S88
S89/OSCI
Note : "L" (VSS)
: Low (VSS) level output
S88
: Segment output
"L" (VSS)/OSCI : Low (VSS) level output in internal oscillator operating mode (OC=0)
External clock input in external clock operating mode (OC=1)
S89/OSCI
: Segment output in internal oscillator operating mode (OC=0)
External clock input in external clock operating mode (OC=1)
(9) EXF … External clock operating frequency setting control data
This control data bit sets the operating frequency of the external clock which input into the OSCI pin, when the
external clock operating mode (OC="1") is set. However, be careful of setting the fCK1=300[kHz]typ when the
external clock operating mode (OC="1") is set in the case of the simple mode transfer forcibly. In addition, this data
is effective only when external clock operating mode (OC= "1") is set.
EXF
External clock operating frequency fCK[kHz]
0
fCK1=300[kHz] typ
1
fCK2=38[kHz] typ
No.A1976-26/43
LC75809PT
(10) SC … Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
1
Off
Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off
waveforms from the segment output pins.
(11) BU … Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
0
Mode
Normal mode
Power saving mode
In this mode, the internal oscillator circuit stops oscillation (the S89/OSCI pin is configured for segment output) if the IC is
in the internal oscillator operating mode (OC=0) and the IC stops receiving external clock signals (the S89/OSCI pin is
1
configured for external clock input) if the IC is in the external clock operating mode (OC=1).
The common and segment output pins go to the VSS level. However, the S1/P1 to S12/P12 output pins can be used as
general-purpose output ports under the control of the data bits P0 to P3.
(The general-purpose output port P1 to P12 can not be used as PWM output or clock output).
No.A1976-27/43
LC75809PT
(12) W10 to W15, W20 to W25, W30 to W35 , W40 to W45, W50 to W55, W60 to W65 … PWM data of the PWM output
These control data bits set the pulse width of the PWM output P1 to P12. However, when the PWM output
function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency
is set the fCK2=38[kHz]typ (EXF="1") in external clock operating mode (OC= "1") or when the serial data
transfer is the simple mode transfer, these control data bits become invalid.
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
1
1
0
Pulse width of
Pulse width of
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
(1/64)×Tp
0
0
0
0
0
1
(33/64)×Tp
(2/64)×Tp
1
0
0
0
0
1
(34/64)×Tp
0
(3/64)×Tp
0
1
0
0
0
1
(35/64)×Tp
0
0
(4/64)×Tp
1
1
0
0
0
1
(36/64)×Tp
0
0
(5/64)×Tp
0
0
1
0
0
1
(37/64)×Tp
0
0
0
(6/64)×Tp
1
0
1
0
0
1
(38/64)×Tp
1
0
0
0
(7/64)×Tp
0
1
1
0
0
1
(39/64)×Tp
1
0
0
0
(8/64)×Tp
1
1
1
0
0
1
(40/64)×Tp
0
0
1
0
0
(9/64)×Tp
0
0
0
1
0
1
(41/64)×Tp
1
0
0
1
0
0
(10/64)×Tp
1
0
0
1
0
1
(42/64)×Tp
0
1
0
1
0
0
(11/64)×Tp
0
1
0
1
0
1
(43/64)×Tp
1
1
0
1
0
0
(12/64)×Tp
1
1
0
1
0
1
(44/64)×Tp
0
0
1
1
0
0
(13/64)×Tp
0
0
1
1
0
1
(45/64)×Tp
1
0
1
1
0
0
(14/64)×Tp
1
0
1
1
0
1
(46/64)×Tp
0
1
1
1
0
0
(15/64)×Tp
0
1
1
1
0
1
(47/64)×Tp
1
1
1
1
0
0
(16/64)×Tp
1
1
1
1
0
1
(48/64)×Tp
0
0
0
0
1
0
(17/64)×Tp
0
0
0
0
1
1
(49/64)×Tp
1
0
0
0
1
0
(18/64)×Tp
1
0
0
0
1
1
(50/64)×Tp
0
1
0
0
1
0
(19/64)×Tp
0
1
0
0
1
1
(51/64)×Tp
1
1
0
0
1
0
(20/64)×Tp
1
1
0
0
1
1
(52/64)×Tp
0
0
1
0
1
0
(21/64)×Tp
0
0
1
0
1
1
(53/64)×Tp
1
0
1
0
1
0
(22/64)×Tp
1
0
1
0
1
1
(54/64)×Tp
0
1
1
0
1
0
(23/64)×Tp
0
1
1
0
1
1
(55/64)×Tp
1
1
1
0
1
0
(24/64)×Tp
1
1
1
0
1
1
(56/64)×Tp
0
0
0
1
1
0
(25/64)×Tp
0
0
0
1
1
1
(57/64)×Tp
1
0
0
1
1
0
(26/64)×Tp
1
0
0
1
1
1
(58/64)×Tp
0
1
0
1
1
0
(27/64)×Tp
0
1
0
1
1
1
(59/64)×Tp
1
1
0
1
1
0
(28/64)×Tp
1
1
0
1
1
1
(60/64)×Tp
0
0
1
1
1
0
(29/64)×Tp
0
0
1
1
1
1
(61/64)×Tp
1
0
1
1
1
0
(30/64)×Tp
1
0
1
1
1
1
(62/64)×Tp
0
1
1
1
1
0
(31/64)×Tp
0
1
1
1
1
1
(63/64)×Tp
1
1
1
1
1
0
(32/64)×Tp
1
1
1
1
1
1
(64/64)×Tp
PWM output
Note : W10 to W15 … PWM data of the PWM output (Ch1)
W20 to W25 … PWM data of the PWM output (Ch2)
W30 to W35 … PWM data of the PWM output (Ch3)
W40 to W45 … PWM data of the PWM output (Ch4)
W50 to W55 … PWM data of the PWM output (Ch5)
W60 to W65 … PWM data of the PWM output (Ch6)
PWM output
n=1 to 6
1
Tp= fp
No.A1976-28/43
LC75809PT
Display Data and Output Pin Correspondence (1/4 Duty)
Output pin
COM1
COM2
COM3
COM4
Output pin
COM1
COM2
COM3
COM4
S1/P1
D1
D2
D3
D4
S45
D177
D178
D179
D180
S2/P2
D5
D6
D7
D8
S46
D181
D182
D183
D184
S3/P3
D9
D10
D11
D12
S47
D185
D186
D187
D188
S4/P4
D13
D14
D15
D16
S48
D189
D190
D191
D192
S5/P5
D17
D18
D19
D20
S49
D193
D194
D195
D196
S6/P6
D21
D22
D23
D24
S50
D197
D198
D199
D200
S7/P7
D25
D26
D27
D28
S51
D201
D202
D203
D204
S8/P8
D29
D30
D31
D32
S52
D205
D206
D207
D208
S9/P9
D33
D34
D35
D36
S53
D209
D210
D211
D212
S10/P10
D37
D38
D39
D40
S54
D213
D214
D215
D216
S11/P11
D41
D42
D43
D44
S55
D217
D218
D219
D220
S12/P12
D45
D46
D47
D48
S56
D221
D222
D223
D224
S13
D49
D50
D51
D52
S57
D225
D226
D227
D228
S14
D53
D54
D55
D56
S58
D229
D230
D231
D232
S15
D57
D58
D59
D60
S59
D233
D234
D235
D236
S16
D61
D62
D63
D64
S60
D237
D238
D239
D240
S17
D65
D66
D67
D68
S61
D241
D242
D243
D244
S18
D69
D70
D71
D72
S62
D245
D246
D247
D248
S19
D73
D74
D75
D76
S63
D249
D250
D251
D252
S20
D77
D78
D79
D80
S64
D253
D254
D255
D256
S21
D81
D82
D83
D84
S65
D257
D258
D259
D260
S22
D85
D86
D87
D88
S66
D261
D262
D263
D264
S23
D89
D90
D91
D92
S67
D265
D266
D267
D268
S24
D93
D94
D95
D96
S68
D269
D270
D271
D272
S25
D97
D98
D99
D100
S69
D273
D274
D275
D276
S26
D101
D102
D103
D104
S70
D277
D278
D279
D280
S27
D105
D106
D107
D108
S71
D281
D282
D283
D284
S28
D109
D110
D111
D112
S72
D285
D286
D287
D288
S29
D113
D114
D115
D116
S73
D289
D290
D291
D292
S30
D117
D118
D119
D120
S74
D293
D294
D295
D296
S31
D121
D122
D123
D124
S75
D297
D298
D299
D300
S32
D125
D126
D127
D128
S76
D301
D302
D303
D304
S33
D129
D130
D131
D132
S77
D305
D306
D307
D308
S34
D133
D134
D135
D136
S78
D309
D310
D311
D312
S35
D137
D138
D139
D140
S79
D313
D314
D315
D316
S36
D141
D142
D143
D144
S80
D317
D318
D319
D320
S37
D145
D146
D147
D148
S81
D321
D322
D323
D324
S38
D149
D150
D151
D152
S82
D325
D326
D327
D328
S39
D153
D154
D155
D156
S83
D329
D330
D331
D332
S40
D157
D158
D159
D160
S84
D333
D334
D335
D336
S41
D161
D162
D163
D164
S85
D337
D338
D339
D340
S42
D165
D166
D167
D168
S86
D341
D342
D343
D344
S43
D169
D170
D171
D172
S88
D345
D346
D347
D348
S44
D173
D174
D175
D176
S89/OSCI
D349
D350
D351
D352
Note : This table assumes that pins S1/P1 to S12/P12 and S89/OSCI are configured for segment output.
No.A1976-29/43
LC75809PT
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D81
D82
D83
D84
0
0
0
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
0
0
0
1
The LCD segment corresponding to COM4 is on.
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segment corresponding to COM3 and COM4 are on.
0
1
0
0
The LCD segment corresponding to COM2 is on.
0
1
0
1
The LCD segment corresponding to COM2 and COM4 are on.
0
1
1
0
The LCD segment corresponding to COM2 and COM3 are on.
0
1
1
1
The LCD segments corresponding to COM2, COM3, and COM4 are on.
1
0
0
0
The LCD segment corresponding to COM1 is on.
1
0
0
1
The LCD segment corresponding to COM1 and COM4 are on.
1
0
1
0
The LCD segment corresponding to COM1 and COM3 are on.
1
0
1
1
The LCD segments corresponding to COM1, COM3, and COM4 are on.
1
1
0
0
The LCD segment corresponding to COM1 and COM2 are on.
1
1
0
1
The LCD segments corresponding to COM1, COM2, and COM4 are on.
1
1
1
0
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
1
1
1
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
No.A1976-30/43
LC75809PT
Display Data and Output Pin Correspondence (1/3 Duty)
Output pin
COM1
COM2
COM3
Output pin
COM1
COM2
COM3
S1/P1
D1
D2
D3
S46
D136
D137
D138
S2/P2
D4
D5
D6
S47
D139
D140
D141
S3/P3
D7
D8
D9
S48
D142
D143
D144
S4/P4
D10
D11
D12
S49
D145
D146
D147
S5/P5
D13
D14
D15
S50
D148
D149
D150
S6/P6
D16
D17
D18
S51
D151
D152
D153
S7/P7
D19
D20
D21
S52
D154
D155
D156
S8/P8
D22
D23
D24
S53
D157
D158
D159
S9/P9
D25
D26
D27
S54
D160
D161
D162
S10/P10
D28
D29
D30
S55
D163
D164
D165
S11/P11
D31
D32
D33
S56
D166
D167
D168
S12/P12
D34
D35
D36
S57
D169
D170
D171
S13
D37
D38
D39
S58
D172
D173
D174
S14
D40
D41
D42
S59
D175
D176
D177
S15
D43
D44
D45
S60
D178
D179
D180
S16
D46
D47
D48
S61
D181
D182
D183
S17
D49
D50
D51
S62
D184
D185
D186
S18
D52
D53
D54
S63
D187
D188
D189
S19
D55
D56
D57
S64
D190
D191
D192
S20
D58
D59
D60
S65
D193
D194
D195
S21
D61
D62
D63
S66
D196
D197
D198
S22
D64
D65
D66
S67
D199
D200
D201
S23
D67
D68
D69
S68
D202
D203
D204
S24
D70
D71
D72
S69
D205
D206
D207
S25
D73
D74
D75
S70
D208
D209
D210
S26
D76
D77
D78
S71
D211
D212
D213
S27
D79
D80
D81
S72
D214
D215
D216
S28
D82
D83
D84
S73
D217
D218
D219
S29
D85
D86
D87
S74
D220
D221
D222
S30
D88
D89
D90
S75
D223
D224
D225
S31
D91
D92
D93
S76
D226
D227
D228
S32
D94
D95
D96
S77
D229
D230
D231
S33
D97
D98
D99
S78
D232
D233
D234
S34
D100
D101
D102
S79
D235
D236
D237
S35
D103
D104
D105
S80
D238
D239
D240
S36
D106
D107
D108
S81
D241
D242
D243
S37
D109
D110
D111
S82
D244
D245
D246
S38
D112
D113
D114
S83
D247
D248
D249
S39
D115
D116
D117
S84
D250
D251
D252
S40
D118
D119
D120
S85
D253
D254
D255
S41
D121
D122
D123
S86
D256
D257
D258
S42
D124
D125
D126
S87/COM4
D259
D260
D261
S43
D127
D128
D129
S88
D262
D263
D264
S44
D130
D131
D132
S89/OSCI
D265
D266
D267
S45
D133
D134
D135
Note : This table assumes that pins S1/P1 to S12/P12, S87/COM4 and S89/OSCI are configured for segment
output.
No.A1976-31/43
LC75809PT
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D61
D62
D63
0
0
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
0
0
1
The LCD segment corresponding to COM3 is on.
0
1
0
The LCD segment corresponding to COM2 is on.
0
1
1
The LCD segment corresponding to COM2 and COM3 are on.
1
0
0
The LCD segment corresponding to COM1 is on.
1
0
1
The LCD segment corresponding to COM1 and COM3 are on.
1
1
0
The LCD segment corresponding to COM1 and COM2 are on.
1
1
1
The LCD segments corresponding to COM1, COM2, and COM3 are on.
No.A1976-32/43
LC75809PT
Output waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
COM1
COM2
COM3
COM4
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3
are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are on.
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
No.A1976-33/43
LC75809PT
Control data
FC0
FC1
Common/segment output waveform frame frequency fo[Hz]
FC2
Internal oscillator operating mode
External clock operating mode
(The control data OC is 0,
(The control data OC is 1
External clock operating mode
(The control data OC is 1
fosc=300[kHz] typ)
and EXF is 0, fCK1=300[kHz] typ)
and EXF is 1, fCK2=38[kHz] typ)
0
0
0
fosc/6144
fCK1/6144
fCK2/768
0
0
1
fosc/4608
fCK1/4608
fCK2/576
0
1
0
fosc/3072
fCK1/3072
fCK2/384
0
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
fosc/1536
fCK1/1536
fCK2/192
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
0
fosc/768
fCK1/768
fCK2/96
Note : When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time
of the (FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384).
In addition, if the serial data transfer is the simple mode transfer, the frame frequency is set the fosc/3072
or fCK1/3072 when the control data FC is 0, and is set the fosc/1536 or fCK1/1536 when FC is 1.
No.A1976-34/43
LC75809PT
Output waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]
COM1
VDD0
VDD1
VDD2
0V
COM2
VDD0
VDD1
VDD2
0V
COM3
VDD0
VDD1
VDD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
VDD0
VDD1
VDD2
0V
VDD0
VDD1
VDD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VDD0
VDD1
VDD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VDD0
VDD1
VDD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VDD0
VDD1
VDD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VDD0
VDD1
VDD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VDD0
VDD1
VDD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2,and COM3
are on.
VDD0
VDD1
VDD2
0V
No.A1976-35/43
LC75809PT
Control data
FC0
FC1
Common/segment output waveform frame frequency fo[Hz]
FC2
External clock operating mode
Internal oscillator operating mode
External clock operating mode
(The control data OC is 0,
(The control data OC is 1
(The control data OC is 1
fosc=300[kHz] typ)
and EXF is 0, fCK1=300[kHz] typ)
and EXF is 1, fCK2=38[kHz] typ)
0
0
0
fosc/6144
fCK1/6144
fCK2/768
0
0
1
fosc/4608
fCK1/4608
fCK2/576
0
1
0
fosc/3072
fCK1/3072
fCK2/384
0
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
fosc/1536
fCK1/1536
fCK2/192
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
0
fosc/768
fCK1/768
fCK2/96
Note : When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time
of the (FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384).
In addition, if the serial data transfer is the simple mode transfer, the frame frequency is set the fosc/3072
or fCK1/3072 when the control data FC is 0, and is set the fosc/1536 or fCK1/1536 when FC is 1.
No.A1976-36/43
LC75809PT
PWM output waveforms
VDD
P1 to P12
(PWM output Ch1)
(56/64)×Tp
VSS
(56/64)×Tp
VDD
P1 to P12
(PWM output Ch2)
VSS
(48/64)×Tp
(48/64)×Tp
VDD
P1 to P12
(PWM output Ch3)
(1)
(40/64)×Tp
VSS
(40/64)×Tp
VDD
P1 to P12
(PWM output Ch4)
VSS
(32/64)×Tp
(32/64)×Tp
VDD
P1 to P12
(PWM output Ch5)
VSS
(24/64)×Tp
(24/64)×Tp
VDD
P1 to P12
(PWM output Ch6)
VSS
(16/64)×Tp
(16/64)×Tp
VDD
P1 to P12
(PWM output Ch1)
(8/64)×Tp
VSS
(8/64)×Tp
VDD
P1 to P12
(PWM output Ch2)
VSS
(24/64)×Tp
(24/64)×Tp
VDD
P1 to P12
(PWM output Ch3)
(48/64)×Tp
(2)
VSS
(48/64)×Tp
VDD
P1 to P12
(PWM output Ch4)
(16/64)×Tp
VSS
(16/64)×Tp
VDD
P1 to P12
(PWM output Ch5)
VSS
(32/64)×Tp
(32/64)×Tp
VDD
P1 to P12
(PWM output Ch6)
(40/64)×Tp
VSS
(40/64)×Tp
Tp
Tp=
Tp
1
fp
Control data
PWM output Ch1
PWM
PWM output Ch2
output
PWM output Ch3
W10
W11
W12
W13
W14
W15
W20
W21
W22
W23
W24
W25
W30
W31
W32
W33
W34
W35
waveforms
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
0
1
(1)
1
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
0
1
(2)
Control data
PWM output Ch4
PWM
PWM output Ch5
output
PWM output Ch6
W40
W41
W42
W43
W44
W45
W50
W51
W52
W53
W54
W55
W60
W61
W62
W63
W64
W65
waveforms
1
1
1
1
1
0
1
1
1
0
1
0
1
1
1
1
0
0
(1)
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
0
1
(2)
Continued on next page.
No.A1976-37/43
LC75809PT
Continued from preceding page.
Control data
PF0
PF1
PF2
PWM output waveform frame frequency fp[Hz]
PF3
Internal oscillator operating mode
External clock operating mode
(The control data OC is 0,
(The control data OC is 1 and
fosc=300[kHz] typ)
EXF is 0, fCK1=300[kHz] typ)
0
0
0
0
fosc/1536
fCK1/1536
1
0
0
0
fosc/1408
fCK1/1408
0
1
0
0
fosc/1280
fCK1/1280
1
1
0
0
fosc/1152
fCK1/1152
0
0
1
0
fosc/1024
fCK1/1024
1
0
1
0
fosc/896
fCK1/896
0
1
1
0
fosc/768
fCK1/768
1
1
1
0
fosc/640
fCK1/640
0
0
0
1
fosc/512
fCK1/512
1
0
0
1
fosc/384
fCK1/384
0
1
0
1
fosc/256
fCK1/256
Note: When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame frequency at
the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, fCK1/896).
X: don’t care
Clock output waveforms
Control data
P1
Tc/2
1
Tc=
fc
Clock frequency of clock output P1
P1A
P1B
P1C
P1D
1
1
1
0
0
0
0
1
Tc
fc(=1/Tc)[Hz]
Clock output function
(fosc/2, fCK/2)
Clock output function
(fosc/8, fCK/8)
No.A1976-38/43
LC75809PT
Display Control and the INH Pin
Since the LSI internal data (1/4 duty : the display data D1 to D352 and the control data, 1/3 duty : the display data D1 to
D267 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same
time as power is applied to turn off the display (This sets the S1/P1 to S12/P12, S13 to S86, COM1 to COM3,
COM4/S87, S88, and S89/OSCI pins to the VSS level.) and during this period send serial data from the controller. The
controller should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless
display at power on. (See Figure 5, Figure 6, Figure 7 and Figure 8.)
(1)1/4 duty
t2
≈
t1
≈
VDD
INH
VIL1
tc
CE
≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈
P1A,P1B,P1C,P1D,
P2A,P2B,P2C to P12A,P12B,P12C
Internal data PF0 to PF3,FC0 to FC2,OC,CT0 to CT2
P0 to P3,DT,DN,EXT,SC,BU
W10 to W15,W20 to W25,W30 to W35
Internal data W40 to W45,W50 to W55,W60 to W65
VIL1
Display data and control data transferred
Undefined
Defined
Undefined
Undefined
Defined
Undefined
Internal data (D1 to D88)
Undefined
Defined
Undefined
Internal data (D89 to D176)
Undefined
Defined
Undefined
Internal data (D177 to D260)
Undefined
Defined
Undefined
Internal data (D261 to D352)
Undefined
Defined
Undefined
Note : t1>1ms
t2>0
tc … 10μs min
[Figure 5]
(2)1/3 duty
t2
≈
t1
≈
VDD
INH
VIL1
tc
CE
≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈
P1A,P1B,P1C,P1D,
P2A,P2B,P2C to P12A,P12B,P12C
Internal data PF0 to PF3,FC0 to FC2,OC,CT0 to CT2
P0 to P3,DT,DN,EXT,SC,BU
W10 to W15,W20 to W25,W30 to W35
Internal data W40 to W45,W50 to W55,W60 to W65
VIL1
Display data and control data transferred
Undefined
Defined
Undefined
Undefined
Defined
Undefined
Internal data (D1 to D87)
Undefined
Defined
Undefined
Internal data (D88 to D177)
Undefined
Defined
Undefined
Internal data (D178 to D267)
Undefined
Defined
Undefined
Note : t1>1ms
t2>0
tc … 10μs min
[Figure 6]
No.A1976-39/43
LC75809PT
(3)1/4 duty (Simple mode transfer)
t2
≈
t1
≈
VDD
INH
VIL1
tc
CE
≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈
VIL1
Display data and control
data transferred
D1 to D88,OC
Internal data CT0 to CT2,P0 to P3,
DT,DN,FC,SC,BU
Undefined
Defined
Undefined
Internal data (D89 to D176)
Undefined
Defined
Undefined
Internal data (D177 to D260)
Undefined
Defined
Undefined
Internal data (D261 to D352)
Undefined
Defined
Undefined
Note : t1>1ms
t2>0
tc … 10μs min
[Figure 7]
(4)1/3 duty (Simple mode transfer)
t2
≈
t1
≈
VDD
INH
VIL1
tc
CE
≈ ≈ ≈ ≈ ≈ ≈ ≈
VIL1
Display data and control
data transferred
D1 to D87,OC
Internal data CT0 to CT2,P0 to P3,
DT,DN,FC,SC,BU
Undefined
Defined
Undefined
Internal data (D88 to D177)
Undefined
Defined
Undefined
Internal data (D178 to D267)
Undefined
Defined
Undefined
Note : t1>1ms
t2>0
tc … 10μs min
[Figure 8]
No.A1976-40/43
LC75809PT
Notes on Controller Transfer of Display Data
When using the LC75809PT in 1/4 duty, applications transfer the display data (D1 to D352) in four operations,
and in 1/3 duty, they transfer the display data (D1 to D267) in three operations. In either case, applications
should transfer all of the display data within 30 ms to maintain the quality of displayed image.
S89/OSCI Pin Peripheral Circuit
(1) Internal oscillator operating mode (control data OC=0)
Connect the S89/OSCI pin to the LCD panel when the internal oscillator operating mode is selected.
OSCI/S89
To LCD panel
(2) External clock operating mode (control data OC=1)
When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22kΩ) between
the S89/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according
to the allowable current value at the external clock output pin. Also make sure that the waveform of the external
clock is not heavily distorted.
External clock output pin
OSCI/S89
Rg
External oscillator
Note : Allowable current value at external clock output pin >
VDD
Rg
(3) Unused pin treatment
When the S89/OSCI pin is not to be used, select the internal oscillator operating mode (setting control data OC to 0)
to keep the pin open.
OSCI/S89
OPEN
P1 to P12 Pin Peripheral Circuit
It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using the PWM output
P1 to P12
+5V
LED
P1 to P12
No.A1976-41/43
LC75809PT
Sample Application Circuit 1
1/4 Duty, 1/3Bias
(P1)
(P2)
(P12)
VDD
+5V
General-purpose
output ports
Used for functions
such as backlight
control
COM1
COM2
VDD1
LCD panel (up to 352 segments)
COM3
S87/COM4
VDD2
C
P1/S1
C
P2/S2
VSS
P12/S12
S13
C≥0.047μF
INH
CE
From the
controller
S86
S88
*3
CL
DI
*4
OSCI/S89
*3 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*4 Connect the S89/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg (2.2 to 22kΩ) between the S89/OSCI pin and external clock output pin (external oscillator) in the external
clock operating mode (see “S89/OSCI Pin Peripheral Circuit”)
Sample Application Circuit 2
1/3 Duty, 1/3 Bias
(P1)
(P2)
(P12)
Used for functions
such as backlight
control
COM1
VDD
+5V
General-purpose
output ports
COM3
P1/S1
VDD2
C
P2/S2
C
VSS
P12/S12
S13
C≥0.047μF
From the
controller
INH
CE
S86
COM4/S87
*3
S88
CL
DI
LCD panel (up to 267 segments)
COM2
VDD1
*4
OSCI/S89
*3 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*4 Connect the S89/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg (2.2 to 22kΩ) between the S89/OSCI pin and external clock output pin (external oscillator) in the external
clock operating mode (see “S89/OSCI Pin Peripheral Circuit”)
No.A1976-42/43
LC75809PT
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PS No.A1976-43/43
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