ENA2226 D

Ordering number : ENA2226B
LC75843UGA
CMOS IC
1/1 to 1/4 Duty General-Purpose
LCD Display Driver
http://onsemi.com
Overview
The LC75843UGA is the 1/1 to 1/4 duty general-purpose microprocessor-controlled LCD driver that can be used in
applications such as Automotive display. In addition to being able to drive up to 100 segments directly, the
LC75843UGA can also control up to 4 general-purpose output ports. Because it has the PWM output of a maximum
of 3ch, the brightness control of the LED backlight of RGB can be done. Incorporation of an oscillation circuit helps
to reduce the number of external resistors and capacitors required.
Features
 Support for static(1/1duty) or 1/2-duty 1/2-bias or 1/3-duty 1/3-bias or 1/4-duty 1/3-bias drive techniques under
serial data control.
When 1/1-duty : Capable of driving up to 28 segments
When 1/2-duty : Capable of driving up to 54 segments
When 1/3-duty : Capable of driving up to 78 segments
When 1/4-duty : Capable of driving up to 100 segments
 Serial data input supports CCB format communication with the system controller.
(Support 3.3V and 5V operation)
 Serial data control of the power-saving mode based backup function and the all segments forced off function.
 Serial data control of switching between the segment output port and general-purpose output port function.
(Support for up to 4 general-purpose output ports)
 Support for the PWM output function of a maximum of 3ch. ( It can output from the general-purpose output port ).
 Support for clock output function of 1ch.( It can output from the general-purpose output port ).
 Serial data control of the frame frequency of the common and segment output waveforms.
 Serial data control of switching between the internal oscillator operating mode and external clock operating mode.
 High generality, since display data is displayed directly without the intervention of a decoder circuit.
 Built-in LCD drive bias voltage stabilization circuit.
 The INH pin allows the display to be forced to the off state.
 Incorporation of an oscillator circuit. (Incorporation of resistor and capacitor for an oscillation)
 AEC-Q100 qualified and PPAP capable.

CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
TSSOP36(275mil)

CCB is a registered trademark of Semiconductor Components Industries, LLC.
ORDERING INFORMATION
See detailed ordering and shipping information on page 35 of this data sheet.
Semiconductor Components Industries, LLC, 2014
January, 2014
12314HK 20131220-S00002/D2013HK/D1113HKPC No.A2226-1/35
LC75843UGA
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter
Symbol
Conditions
Maximum supply voltage
VDD max
VDD
Input voltage
VIN
CE, CL, DI, INH, OSCI
Output voltage
VOUT
S1 to S28, COM1 to COM4, P1 to P4
Output current
IOUT1
S1 to S28
Ratings
Unit
-0.3 to +6.8
V
-0.3 to +6.8
V
-0.3 to VDD+0.3
V
300
A
IOUT2
COM1 to COM4
3
IOUT3
P1 to P4
5
Allowable power dissipation
Pd max
Ta = 105C
Operating temperature
Topr
-40 to +105
C
Storage temperature
Tstg
-55 to +125
C
mA
50
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +105C, VSS = 0V
Ratings
Parameter
Symbol
Conditions
Unit
min
Supply voltage
Input high level voltage
Input low level voltage
VDD
VDD
typ
max
4.5
6.3
VIH1
CE, CL, DI, INH
0.4VDD
6.3
VIH2
OSCI
0.4VDD
6.3
V
V
VIL1
CE, CL, DI, INH
0
0.2VDD
VIL2
OSCI
0
0.2VDD
External clock operating frequency
fCK
OSCI, External clock operating mode [Figure 3]
10
300
600
kHz
External clock duty cycle
DCK
OSCI, External clock operating mode [Figure 3]
30
50
70
%
Data setup time
tds
CL, DI
[Figure 1], [Figure 2]
160
ns
Data hold time
tdh
CL, DI
[Figure 1], [Figure 2]
160
ns
CE wait time
tcp
CE, CL
[Figure 1], [Figure 2]
160
ns
CE setup time
tcs
CE, CL
[Figure 1], [Figure 2]
160
ns
CE hold time
tch
CE, CL
[Figure 1], [Figure 2]
160
ns
High level clock pulse width
tH
CL
[Figure 1], [Figure 2]
160
ns
Low level clock pulse width
tL
CL
[Figure 1], [Figure 2]
160
Rise time
tr
CE, CL, DI
[Figure 1], [Figure 2]
160
ns
Fall time
tf
CE, CL, DI
[Figure 1], [Figure 2]
160
ns
INH switching time
tc
INH, CE
[Figure 4], [Figure 5]
[Figure 6], [Figure 7]
10
V
ns
s
No.A2226-2/35
LC75843UGA
Electrical Characteristics for the Allowable Operating Ranges
Ratings
Parameter
Symbol
Pin
Conditions
Unit
min
typ
max
Hysteresis
VH
CE, CL, DI, INH
Input high level current
IIH1
CE, CL, DI, INH
VI = 6.3V
5.0
IIH2
OSCI
VI = 6.3V
5.0
Input low level current
Output high level voltage
Output low level voltage
Output middle level
0.03VDD
IIL1
CE, CL, DI, INH
VI = 0V
-5.0
IIL2
OSCI
VI = 0V
-5.0
VOH1
S1 to S28
IO = -20A
VOH2
COM1 to COM4
IO = -100A
VDD-0.9
VOH3
P1 to P4
IO = -1mA
VDD-0.9
VOL1
S1 to S28
IO = 20A
0.9
VOL2
COM1 to COM4
IO = 100A
0.9
VOL3
P1 to P4
IO = 1mA
0.9
VMID1
S1 to S25, S28
1/3 bias IO = ±20A
voltage
V
2/3VDD
+0.9
1/3VDD
1/3VDD
-0.9
+0.9
VMID3
COM1 to COM4
1/3 bias IO = ±100A
2/3VDD
2/3VDD
-0.9
+0.9
1/3VDD
1/3VDD
1/3 bias IO = ±100A
VMID5
COM1, COM2
1/2 bias IO = ±100A
fosc
Internal oscillator
Internal oscillator operating mode
IDD1
VDD
Power-saving mode
IDD2
VDD
VDD = 6.3V
Output open
-0.9
+0.9
1/2VDD
1/2VDD
-0.9
+0.9
240
V
2/3VDD
-0.9
1/3 bias IO = ±20A
circuit
Current drain
VDD-0.9
S1 to S25, S28
COM1 to COM4
A
A
VMID2
VMID4
Oscillator frequency
V
300
360
V
kHz
100
750
1500
Internal oscillator operating mode
IDD3
VDD
VDD = 6.3V
Output open
External clock operating mode
fCK = 300kHz
A
750
1500
VIH2 = 0.5VDD
VIL2 = 0.1VDD
*We have a case to change these electrical characteristics without a notice for improvement.
No.A2226-3/35
LC75843UGA

1. When CL is stopped at the low level
VIH1
tH
VIH1
50%
VIL1
CL
 
tr
tf
VIH1
DI
VIL1
tds
tcp
  
tL
VIL1
 
CE
tcs
tch
tdh
[Figure 1]

2. When CL is stopped at the high level
VIH1
VIL1

CE
tH

tL
tr
tcp
tcs
VIH1
DI
VIL1
tds
tch
 
tf
  
VIH1
50%
VIL1
CL
tdh
[Figure 2]
3. OSCI pin clock timing in external clock operating mode
tCKH
OSCI
fCK=
tCKL
VIH2
50%
VIL2
1
tCKH + tCKL
[kHz]
tCKH
100[%]
DCK=
tCKH + tCKL
[Figure 3]
No.A2226-4/35
S18
S17
S15
S16
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
P4/S4
P3/S3
P2/S2
P1/S1
DI
S19
S20
S22
S21
S23
S24
COM4/S25
COM3/S26
COM2/S27
COM1
S28
VDD
VSS
OSCI
INH
CE
CL
LC75843UGA
Pin Assignment
36
19
LC75843UGA
(TSSOP36)
1
18
Top view
Package Dimensions
TSSOP36(275mil)
unit : mm
No.A2226-5/35
LC75843UGA
COMMON
DRIVER
S1/P1
S2/P2
S3/P3
S4/P4
S5
S24
S23
S28
COM3/S26
COM4/S25
COM2/S27
COM1
Block Diagram
SEGMENT DRIVER & LATCH
INH
OSCI
CLOCK
GENERATOR
CONTROL
REGISTER
VDD
SHIFT REGISTER
LCD DRIVE
BIAS VOLTAGE
STABILIZATION
CIRCUIT
2/3VDD
1/3VDD
1/2VDD
CCB INTERFACE
CE
CL
DI
VSS
No.A2226-6/35
LC75843UGA
Pin Functions
Symbol
Pin No.
Function
S1/P1 to S4/P4
1 to 4
Segment outputs for displaying the display data transferred by serial data
S5 to S24
5 to 24
input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports
S28
29
under serial data control.
COM1
28
Common driver outputs
COM2/S27
27
The frame frequency is fo[Hz].
COM3/S26
26
The COM2/S27 to COM4/S25 pin can be used as a segment output by control
COM4/S25
25
Handling
Active
I/O
-
O
OPEN
-
O
OPEN
-
I
GND
H
I
when unused
data.
This is input pin for the external clock.
OSCI
32
Input the clock at external clock operating mode.
Furthermore, connect to GND at internal oscillator operating mode.
CE
34
CL
35
DI
36
Serial data transfer inputs. Must be connected to the controller.
CE : Chip enable
I
CL : Synchronization clock
DI : Transfer data
-
I
L
I
GND
Display off control input
•INH=low(VSS)….Display forced off
S1/P1 to S4/P4=low (VSS)
(These pins are forcibly set to the general-purpose output
port function and held at the VSS level.)
S5 to S24, S28=low(VSS)
COM1=low(VSS)
COM2/S27 to COM4/S25=low(VSS)
INH
33
Stops the internal oscillator.
GND
Inhibits external clock input.
•INH=high(VDD)…Display on
Enables the internal oscillator circuit.
(Internal oscillator operating mode)
Enables external clock input.
(External clock operating mode)
However, serial data transfer is possible when the display is forced off.
VDD
30
Power supply pin. A power voltage of 4.5 to 6.3V must be applied to this pin.
-
-
-
VSS
31
Ground pin. Must be connected to ground.
-
-
-
No.A2226-7/35
LC75843UGA
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
CE
CL
DI
0
0
1
0
0
0
1
0
D1 D2
D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 0
0
0
0
0
0
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
1
0
0
0
Display data
100 bits
1
0
Control data
10 bits
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
DD
2 bits
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
18 bits
Fixed data
4 bits
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
Control data
24 bits
0
DD
2 bits
Note: DD is the direction data
• CCB address ................................................
• D1 to D100 ..................................................
• DT0, DT1 ....................................................
• W 10 to W15, W20 to W25, W30 to W35 ...
• PF0 to PF3 ...................................................
• PS10, PS11 to PS40, PS41 ..........................
• P0 to P2 .......................................................
• FC0 to FC3 ..................................................
• DN ...............................................................
• EXF .............................................................
• OC ...............................................................
“44H”
Display data
1/1-duty to 1/4-duty drive switching control data
PWM data of the PWM output
PWM output waveform frame frequency setting control data
General-purpose output port (P1 to P4) function setting control data
Segment output port/general-purpose output port switching control data
Common/segment output waveform frame frequency setting control data
S28 pin state setting control data
External clock operating frequency setting control data
Internal oscillator operating mode/external clock operating mode
switching control data
• SC ................................................................ Segment on/off control data
• BU ............................................................... Normal mode/power-saving mode control data
No.A2226-8/35
LC75843UGA
(2) When CL is stopped at the high level
CE
CL
DI
0
0
1
0
0
0
1
0
D1 D2
D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 0
0
0
0
0
0
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
1
0
0
0
Display data
100 bits
1
0
Control data
10 bits
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
DD
2 bits
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
18 bits
Fixed data
4 bits
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
Control data
24 bits
0
DD
2 bits
Note: DD is the direction data
• CCB address ................................................
• D1 to D100 ..................................................
• DT0, DT1 ....................................................
• W 10 to W15, W20 to W25, W30 to W35 ...
• PF0 to PF3 ...................................................
• PS10, PS11 to PS40, PS41 ..........................
• P0 to P2 .......................................................
• FC0 to FC3 ..................................................
• DN ...............................................................
• EXF .............................................................
• OC ...............................................................
“44H”
Display data
1/1-duty to 1/4-duty drive switching control data
PWM data of the PWM output
PWM output waveform frame frequency setting control data
General-purpose output port (P1 to P4) function setting control data
Segment output port/general-purpose output port switching control data
Common/segment output waveform frame frequency setting control data
S28 pin state setting control data
External clock operating frequency setting control data
Internal oscillator operating mode/external clock operating mode
switching control data
• SC ................................................................ Segment on/off control data
• BU ............................................................... Normal mode/power-saving mode control data
No.A2226-9/35
LC75843UGA
2. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
DI
0
0
1
0
0
0
1
0
D1 D2
D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 0
0
0
0
0
0
0
0
0
0
0
0
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
1
0
0
Display data
78 bits
0
1
0
Control data
16 bits
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
DD
2 bits
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
18 bits
Fixed data
4 bits
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
Control data
24 bits
0
DD
2 bits
Note: DD is the direction data
• CCB address ................................................
• D1 to D78 ....................................................
• DT0, DT1 ....................................................
• W 10 to W15, W20 to W25, W30 to W35 ...
• PF0 to PF3 ...................................................
• PS10, PS11 to PS40, PS41 ..........................
• P0 to P2 .......................................................
• FC0 to FC3 ..................................................
• DN ...............................................................
• EXF .............................................................
• OC ...............................................................
“44H”
Display data
1/1-duty to 1/4-duty drive switching control data
PWM data of the PWM output
PWM output waveform frame frequency setting control data
General-purpose output port (P1 to P4) function setting control data
Segment output port/general-purpose output port switching control data
Common/segment output waveform frame frequency setting control data
S28 pin state setting control data
External clock operating frequency setting control data
Internal oscillator operating mode/external clock operating mode
switching control data
• SC ................................................................ Segment on/off control data
• BU ............................................................... Normal mode/power-saving mode control data
No.A2226-10/35
LC75843UGA
(2) When CL is stopped at the high level
CE
CL
DI
0
0
1
0
0
0
1
0
D1 D2
D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 0
0
0
0
0
0
0
0
0
0
0
0
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
1
0
0
Display data
78 bits
0
1
0
Control data
16 bits
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
DD
2 bits
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
18 bits
Fixed data
4 bits
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
Control data
24 bits
0
DD
2 bits
Note: DD is the direction data
• CCB address ................................................
• D1 to D78 ....................................................
• DT0, DT1 ....................................................
• W 10 to W15, W20 to W25, W30 to W35 ...
• PF0 to PF3 ...................................................
• PS10, PS11 to PS40, PS41 ..........................
• P0 to P2 .......................................................
• FC0 to FC3 ..................................................
• DN ...............................................................
• EXF .............................................................
• OC ...............................................................
“44H”
Display data
1/1-duty to 1/4-duty drive switching control data
PWM data of the PWM output
PWM output waveform frame frequency setting control data
General-purpose output port (P1 to P4) function setting control data
Segment output port/general-purpose output port switching control data
Common/segment output waveform frame frequency setting control data
S28 pin state setting control data
External clock operating frequency setting control data
Internal oscillator operating mode/external clock operating mode
switching control data
• SC ................................................................ Segment on/off control data
• BU ............................................................... Normal mode/power-saving mode control data
No.A2226-11/35
LC75843UGA
3. 1/2 duty
(1) When CL is stopped at the low level
CE
CL
DI
0
0
1
0
0
0
1
0
D1 D2
D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0
0
0
0
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
1
0
0
Display data
54 bits
0
1
0
Control data
8 bits
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
DD
2 bits
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
18 bits
Fixed data
4 bits
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
Control data
24 bits
0
DD
2 bits
Note: DD is the direction data
• CCB address ................................................
• D1 to D54 ....................................................
• DT0, DT1 ....................................................
• W 10 to W15, W20 to W25, W30 to W35 ...
• PF0 to PF3 ...................................................
• PS10, PS11 to PS40, PS41 ..........................
• P0 to P2 .......................................................
• FC0 to FC3 ..................................................
• DN ...............................................................
• EXF .............................................................
• OC ...............................................................
“44H”
Display data
1/1-duty to 1/4-duty drive switching control data
PWM data of the PWM output
PWM output waveform frame frequency setting control data
General-purpose output port (P1 to P4) function setting control data
Segment output port/general-purpose output port switching control data
Common/segment output waveform frame frequency setting control data
S28 pin state setting control data
External clock operating frequency setting control data
Internal oscillator operating mode/external clock operating mode
switching control data
• SC ................................................................ Segment on/off control data
• BU ............................................................... Normal mode/power-saving mode control data
No.A2226-12/35
LC75843UGA
(2) When CL is stopped at the high level
CE
CL
DI
0
0
1
0
0
0
1
0
D1 D2
D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0
0
0
0
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
1
0
0
Control data
8 bits
Display data
54 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
DD
2 bits
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
18 bits
Fixed data
4 bits
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
Control data
24 bits
0
DD
2 bits
Note: DD is the direction data
• CCB address ................................................
• D1 to D54 ....................................................
• DT0, DT1 ....................................................
• W 10 to W15, W20 to W25, W30 to W35 ...
• PF0 to PF3 ...................................................
• PS10, PS11 to PS40, PS41 ..........................
• P0 to P2 .......................................................
• FC0 to FC3 ..................................................
• DN ...............................................................
• EXF .............................................................
• OC ...............................................................
“44H”
Display data
1/1-duty to 1/4-duty drive switching control data
PWM data of the PWM output
PWM output waveform frame frequency setting control data
General-purpose output port (P1 to P4) function setting control data
Segment output port/general-purpose output port switching control data
Common/segment output waveform frame frequency setting control data
S28 pin state setting control data
External clock operating frequency setting control data
Internal oscillator operating mode/external clock operating mode
switching control data
• SC ................................................................ Segment on/off control data
• BU ............................................................... Normal mode/power-saving mode control data
No.A2226-13/35
LC75843UGA
4. 1/1 duty
(1) When CL is stopped at the low level
CE
CL
DI
0
0
1
0
0
0
1
0
D1 D2
D21 D22 D23 D24 D25 D26 D27 D28 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
1
0
0
Control data
18 bits
Display data
28 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
DD
2 bits
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
18 bits
Fixed data
4 bits
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
Control data
24 bits
0
DD
2 bits
Note: DD is the direction data
• CCB address ................................................
• D1 to D28 ....................................................
• DT0, DT1 ....................................................
• W 10 to W15, W20 to W25, W30 to W35 ...
• PF0 to PF3 ...................................................
• PS10, PS11 to PS40, PS41 ..........................
• P0 to P2 .......................................................
• FC0 to FC3 ..................................................
• DN ...............................................................
• EXF .............................................................
• OC ...............................................................
“44H”
Display data
1/1-duty to 1/4-duty drive switching control data
PWM data of the PWM output
PWM output waveform frame frequency setting control data
General-purpose output port (P1 to P4) function setting control data
Segment output port/general-purpose output port switching control data
Common/segment output waveform frame frequency setting control data
S28 pin state setting control data
External clock operating frequency setting control data
Internal oscillator operating mode/external clock operating mode
switching control data
• SC ................................................................ Segment on/off control data
• BU ............................................................... Normal mode/power-saving mode control data
No.A2226-14/35
LC75843UGA
(2) When CL is stopped at the high level
CE
CL
DI
0
0
1
0
0
0
1
0
D1 D2
D21 D22 D23 D24 D25 D26 D27 D28 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
0
0
1
0
0
Control data
18 bits
Display data
28 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
DD
2 bits
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
18 bits
Fixed data
4 bits
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
Control data
24 bits
0
DD
2 bits
Note: DD is the direction data
• CCB address ................................................
• D1 to D28 ....................................................
• DT0, DT1 ....................................................
• W 10 to W15, W20 to W25, W30 to W35 ...
• PF0 to PF3 ...................................................
• PS10, PS11 to PS40, PS41 ..........................
• P0 to P2 .......................................................
• FC0 to FC3 ..................................................
• DN ...............................................................
• EXF .............................................................
• OC ...............................................................
“44H”
Display data
1/1-duty to 1/4-duty drive switching control data
PWM data of the PWM output
PWM output waveform frame frequency setting control data
General-purpose output port (P1 to P4) function setting control data
Segment output port/general-purpose output port switching control data
Common/segment output waveform frame frequency setting control data
S28 pin state setting control data
External clock operating frequency setting control data
Internal oscillator operating mode/external clock operating mode
switching control data
• SC ................................................................ Segment on/off control data
• BU ............................................................... Normal mode/power-saving mode control data
No.A2226-15/35
LC75843UGA
Serial Data Transfer Example
1. 1/4 duty
All 160 bits of serial data must be sent.
8 bits
0
0
1
0
0
112 bits
0
1
0
D1 D2
D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 0
0
0
0
0
0
0
0 DT0 DT1 0
1
0
0 DT0 DT1 0
1
0
0 DT0 DT1 0
1
0
0 DT0 DT1 0
1
B0 B1 B2 B3 A0 A1 A2 A3
8 bits
0
0
1
0
0
48 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
0
2. 1/3 duty
All 144 bits of serial data must be sent.
8 bits
0
0
1
0
0
96 bits
0
1
0
D1 D2
D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
8 bits
0
0
1
0
0
48 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
0
3. 1/2 duty
All 112 bits of serial data must be sent.
8 bits
0
0
1
0
0
64 bits
0
1
0
D1 D2
D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
8 bits
0
0
1
0
0
48 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
0
4. 1/1 duty
All 96 bits of serial data must be sent.
8 bits
0
0
1
0
0
48 bits
0
1
0
D1 D2
D21 D22 D23 D24 D25 D26 D27 D28 0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
8 bits
0
0
1
0
0
48 bits
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU 1
0
No.A2226-16/35
LC75843UGA
Control Data Functions
(1) DT0, DT1    LCD drive scheme ( 1/1-duty to 1/4-duty drive ) switching control data.
These control data bits select 1/4-duty 1/3 bias drive, 1/3-duty 1/3 bias drive, 1/2-duty 1/2 bias drive, or 1/1-duty
drive.
Pin state
DT0
DT1
Drive scheme
0
0
1
0
0
1
COM2/S27
COM3/S26
COM4/S25
1/4-duty 1/3-bias drive
COM2
COM3
COM4
1/3-duty 1/3-bias drive
COM2
COM3
S25
1
1/2-duty 1/2-bias drive
COM2
S26
S25
1
static (1/1-duty drive)
S27
S26
S25
Note: COM2 to COM4: Common output , S27 to S25: Segment output
(2) PF0 to PF3    PWM output waveform frame frequency setting control data
These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output
function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency
is set the fCK2=38[KHz] typ (EXF=“1”) in external clock operating mode (OC=“1”), these control data bits become
invalid.
Control data
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
PF0
PF1
PF2
PF3
External clock operating mode
(The control data OC is 0,
(The control data OC is 1,
fosc=300[kHz]typ)
and EXF is 0, fCK1=300[kHz]typ)
0
0
0
0
fosc/1536
fCK1/1536
1
0
0
0
fosc/1408
fCK1/1408
0
1
0
0
fosc/1280
fCK1/1280
1
1
0
0
fosc/1152
fCK1/1152
0
0
1
0
fosc/1024
fCK1/1024
1
0
1
0
fosc/896
fCK1/896
0
1
1
0
fosc/768
fCK1/768
1
1
1
0
fosc/640
fCK1/640
0
0
0
1
fosc/512
fCK1/512
1
0
0
1
fosc/384
fCK1/384
0
1
0
1
fosc/256
fCK1/256
Note: When is setting (PF0, PF1, PF2, PF3)=(1, 1, 0, 1) and (X, X, 1, 1), the frame frequency is same as
frame frequency at the time of the (PF0, PF1, PF2, PF3)=(1, 0, 1, 0) setting (fosc/896, fCK1/896).
X : don’t care
No.A2226-17/35
LC75843UGA
(3) PS10, PS11 to PS40, PS41    General-purpose output port (P1 to P4) function setting control data
These control data bits set the general-purpose output function (High or low level output), clock output function or
PWM output function of the P1 output pin, and the general-purpose output function (High or low level output) or
PWM output function of the P2 to P4 output pins.
However, be careful of being unable to set a PWM output function when the external clock operating frequency is
set the fCK2=38[kHz] typ (EXF=“1”) in external clock operating mode (OC=“1”).
PS10
PS11
General-purpose output port (P1) function
0
0
General-purpose output function (High or low level output)
1
0
Clock output function (clock frequency : fosc/2, fCK/2)
0
1
Clock output function (clock frequency : fosc/8, fCK/8)
1
1
PWM output function (ch1) (Support for PWM data W10 to W15)
PS20
PS21
General-purpose output port (P2) function
0
0
General-purpose output function (High or low level output)
1
0
PWM output function (ch1) (Support for PWM data W10 to W15)
0
1
PWM output function (ch2) (Support for PWM data W20 to W25)
1
1
PWM output function (ch3) (Support for PWM data W30 to W35)
PS30
PS31
General-purpose output port (P3) function
0
0
General-purpose output function (High or low level output)
1
0
PWM output function (ch1) (Support for PWM data W10 to W15)
0
1
PWM output function (ch2) (Support for PWM data W20 to W25)
1
1
PWM output function (ch3) (Support for PWM data W30 to W35)
PS40
PS41
General-purpose output port (P4) function
0
0
General-purpose output function (High or low level output)
1
0
PWM output function (ch1) (Support for PWM data W10 to W15)
0
1
PWM output function (ch2) (Support for PWM data W20 to W25)
1
1
PWM output function (ch3) (Support for PWM data W30 to W35)
(4) P0 to P2    Segment output port/general-purpose output port switching control data.
These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S4/P4
output pins.
Control data
Output pin state
P0
P1
P2
S1/P1
S2/P2
S3/P3
S4/P4
0
0
0
S1
S2
S3
S4
0
0
1
P1
S2
S3
S4
0
1
0
P1
P2
S3
S4
0
1
1
P1
P2
P3
S4
1
0
0
P1
P2
P3
P4
Note: Sn(n=1 to 4): Segment output ports
Pn(n=1 to 4): General-purpose output ports
Note: When are setting (P0, P1, P2)=(1, 0, 1), (1, 1, 0), and (1, 1, 1), the all P1/S1 to P4/S4 output pins selects the
segment output port.
The table below lists the correspondence between the display data and the output pins when these pins are selected
to be general-purpose output ports.
Correspondence display data
Output pin
1/4 duty
1/3 duty
1/2 duty
1/1 duty
S1/P1
D1
D1
D1
D1
S2/P2
D5
D4
D3
D2
S3/P3
D9
D7
D5
D3
S4/P4
D13
D10
D7
D4
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port, the S4/P4 output pin will output a high level when the display data D13 is 1, and will output a low level when
D13 is 0.
No.A2226-18/35
LC75843UGA
(5) FC0 to FC3    Common/segment output waveform frame frequency control data
These control data bits set the frame frequency of the common and segment output waveforms.
Control data
FC0
FC1
FC2
Frame frequency fo[Hz]
FC3
Internal oscillator
External clock
External clock
operating mode
operating mode
operating mode
(The control data OC is 0,
(The control data OC is 1,
(The control data OC is 1,
fosc=300[kHz]typ)
and EXF is 0,
and EXF is 1,
fCK1=300[kHz]typ)
fCK2=38[kHz]typ)
0
0
0
0
fosc/6144
fCK1/6144
fCK2/768
0
0
0
1
fosc/5376
fCK1/5376
fCK2/672
0
0
1
0
fosc/4608
fCK1/4608
fCK2/576
0
0
1
1
fosc/3840
fCK1/3840
fCK2/480
0
1
0
0
fosc/3456
fCK1/3456
fCK2/432
0
1
0
1
fosc/3072
fCK1/3072
fCK2/384
0
1
1
0
fosc/2688
fCK1/2688
fCK2/336
0
1
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
0
fosc/2112
fCK1/2112
fCK2/264
1
0
0
1
fosc/1920
fCK1/1920
fCK2/240
1
0
1
0
fosc/1728
fCK1/1728
fCK2/216
1
0
1
1
fosc/1536
fCK1/1536
fCK2/192
1
1
0
0
fosc/1344
fCK1/1344
fCK2/168
1
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
1
0
fosc/960
fCK1/960
fCK2/120
1
1
1
1
fosc/768
fCK1/768
fCK2/96
(6) DN    S28 pin state setting control data
This control data bit sets state of the S28 pin.
Number of display segments
Pin state
DN
1/4 duty
1/3 duty
1/2 duty
1/1 duty
S28
0
Up to 96 segments
Up to 75 segments
Up to 52 segments
Up to 27 segments
“L” (VSS)
1
Up to100 segments
Up to 78 segments
Up to 54 segments
Up to 28 segments
S28
(7) EXF    External clock operating frequency setting control data
This control data sets the operating frequency of the external clock which input into the OSCI pin, when the external
clock operating mode (OC=“1”) is set. However, this control data is effective only when external clock operating
mode (OC=“1”) is set.
EXF
External clock operating frequency fCK[KHz]
0
fCK1=300[kHz]typ
1
fCK2=38[kHz]typ
(8) OC    Internal oscillator operating mode/external clock operating mode switching control data.
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
Input pin (OSCI) state
OC
Fundamental clock operating mode
0
Internal oscillator operating mode
Connect to GND
1
External clock operating mode
Input the clock from the outside
(9) SC    Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
on
1
off
Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off
waveforms from the segment output pins.
No.A2226-19/35
LC75843UGA
(10) BU    Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
0
Mode
Normal mode
Power saving mode
In this mode, the internal oscillator circuit stops oscillation if the IC is in the internal oscillator operating mode(OC=0) and
the IC stops receiving external clock signals if the IC is in the external clock operating mode(OC=1). The common and
1
segment output pins go to the VSS level.
However, the S1/P1 to S4/P4 output pins can be used as general-purpose output ports under the control of the data bits
P0 to P2. (The general-purpose output port P1 to P4 can not be used as clock output or PWM output).
No.A2226-20/35
LC75843UGA
(11) W10 to W15, W20 to W25, W30 to W35    PWM data of the PWM output
These control data bits set the pulse width of the PWM output P1 to P4. However, when the PWM output function
isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the
fCK2=38[kHz]typ (EXF=“1”) in external clock operating mode (OC=“1”), these control data bits become invalid.
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
1
1
0
1
Pulse width of
Pulse width of
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
(1/64)Tp
0
0
0
0
0
1
(33/64)Tp
(2/64)Tp
1
0
0
0
0
1
(34/64)Tp
0
(3/64)Tp
0
1
0
0
0
1
(35/64)Tp
0
0
(4/64)Tp
1
1
0
0
0
1
(36/64)Tp
0
0
(5/64)Tp
0
0
1
0
0
1
(37/64)Tp
0
0
0
(6/64)Tp
1
0
1
0
0
1
(38/64)Tp
1
0
0
0
(7/64)Tp
0
1
1
0
0
1
(39/64)Tp
1
0
0
0
(8/64)Tp
1
1
1
0
0
1
(40/64)Tp
0
0
1
0
0
(9/64)Tp
0
0
0
1
0
1
(41/64)Tp
0
0
1
0
0
(10/64)Tp
1
0
0
1
0
1
(42/64)Tp
0
1
0
1
0
0
(11/64)Tp
0
1
0
1
0
1
(43/64)Tp
1
1
0
1
0
0
(12/64)Tp
1
1
0
1
0
1
(44/64)Tp
0
0
1
1
0
0
(13/64)Tp
0
0
1
1
0
1
(45/64)Tp
1
0
1
1
0
0
(14/64)Tp
1
0
1
1
0
1
(46/64)Tp
0
1
1
1
0
0
(15/64)Tp
0
1
1
1
0
1
(47/64)Tp
1
1
1
1
0
0
(16/64)Tp
1
1
1
1
0
1
(48/64)Tp
0
0
0
0
1
0
(17/64)Tp
0
0
0
0
1
1
(49/64)Tp
1
0
0
0
1
0
(18/64)Tp
1
0
0
0
1
1
(50/64)Tp
0
1
0
0
1
0
(19/64)Tp
0
1
0
0
1
1
(51/64)Tp
1
1
0
0
1
0
(20/64)Tp
1
1
0
0
1
1
(52/64)Tp
0
0
1
0
1
0
(21/64)Tp
0
0
1
0
1
1
(53/64)Tp
1
0
1
0
1
0
(22/64)Tp
1
0
1
0
1
1
(54/64)Tp
0
1
1
0
1
0
(23/64)Tp
0
1
1
0
1
1
(55/64)Tp
1
1
1
0
1
0
(24/64)Tp
1
1
1
0
1
1
(56/64)Tp
0
0
0
1
1
0
(25/64)Tp
0
0
0
1
1
1
(57/64)Tp
1
0
0
1
1
0
(26/64)Tp
1
0
0
1
1
1
(58/64)Tp
0
1
0
1
1
0
(27/64)Tp
0
1
0
1
1
1
(59/64)Tp
1
1
0
1
1
0
(28/64)Tp
1
1
0
1
1
1
(60/64)Tp
0
0
1
1
1
0
(29/64)Tp
0
0
1
1
1
1
(61/64)Tp
1
0
1
1
1
0
(30/64)Tp
1
0
1
1
1
1
(62/64)Tp
0
1
1
1
1
0
(31/64)Tp
0
1
1
1
1
1
(63/64)Tp
1
1
1
1
1
0
(32/64)Tp
1
1
1
1
1
1
(64/64)Tp
PWM output
Note : W10 to W15    PWM data of the PWM output (Ch1)
W20 to W25    PWM data of the PWM output (Ch2)
W30 to W35    PWM data of the PWM output (Ch3)
PWM output
n=1 to 3
Tp=
1
fp
No.A2226-21/35
LC75843UGA
Display Data and Output Pin Correspondence (1/4 Duty)
Output pin
COM1
COM2
COM3
COM4
Output pin
COM1
COM2
COM3
COM4
S1/P1
D1
D2
D3
D4
S14
D53
D54
D55
D56
S2/P2
D5
D6
D7
D8
S15
D57
D58
D59
D60
D64
S3/P3
D9
D10
D11
D12
S16
D61
D62
D63
S4/P4
D13
D14
D15
D16
S17
D65
D66
D67
D68
S5
D17
D18
D19
D20
S18
D69
D70
D71
D72
S6
D21
D22
D23
D24
S19
D73
D74
D75
D76
S7
D25
D26
D27
D28
S20
D77
D78
D79
D80
S8
D29
D30
D31
D32
S21
D81
D82
D83
D84
S9
D33
D34
D35
D36
S22
D85
D86
D87
D88
S10
D37
D38
D39
D40
S23
D89
D90
D91
D92
S11
D41
D42
D43
D44
S24
D93
D94
D95
D96
S12
D45
D46
D47
D48
S28
D97
D98
D99
D100
S13
D49
D50
D51
D52
Note: This table assumes that pins S1/P1 to S4/P4 are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D81
D82
D83
D84
0
0
0
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
0
0
0
1
The LCD segment corresponding to COM4 is on.
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segments corresponding to COM3 and COM4 are on.
0
1
0
0
The LCD segment corresponding to COM2 is on.
0
1
0
1
The LCD segments corresponding to COM2 and COM4 are on.
0
1
1
0
The LCD segments corresponding to COM2 and COM3 are on.
0
1
1
1
The LCD segments corresponding to COM2, COM3, and COM4 are on.
1
0
0
0
The LCD segment corresponding to COM1 is on.
1
0
0
1
The LCD segments corresponding to COM1 and COM4 are on.
1
0
1
0
The LCD segments corresponding to COM1 and COM3 are on.
1
0
1
1
The LCD segments corresponding to COM1, COM3, and COM4 are on.
1
1
0
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
0
1
The LCD segments corresponding to COM1, COM2, and COM4 are on.
1
1
1
0
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
1
1
1
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
No.A2226-22/35
LC75843UGA
Display Data and Output Pin Correspondence (1/3 Duty)
Output pin
COM1
COM2
COM3
Output pin
COM1
COM2
COM3
S1/P1
D1
D2
D3
S14
D40
D41
D42
S2/P2
D4
D5
D6
S15
D43
D44
D45
S3/P3
D7
D8
D9
S16
D46
D47
D48
S4/P4
D10
D11
D12
S17
D49
D50
D51
S5
D13
D14
D15
S18
D52
D53
D54
S6
D16
D17
D18
S19
D55
D56
D57
S7
D19
D20
D21
S20
D58
D59
D60
S8
D22
D23
D24
S21
D61
D62
D63
S9
D25
D26
D27
S22
D64
D65
D66
S10
D28
D29
D30
S23
D67
D68
D69
S11
D31
D32
D33
S24
D70
D71
D72
S12
D34
D35
D36
COM4/S25
D73
D74
D75
S13
D37
D38
D39
S28
D76
D77
D78
Note: This table assumes that pins S1/P1 to S4/P4, and COM4/S25 are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D61
D62
D63
0
0
0
The LCD segments corresponding to COM1, COM2 and COM3 are off.
0
0
1
The LCD segment corresponding to COM3 is on.
0
1
0
The LCD segment corresponding to COM2 is on.
0
1
1
The LCD segments corresponding to COM2 and COM3 are on.
1
0
0
The LCD segment corresponding to COM1 is on.
1
0
1
The LCD segments corresponding to COM1 and COM3 are on.
1
1
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
1
The LCD segments corresponding to COM1, COM2, and COM3 are on.
Display Data and Output Pin Correspondence (1/2 Duty)
Output pin
COM1
COM2
Output pin
COM1
COM2
S1/P1
D1
D2
S15
D29
D30
S2/P2
D3
D4
S16
D31
D32
S3/P3
D5
D6
S17
D33
D34
S4/P4
D7
D8
S18
D35
D36
S5
D9
D10
S19
D37
D38
S6
D11
D12
S20
D39
D40
S7
D13
D14
S21
D41
D42
S8
D15
D16
S22
D43
D44
S9
D17
D18
S23
D45
D46
S10
D19
D20
S24
D47
D48
S11
D21
D22
COM4/S25
D49
D50
S12
D23
D24
COM3/S26
D51
D52
S13
D25
D26
S28
D53
D54
S14
D27
D28
Note: This table assumes that pins S1/P1 to S4/P4, COM4/S25, and COM3/S26 are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D41
D42
0
0
The LCD segments corresponding to COM1 and COM2 are off.
0
1
The LCD segment corresponding to COM2 is on.
1
0
The LCD segment corresponding to COM1 is on.
1
1
The LCD segments corresponding to COM1 and COM2 are on.
No.A2226-23/35
LC75843UGA
Display Data and Output Pin Correspondence (1/1 Duty)
Output pin
COM1
Output pin
COM1
S1/P1
D1
S15
D15
S2/P2
D2
S16
D16
S3/P3
D3
S17
D17
S4/P4
D4
S18
D18
S5
D5
S19
D19
S6
D6
S20
D20
S7
D7
S21
D21
S8
D8
S22
D22
S9
D9
S23
D23
S10
D10
S24
D24
S11
D11
COM4/S25
D25
S12
D12
COM3/S26
D26
S13
D13
COM2/S27
D27
S14
D14
S28
D28
Note: This table assumes that pins S1/P1 to S4/P4, COM4/S25, COM3/S26, and COM2/S27 are configured for
segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D21
0
The LCD segment corresponding to COM1 is off.
1
The LCD segment corresponding to COM1 is on.
No.A2226-24/35
LC75843UGA
Output waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
COM1
COM2
COM3
COM4
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3
are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are on.
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
VDD
2/3VDD
1/3VDD
0V
No.A2226-25/35
LC75843UGA
Output waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]
COM1
VDD
2/3VDD
1/3VDD
0V
VDD
COM2
2/3VDD
1/3VDD
0V
COM3
VDD
2/3VDD
1/3VDD
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are off.
VDD
2/3VDD
1/3VDD
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VDD
2/3VDD
1/3VDD
0V
VDD
LCD driver output when only LCD segments
corresponding to COM2 are on.
2/3VDD
1/3VDD
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VDD
2/3VDD
1/3VDD
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VDD
2/3VDD
1/3VDD
0V
VDD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
2/3VDD
1/3VDD
0V
VDD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
2/3VDD
1/3VDD
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are on.
VDD
2/3VDD
1/3VDD
0V
No.A2226-26/35
LC75843UGA
Output waveforms (1/2-Duty 1/2-Bias Drive Scheme)
fo[Hz]
VDD
1/2VDD
COM1
0V
VDD
1/2VDD
COM2
0V
VDD
1/2VDD
LCD driver output when all LCD segments
corresponding to COM1 and COM2 are off.
0V
VDD
1/2VDD
LCD driver output when only LCD segments
corresponding to COM1 are on.
0V
VDD
1/2VDD
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
VDD
1/2VDD
LCD driver output when all LCD segments
corresponding to COM1 and COM2 are on.
0V
Output waveforms (1/1-Duty Drive Scheme)
fo[Hz]
VDD
COM1
0V
VDD
LCD driver output when LCD segments
corresponding to COM1 are off.
0V
VDD
LCD driver output when LCD segments
corresponding to COM1 are on.
0V
Control data
FC0
FC1
FC2
Frame frequency fo[Hz]
FC3
Internal oscillator operating mode
External clock operating mode
(The control data OC is 0,
(The control data OC is 1,
External clock operating mode
(The control data OC is 1,
fosc=300[kHz]typ)
and EXF is 0, fCK1=300[kHz]typ)
and EXF is 1, fCK2=38[kHz]typ)
0
0
0
0
fosc/6144
fCK1/6144
fCK2/768
0
0
0
1
fosc/5376
fCK1/5376
fCK2/672
0
0
1
0
fosc/4608
fCK1/4608
fCK2/576
0
0
1
1
fosc/3840
fCK1/3840
fCK2/480
0
1
0
0
fosc/3456
fCK1/3456
fCK2/432
0
1
0
1
fosc/3072
fCK1/3072
fCK2/384
0
1
1
0
fosc/2688
fCK1/2688
fCK2/336
0
1
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
0
fosc/2112
fCK1/2112
fCK2/264
1
0
0
1
fosc/1920
fCK1/1920
fCK2/240
1
0
1
0
fosc/1728
fCK1/1728
fCK2/216
1
0
1
1
fosc/1536
fCK1/1536
fCK2/192
1
1
0
0
fosc/1344
fCK1/1344
fCK2/168
1
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
1
0
fosc/960
fCK1/960
fCK2/120
1
1
1
1
fosc/768
fCK1/768
fCK2/96
No.A2226-27/35
LC75843UGA
PWM output waveforms
VDD
P1 to P4
(PWM output Ch1)
(56/64)Tp
VSS
(56/64)Tp
VDD
(1)
P2 to P4
(PWM output Ch2)
(48/64)Tp
VSS
(48/64)Tp
VDD
P2 to P4
(PWM output Ch3)
(40/64)Tp
VSS
(40/64)Tp
VDD
P1 to P4
(PWM output Ch1)
(8/64)Tp
VSS
(8/64)Tp
VDD
(2)
P2 to P4
(PWM output Ch2)
VSS
(16/64)Tp
(16/64)Tp
VDD
P2 to P4
(PWM output Ch3)
(24/64)Tp
VSS
(24/64)Tp
VDD
P1 to P4
(PWM output Ch1)
(32/64)Tp
VSS
(32/64)Tp
VDD
(3)
P2 to P4
(PWM output Ch2)
(32/64)Tp
VSS
(32/64)Tp
VDD
P2 to P4
(PWM output Ch3)
(32/64)Tp
VSS
(32/64)Tp
Tp
Tp=
Tp
1
fp
Control data
PWM output
W10
W11
W12
W13
W14
W15
W20
W21
W22
W23
W24
W25
W30
W31
W32
W33
W34
W35
waveforms
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
0
1
(1)
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
0
1
0
(2)
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
(3)
Control data
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
PF0
PF1
PF2
PF3
External clock operating mode
(The control data OC is 0,
(The control data OC is 1,
fosc=300[kHz]typ)
and EXF is 0, fCK1=300[kHz]typ)
0
0
0
0
fosc/1536
fCK1/1536
1
0
0
0
fosc/1408
fCK1/1408
0
1
0
0
fosc/1280
fCK1/1280
1
1
0
0
fosc/1152
fCK1/1152
0
0
1
0
fosc/1024
fCK1/1024
1
0
1
0
fosc/896
fCK1/896
0
1
1
0
fosc/768
fCK1/768
1
1
1
0
fosc/640
fCK1/640
0
0
0
1
fosc/512
fCK1/512
1
0
0
1
fosc/384
fCK1/384
0
1
0
1
fosc/256
fCK1/256
Note: When is setting (PF0, PF1, PF2, PF3)=(1, 1, 0, 1) and (X, X, 1, 1) the frame frequency is same as
frame frequency at the time of the (PF0, PF1, PF2, PF3)=(1, 0, 1, 0) setting (fosc/896, fCK1/896).
X:don’t care
No.A2226-28/35
LC75843UGA
Clock output waveforms
Control data
P1
Tc/2
1
Tc= fc
Tc
Clock frequency of clock output P1
PS10
PS11
fc(=1/Tc)[Hz]
1
0
Clock output function (fosc/2, fCK/2)
0
1
Clock output function (fosc/8, fCK/8)
No.A2226-29/35
LC75843UGA
Display Control and the INH Pin
Since the LSI internal data (1/4 duty : the display data D1 to D100 and the control data, 1/3 duty : the display data D1 to
D78 and the control data, 1/2 duty : the display data D1 to D54 and the control data, 1/1 duty : the display data D1 to
D28 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same
time as power is applied to turn off the display (This sets the S1/P1 to S4/P4, S5 to S24, COM4/S25,
COM3/S26,COM2/S27, COM1, and S28 pins to the VSS level.) and during this period send serial data from the
controller. The controller should then set the INH pin high after the data transfer has completed . This procedure
prevents meaningless display at power on. (See Figure 4, Figure 5, Figure 6, Figure 7.)
(1)1/4 duty
t2
~
~
t1
~
~
VDD
INH
VIL1
VIL1
~
~
tc
CE
W10 to W15, W20 to W25,
W30 to W35, PF0 to PF3,
PS10, PS11 to PS40, PS41,
P0 to P2, FC0 to FC3,
DN, EXF, OC, SC, BU
Undefined
Defined
Undefined
~
~
Defined
~
~
Internal
data
Undefined
Undefined
~
~
Internal
(D1 to D100, DT0, DT1)
data
~
~
Display data and
control data transferred
Note : t1>1ms
t2>0
tc … 10s min
[Figure 4]
(2)1/3 duty
t2
~
~
t1
~
~
VDD
INH
VIL1
VIL1
~
~
tc
CE
W10 to W15, W20 to W25,
W30 to W35, PF0 to PF3,
PS10, PS11 to PS40, PS41,
P0 to P2, FC0 to FC3,
DN, EXF, OC, SC, BU
Undefined
Defined
Undefined
~
~
Defined
~
~
Internal
data
Undefined
Undefined
~
~
Internal
(D1 to D78, DT0, DT1)
data
~
~
Display data and
control data transferred
[Figure 5]
Note : t1>1ms
t2>0
tc … 10s min
No.A2226-30/35
LC75843UGA
(3)1/2 duty
t2
~
~
t1
~
~
VDD
INH
VIL1
CE
VIL1
~
~
tc
W10 to W15, W20 to W25,
W30 to W35, PF0 to PF3,
PS10, PS11 to PS40, PS41,
P0 to P2, FC0 to FC3,
DN, EXF, OC, SC, BU
Undefined
Defined
Undefined
~
~
Defined
~
~
Internal
data
Undefined
Undefined
~
~
Internal
(D1 to D54, DT0, DT1)
data
~
~
Display data and
control data transferred
Note : t1>1ms
t2>0
tc … 10s min
[Figure 6]
(4)1/1 duty
t2
~
~
t1
~
~
VDD
INH
VIL1
CE
VIL1
~
~
tc
W10 to W15, W20 to W25,
W30 to W35, PF0 to PF3,
PS10, PS11 to PS40, PS41,
P0 to P2, FC0 to FC3,
DN, EXF, OC, SC, BU
Undefined
Defined
Undefined
~
~
Defined
~
~
Internal
data
Undefined
Undefined
~
~
Internal
(D1 to D28, DT0, DT1)
data
~
~
Display data and
control data transferred
[Figure 7]
Note : t1>1ms
t2>0
tc … 10s min
No.A2226-31/35
LC75843UGA
OSCI pin Peripheral Circuit
(1) Internal oscillator operating mode (Control data OC =“0”)
Connect OSCI pin to GND if internal oscillator operating mode is selected.
OSCI
(2) External clock operating mode (Control data OC =“1”)
Input the external clock to OSCI pin if external clock operating mode is selected.
External clock output pin
OSCI
External oscillator
P1 to P4 pin Peripheral Circuit
It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using the PWM output
P1 to P4
+5V
LED
P1 to P4
No.A2226-32/35
LC75843UGA
Sample Applications Circuit 1
1/4 Duty, 1/3 Bias
(P1)
(P2)
(P3)
(P4)
+5V
VDD
General-purpose
output ports
Used for functions
such as backlight
control
COM1
S27/COM2
VSS
LCD panel(up to 100 segments)
S26/COM3
S25/COM4
P1/S1
P2/S2
P3/S3
P4/S4
S5
External clock input
OSCI *3
INH
CE
From the
controller
CL
S23
S24
DI
S28
*2
*2. The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*3. External clock input pin OSCI is supported 3.3V or 5V. Connect to GND at internal oscillator operating
mode, and input the external clock to OSCI pin at external clock operating mode.
(See “OSCI pin peripheral circuit”)
Sample Application Circuit 2
1/3 Duty, 1/3 Bias
(P1)
(P2)
(P3)
(P4)
+5V
VDD
General-purpose
output ports
Used for functions
such as backlight
control
COM1
VSS
S26/COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
External clock input
From the
controller
OSCI *3
INH
S23
CE
CL
S24
DI
*2
LCD panel(up to 78 segments)
S27/COM2
COM4/S25
S28
*2. The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*3. External clock input pin OSCI is supported 3.3V or 5V. Connect to GND at internal oscillator operating
mode, and input the external clock to OSCI pin at external clock operating mode.
(See “OSCI pin peripheral circuit”)
No.A2226-33/35
LC75843UGA
Sample Applications Circuit 3
(P1)
1/2 Duty, 1/2 Bias
(P2)
(P3)
+5V
VDD
COM1
VSS
S27/COM2
P1/S1
P2/S2
P3/S3
P4/S4
S5
External clock input
OSCI *3
S23
S24
INH
From the
controller
CE
*2
Used for functions
such as backlight
control
LCD panel(up to 54 segments)
(P4)
General-purpose
output ports
COM4/S25
CL
COM3/S26
DI
S28
*2. The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*3. External clock input pin OSCI is supported 3.3V or 5V. Connect to GND at internal oscillator operating
mode, and input the external clock to OSCI pin at external clock operating mode.
(See “OSCI pin peripheral circuit”)
(P2)
Static (1/1 Duty)
(P3)
(P4)
+5V
VDD
COM1
P1/S1
VSS
P2/S2
P3/S3
P4/S4
S5
External clock input
S23
OSCI *3
S24
COM4/S25
INH
From the
controller
CE
*2
General-purpose
output ports
Used for functions
such as backlight
control
LCD panel(up to 28 segments)
(P1)
Sample Application Circuit 4
COM3/S26
CL
COM2/S27
DI
S28
*2. The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*3. External clock input pin OSCI is supported 3.3V or 5V. Connect to GND at internal oscillator operating
mode, and input the external clock to OSCI pin at external clock operating mode.
(See “OSCI pin peripheral circuit”)
No.A2226-34/35
LC75843UGA
ORDERING INFORMATION
Device
LC75843UGA-AH
Package
TSSOP36(275mil)
(Pb-Free / Halogen free)
Shipping (Qty / Packing)
1000 / Tape & Reel
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PS No.A2226-35/35
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