ENA1391 D

Ordering number : ENA1391
LC75886PW
CMOS IC
1/4 and 1/3-Duty LCD Display
Driver with Key Input Function
http://onsemi.com
Overview
The LC75886PW is 1/4 duty and 1/3 duty LCD display driver that can directly drive up to 224 segments and can
control up to 5 general-purpose output ports. This product also incorporates a key scan circuit that accepts input from
up to 30 keys to reduce printed circuit board wiring.
Features
• Key input function for up to 30 keys (A key scan is performed only when a key is pressed.)
• 1/4 duty 1/3 bias and 1/3 duty 1/3 bias drive schemes can be controlled from serial data.
• Capable of driving up to 224 segments using 1/4 duty and up to 171 segments using 1/3 duty.
• Switching between key scan output and segment output can be controlled from serial data.
• The key scan operation enabled/disabled state can be controlled from serial data.
• Switching between segment output port and general-purpose output port can be controlled from serial data.
• Switching between general-purpose output port, clock output port, and segment output port can be controlled from
serial data. (Up to 5 general-purpose output ports and up to one clock output port)
• Serial data I/O supports CCB format communication with the system controller. (Support 3.3V and 5V operation)
• Sleep mode and all segments off functions that are controlled from serial data.
• The frame frequency of the common and segment output waveforms can be controlled from serial data.
• Switching between RC oscillator operating mode and external clock operationg mode can be controlled from serial
data.
• Direct display of display data without the use of a decoder provides high generality.
• Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays.
• RES pin provided for forcibly initializing the IC internal circuits.
•
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
•
CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
July, 2013
51309HKIM 20081208-S00009 No.A1391-1/36
LC75886PW
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Maximum supply voltage
Input voltage
Symbol
Conditions
Ratings
Unit
VDD max
VDD
-0.3 to +7.0
VIN1
CE, CL, DI, RES
-0.3 to +7.0
VIN2
OSC, TEST, VDD1, VDD2, KI1 to KI5
-0.3 to VDD+0.3
V
V
VOUT1
DO
VOUT2
OSC, S1 to S57, COM1 to COM4, KS1 to KS6, P1 to P5
IOUT1
S1 to S57
IOUT2
COM1 to COM4
3
IOUT3
KS1 to KS6
1
IOUT4
P1 to P5
5
Allowable power dissipation
Pd max
Ta=85°C
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-55 to +125
°C
Output voltage
Output current
-0.3 to +7.0
-0.3 to VDD+0.3
300
200
V
μA
mA
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V
Ratings
Parameter
Symbol
Conditions
min
typ
Unit
max
Supply voltage
VDD
VDD
Input voltage
VDD1
VDD1
2/3VDD
VDD
VDD2
VDD2
1/3VDD
VDD
VIH1
CE, CL, DI, RES
0.4VDD
6.0
VIH2
KI1 to KI5
0.6VDD
VDD
VIH3
OSC: External clock operating mode
0.4VDD
VDD
VIL1
CE, CL, DI, RES
0
0.2VDD
VIL2
KI1 to KI5
0
0.2VDD
VIL3
OSC: External clock operating mode
0
0.2VDD
ROSC
OSC: RC oscillation operating mode
COSC
OSC: RC oscillation operating mode
Input high level voltage
Input low level voltage
Recommended external
4.5
resistor for RC oscillation
Recommended external
capacitor for RC oscillation
Guaranteed range of RC oscillation
fOSC
OSC: RC oscillation operating mode
External clock operating frequency
fCK
OSC: External clock operating mode
[Figure4]
External clock duty cycle
DCK
OSC: External clock operating mode
[Figure4]
6.0
V
V
V
V
39
kΩ
1000
pF
19
38
76
kHz
10
38
76
kHz
30
50
70
%
Data setup time
tds
CL, DI
[Figure2], [Figure3]
Data hold time
tdh
CL, DI
[Figure2], [Figure3]
160
ns
CE wait time
tcp
CE, CL
[Figure2], [Figure3]
160
ns
CE setup time
tcs
CE, CL
[Figure2], [Figure3]
160
ns
CE hold time
tch
CE, CL
[Figure2], [Figure3]
160
ns
High level clock pulse width
tφH
CL
[Figure2], [Figure3]
160
ns
Low level clock pulse width
tφL
CL
[Figure2], [Figure3]
160
ns
Rise time
tr
CE, CL, DI
[Figure2], [Figure3]
160
ns
Fall time
tf
CE, CL, DI
[Figure2], [Figure3]
160
ns
DO output deley time
tdc
DO RPU=4.7kΩ CL=10pF *1
160
ns
[Figure2], [Figure3]
DO rise time
tdr
DO RPU=4.7kΩ CL=10pF *1
[Figure2], [Figure3]
1.5
μs
1.5
μs
Note: *1 Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor
RPU and the load capacitance CL.
No.A1391-2/36
LC75886PW
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Hysteresis
Symbol
Pin
Conditions
VH1
CE, CL, DI, RES
VH2
KI1 to KI5
Ratings
min
typ
max
0.03VDD
VDET
Input high level current
IIH1
CE, CL, DI, RES
VI=6.0V
IIH2
OSC
VI=VDD: External clock
2.0
2.3
IIL1
CE, CL, DI, RES
VI=0V
IIL2
OSC
VI=0V: External clock
5.0
VIF
KI1 to KI5
Pull-down resistance
RPD
KI1 to KI5
VDD=5.0V
Output off leakage
IOFFH
DO
VO=6.0V
VOH1
KS1 to KS6
IO=-500μA
VDD-1.0
VOH2
P1 to P5
IO=-1mA
VDD-0.9
VOH3
S1 to S57
IO=-20μA
VDD-0.9
VDD-0.9
0.05VDD
50
100
current
VDD-0.5
kΩ
6.0
μA
VDD-0.2
V
VOH4
COM1 to COM4
IO=-100μA
KS1 to KS6
IO=25μA
VOL2
P1 to P5
IO=1mA
0.9
VOL3
S1 to S57
IO=20μA
0.9
VOL4
COM1 to COM4
IO=100μA
VOL5
DO
IO=1mA
VMID1
S1 to S57
1/3 bias IO=±20μA
*2
0.2
0.5
1.5
V
0.9
0.1
2/3VDD
0.3
2/3VDD
-0.9
+0.9
1/3VDD
VMID2
S1 to S57
1/3 bias IO=±20μA
1/3VDD
-0.9
+0.9
VMID3
COM1 to COM4
1/3 bias IO=±100μA
2/3VDD
2/3VDD
-0.9
+0.9
VMID4
COM1 to COM4
1/3 bias IO=±100μA
1/3VDD
1/3VDD
-0.9
+0.9
Oscillator frequency
fOSC
OSC
ROSC=39kΩ, COSC=1000pF
RC oscillation operating mode
Current drain
IDD1
VDD
Sleep mode
IDD2
VDD
VDD=6.0V, Output open,
RC oscillation operating mode,
30.4
38
45.6
VDD=6.0V, Output open,
External clock operating mode,
fCK=38kHz, VIH3=0.5VDD,
V
kHz
100
450
900
fOSC=38kHz
VDD
V
250
VOL1
IDD3
μA
μA
-5.0
Input floating voltage
Output middle level voltage
V
-5.0
operating mode
Output low level voltage
2.6
5.0
operating mode
Output high level voltage
V
0.1VDD
Power-down detection voltage
Input low level current
Unit
μA
550
1100
VIL3=0.1VDD
Note: *2. Excluding the bias voltage generation divider resistor built into the VDD1 and VDD2. (See [Figure 1])
VDD
VDD1
To the common and segment drivers
VDD2
Excluding these resistors
[Figure 1]
No.A1391-3/36
LC75886PW
1. When CL is stopped at the low level
VIH1
CE
VIL1
tφH
VIH1
CL
tφL
50%
VIL1
tr
DI
tf
tcp
tcs
tch
VIH1
VIL1
tdh
tds
tdc
DO
D0
tdr
D1
[Figure 2]
2. When CL is stopped at the high level
VIH1
CE
VIL1
tφL
tφH
CL
tf
VIH1
50%
VIL1
tr
tcp
tcs
tch
VIH1
DI
VIL1
tds
tdh
DO
D0
D1
tdc
tdr
[Figure 3]
3. OSC pin clock timing in external clock operating mode
tCKH
OSC
VIH3
50%
VIL3
tCKL
1
fCK= t
CKH + tCKL
[kHz]
tCKH
DCK= t
CKH + tCKL
×100[%]
[Figure 4]
No.A1391-4/36
LC75886PW
Package Dimensions
unit : mm (typ)
3220
14.0
12.0
1.25
0.5
60
0.135
1.25
41
61
0.5
12.0
1.25
14.0
1.25
40
21
1
20
0.1
0.2
1.4
1.6max
80
0.5
0.5
SANYO : SQFP80(12X12)
KS5
KS4
KS3
KS2/S56
KS1/S55
COM4/S54
COM3
COM2
COM1
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
Pin Assignment
60
50
41
61
40
70
LC75886PW
30
80
21
1
10
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
20
P3/S3
P4/S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
KS6
KI1
KI2
KI3
KI4
KI5
S57/P5
VDD
VDD1
VDD2
VSS
TEST
OSC
RES
DO
CE
CL
DI
P1/S1
P2/S2
Top view
No.A1391-5/36
LC75886PW
VDD
GENERAL
PURPOSE
PORT
SEGMENT DRIVER & LATCH
VDD1
COMMON
DRIVER
VDD2
P5/S57
S1/P1
S2/P2
S3/P3
S5
S4/P4
S53
COM1
COM2
COM3
COM4/S54
Block Diagram
VSS
CLOCK
GENERATOR
OSC
CONTROL
REGISTER
DO
SHIFT REGISTER
CCB
INTERFACE
DI
CL
KEY BUFFER
CE
RES
VDD
KEY SCAN
VDET
KS6
KS5
KS4
KS3
S56/KS2
S55/KS1
KI5
KI4
KI3
KI2
KI1
TEST
No.A1391-6/36
LC75886PW
Pin Functions
Handling
Symbol
Pin No.
Function
Active
I/O
when
unused
S1/P1 to S4/P4
79,80,1,2
S5 to S53
3 to 51
COM1 to COM3
52 to 54
COM4/S54
55
Segment outputs for displaying the display data transferred by serial data
input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports
-
O
OPEN
-
O
OPEN
-
O
OPEN
H
I
GND
-
O
OPEN
-
I/O
VDD
H
I
under serial data control.
Common driver outputs.
The frame frequency is fO[Hz].
The COM4/S54 pin can be used as a segment output in 1/3 duty.
Key scan outputs. Although normal key scan timing lines require diodes to
KS1/S55
56
KS2/S56
57
KS3 to KS6
58 to 61
be inserted in the timing lines to prevent shorts, since these outputs are
unbalanced CMOS transistor outputs, these outputs will not be damaged by
shorting when these outputs are used to form a key matrix. The KS1/S55
and KS2/S56 pins can be used as segment outputs when so specified by the
control data.
KI1 to KI5
62 to 66
P5/S57
67
Key scan inputs.
These pins have built-in pull-down resistors.
General-purpose output port.
This pin can be used as clock output port or segment output port under
serial data control.
Oscillator connections. An oscillator circuit is formed by connecting an
OSC
73
CE
76
external resistor and capacitor at this pin. This pin can also be used as the
external clock input pin if the external clock operating mode is selected with
the control data.
Serial data interface connections to the controller. Note that DO, being an
open-drain output, requires a pull-up resistor.
CL
77
DI
78
I
CE: Chip enable
CL: Synchronization clock
GND
-
I
-
O
OPEN
L
I
VDD
DI: Transfer data
DO
75
DO: Output data
Reset signal input
• RES=Low ····· Display off
- S1/P1 to S4/P4, KS1/S55, KS2/S56=Low
(These pins are forcibly set to the segment output port function and
fixed at the low level.)
- S5 to S53=Low
- COM1 to COM3=Low
- COM4/S54=Low
(This pin is forcibly set to the common output function and fixed at the
low level.)
- P5/S57=Low
(This pin is forcibly set to the general-purpose output port function and
RES
74
fixed at the low level.)
- KS3 to KS6=Low
- Key scanning disabled
- All the key data is reset to low.
- OSC=”Z”(High impedance)
- RC oscillation stopped
- Inhibits external clock input
• RES=High ···· Display on
- General-purpose output port state setting is enabled
- Key scanning is enabled.
- RC oscillation enabled (RC oscilltator operating mode)
- Enables external clock input (external clock operating mode)
However, serial data can be transferred when the RES pin is low
TEST
72
This pin must be connected to ground.
-
I
-
VDD1
69
Used to apply the LCD drive 2/3 bias voltage externally.
-
I
OPEN
VDD2
70
Used to apply the LCD drive 1/3 bias voltage externally.
-
I
OPEN
VDD
68
Power supply connections. Provide a voltage of between 4.5 to 6.0V.
-
-
-
VSS
71
Power supply connections. Connect to ground.
-
-
-
No.A1391-7/36
LC75886PW
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
CE
CL
DI
0 1 0 0 0 0 1 0 D1 D2
B0 B1 B2 B3 A0 A1 A2 A3
DO
0 1 0 0 0 0 1 0 D57 D58
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1 0 D113 D114
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1 0 D169 D170
B0 B1 B2 B3 A0 A1 A2 A3
D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 0 OC PC50 PC51 KSC S0 S1 K0 K1 P0 P1 P2 SC 0 0 0
Display data (56 bits)
Control data (13 bits)
DD
(3 bits)
D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 0 0 0 0 0 0 0 0 0 0 FC0 FC1 FC2 0 0 1
Display data (56 bits)
Control data (13 bits)
DD
(3 bits)
D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Display data (56 bits)
Fixed data (13 bits)
DD
(3 bits)
D215 D216 D217 D218 D219 D220 D221 D222 D223 D224 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Display data (56 bits)
Fixed data (13 bits)
DD
(3 bits)
Note: B0 to B3, A0 to A3 ·········CCB address
DD ·································Direction data
No.A1391-8/36
LC75886PW
(2) When CL is stopped at the high level
CE
CL
DI
0 1 0 0 0 0 1
0
D1 D2
B0 B1 B2 B3 A0 A1 A2 A3
DO
0 1 0 0 0 0 1
0 D57 D58
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1
0
0 1 0 0 0 0 1
0
D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 0 0 0 0 0 0 0 0
Display data (56 bits)
D113 D114
B0 B1 B2 B3 A0 A1 A2 A3
B0 B1 B2 B3 A0 A1 A2 A3
D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 0 OC PC50 PC51 KSC S0 S1 K0 K1 P0 P1 P2 SC 0 0 0
DD
Control data (13 bits)
(3 bits)
Display data (56 bits)
D169 D170
Control data (13 bits)
D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 0 0 0
Display data (56 bits)
DD
(3 bits)
0 0 0 0 0 0 1 0
DD
(3 bits)
Fixed data (13 bits)
D215 D216 D217 D218 D219 D220 D221 D222 D223 D224 0 0 0 0 0 0 0 0
Display data (56 bits)
0 0 FC0 FC1 FC2 0 0 1
0 0 0 0 0 0 1 1
DD
(3 bits)
Fixed data (13 bits)
Note: B0 to B3, A0 to A3 ········· CCB address
DD ································· Direction data
• CCB address ··············· “42H”
• D1 to D224 ················· Display data
• OC ······························ RC oscillator operating mode/external clock operationg mode switching control data
• PC50, PC51················· General-purpose output port/clock output port/segment output port switching control data
• KSC ···························· Key scan operation enabled/disabled state setting control data
• S0, S1·························· Sleep control data
• K0, K1 ························ Key scan output/segment output switching control data
• P0 to P2······················· Segment output port/general-purpose output port switching control data
• SC ······························· Segment on/off control data
• FC0 to FC2 ················· Common and segment output waveform frame frequency control data
No.A1391-9/36
LC75886PW
2. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
DI
0 1 0 0 0 0 1 0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 OC PC50 PC51 KSC S0 S1 K0 K1 P0 P1 P2 SC 1 0 0
DD
Display data (57 bits)
Control data (12 bits)
(3 bits)
D58 D59
D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 0 0 0 0 0 0 0 0 0 FC0 FC1 FC2 1 0 1
Display data (57 bits)
Control data (12 bits)
DD
(3 bits)
D115 D116
D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Display data (57 bits)
Fixed data (12 bits)
DD
(3 bits)
B0 B1 B2 B3 A0 A1 A2 A3
DO
0 1 0 0 0 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
Note: B0 to B3, A0 to A3 ········ CCB address
DD ································· Direction data
No.A1391-10/36
LC75886PW
(2) When CL is stopped at the high level
CE
CL
DI
0 1 0 0 0 0 1
0
D1 D2
DO
0 1 0 0 0 0 1
0
D58 D59
D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 0 0 0 0 0 0 0 0 0 FC0 FC1 FC2 1 0 1
Display data (57 bits)
Control data (12 bits)
DD
(3 bits)
D115 D116
D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Display data (57 bits)
Fixed data (12 bits)
DD
(3 bits)
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1
0
B0 B1 B2 B3 A0 A1 A2 A3
D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 OC PC50 PC51 KSC S0 S1 K0 K1 P0 P1 P2 SC 1 0 0
Control data (12 bits)
DD
(3 bits)
Display data (57 bits)
B0 B1 B2 B3 A0 A1 A2 A3
Note: B0 to B3, A0 to A3 ········· CCB address
DD ································· Direction data
• CCB address ·········· “42H”
• D1 to D171 ············· Display data
• OC ························· RC oscillator operating mode/external clock operationg mode switching control data
• PC50, PC51 ············ General-purpose output port/clock output port/segment output port switching control data
• KSC ······················· Key scan operation enabled/disabled state setting control data
• S0, S1 ····················· Sleep control data
• K0, K1 ··················· Key scan output/segment output switching control data
• P0 to P2 ·················· Segment output port/general-purpose output port switching control data
• SC ·························· Segment on/off control data
• FC0 to FC2 ············· Common and segment output waveform frame frequency control data
No.A1391-11/36
LC75886PW
Control Data Functions
1. OC … RC oscillator operating mode/external clock operating mode switching control data
This control data bit selects the OSC pin function (RC oscillator operating mode or external clock operating mode)
OC
OSC pin function
0
RC oscillator operating mode
1
External clock operating mode
Note: If RC oscillator operating mode is selected, connect an external resistor ROSC and an external capacitor COSC
to the OSC pin.
2. PC50, PC51 … General-purpose output port/clock output port/segment output port switching control data
These control data bits swithes the functions of the P5/S57 output pin between the general-purpose output port, the
clock output port, and the segment output port.
Control data
PC50
PC51
0
0
The state of P5/S57 output pin
General-purpose output port (P5) (”L” level output)
1
0
General-purpose output port (P5) (“H” level output)
0
1
Clock output port (P5) (Clock frequency is fOSC/2 or fCK/2)
1
1
Segment output port (S57)
Note: If the sleep mode is set, the P5/S57 output pin can not be used as the clock output port.
3. KSC … Key scan operation enabled/disabled state setting control data
This control data bit enables or disables key scan operation.
KSC
Key scan operating state
Key scan operation enabled
0
(A key scan operation is performed if any key on the lines corresponding to KS1 to KS6 pin which is set
high is pressed.)
Key scan operation disabled
1
(No key scan operation is performed, even if any of the keys in the key matrix are pressed.
If this state is set up, the key data is forcibly reset to 0 and the key data read request is also cleared.
(DO is set high.))
4. S0, S1 … Sleep control data
These control data bits switch between normal mode and sleep mode, and set the states of the KS1 to KS6 key scan
output during key scan standby.
OSC pin state
Control data
(RC oscillator
Mode
S0
S1
or acceptance
of the external
clock signal)
Output pin states during key scan standby
Segment
output /
Common
KS1
KS2
KS3
KS4
KS5
KS6
output
0
0
Normal
Operating
Operating
H
H
H
H
H
H
0
1
Sleep
Stopped
L
L
L
L
L
L
H
1
0
Sleep
Stopped
L
L
L
L
L
H
H
1
1
Sleep
Stopped
L
H
H
H
H
H
H
Note: This assumes that the KS1/S55 and KS2/S56 output pins are selected for key scan output.
No.A1391-12/36
LC75886PW
5. K0, K1 … Key scan output/segment output switching control data
These control data bits switch the functions of the KS1/S55 and KS2/S56 output pins between the key scan output
and the segment output.
Control data
Output pin state
Maximum number
K0
K1
KS1/S55
KS2/S56
of input keys
0
0
KS1
KS2
30
0
1
S55
KS2
25
1
X
S55
S56
20
Note: KSn (n=1 or 2): Key scan output
Sn (n=55 or 56): Segment output
X : don't care
6. P0 to P2 … Segment output port/general-purpose output port switching control data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Control data
Output pin state
P0
P1
P2
S1/P1
S2/P2
S3/P3
S4/P4
0
0
0
S1
S2
S3
S4
0
0
1
P1
S2
S3
S4
0
1
0
P1
P2
S3
S4
0
1
1
P1
P2
P3
S4
1
0
0
P1
P2
P3
P4
Note: Sn (n=1 to 4): Segment output port
Pn (n=1 to 4): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to
be general-purpose output ports.
Correspondence display data
Output pin
1/4 duty
1/3 duty
S1/P1
D1
D1
S2/P2
D5
D4
S3/P3
D9
D7
S4/P4
D13
D10
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port, the S4/P4 output pin will output a high level when the display data D13 is 1, and will output a low level when
D13 is 0.
7. SC … Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
1
Off
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
8. FC0 to FC2 … Common and segment output waveform frame frequency control data
These control data bits set the common and segment output waveform frequency.
Control data
Frame frequency
FC0
FC1
FC2
fO[Hz]
1
1
0
fOSC/768, fCK/768
1
1
1
fOSC/576, fCK/576
0
0
0
fOSC/384, fCK/384
0
0
1
fOSC/288, fCK/288
0
1
0
fOSC/192, fCK/192
No.A1391-13/36
LC75886PW
Display Data and Output Pin Correspondence
1. 1/4 duty
Output pin
COM1
COM2
COM3
COM4
Output pin
COM1
COM2
COM3
COM4
S1/P1
D1
D2
D3
D4
S29
D113
D114
D115
D116
S2/P2
D5
D6
D7
D8
S30
D117
D118
D119
D120
S3/P3
D9
D10
D11
D12
S31
D121
D122
D123
D124
S4/P4
D13
D14
D15
D16
S32
D125
D126
D127
D128
S5
D17
D18
D19
D20
S33
D129
D130
D131
D132
S6
D21
D22
D23
D24
S34
D133
D134
D135
D136
S7
D25
D26
D27
D28
S35
D137
D138
D139
D140
S8
D29
D30
D31
D32
S36
D141
D142
D143
D144
S9
D33
D34
D35
D36
S37
D145
D146
D147
D148
S10
D37
D38
D39
D40
S38
D149
D150
D151
D152
S11
D41
D42
D43
D44
S39
D153
D154
D155
D156
S12
D45
D46
D47
D48
S40
D157
D158
D159
D160
S13
D49
D50
D51
D52
S41
D161
D162
D163
D164
S14
D53
D54
D55
D56
S42
D165
D166
D167
D168
S15
D57
D58
D59
D60
S43
D169
D170
D171
D172
S16
D61
D62
D63
D64
S44
D173
D174
D175
D176
S17
D65
D66
D67
D68
S45
D177
D178
D179
D180
S18
D69
D70
D71
D72
S46
D181
D182
D183
D184
S19
D73
D74
D75
D76
S47
D185
D186
D187
D188
S20
D77
D78
D79
D80
S48
D189
D190
D191
D192
S21
D81
D82
D83
D84
S49
D193
D194
D195
D196
S22
D85
D86
D87
D88
S50
D197
D198
D199
D200
S23
D89
D90
D91
D92
S51
D201
D202
D203
D204
S24
D93
D94
D95
D96
S52
D205
D206
D207
D208
S25
D97
D98
D99
D100
S53
D209
D210
D211
D212
D216
S26
D101
D102
D103
D104
KS1/S55
D213
D214
D215
S27
D105
D106
D107
D108
KS2/S56
D217
D218
D219
D220
S28
D109
D110
D111
D112
P5/S57
D221
D222
D223
D224
Note: This is for the case where the S1/P1 to S4/P4, KS1/S55, KS2/S56, P5/S57 output pins are selected for use as
segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D41
D42
D43
D44
0
0
0
0
The LCD segments for COM1, COM2, COM3 and COM4 are off.
0
0
0
1
The LCD segment for COM4 is on.
0
0
1
0
The LCD segment for COM3 is on.
0
0
1
1
The LCD segments for COM3 and COM4 are on.
0
1
0
0
The LCD segment for COM2 is on.
0
1
0
1
The LCD segments for COM2 and COM4 are on.
0
1
1
0
The LCD segments for COM2 and COM3 are on.
0
1
1
1
The LCD segments for COM2, COM3 and COM4 are on.
1
0
0
0
The LCD segment for COM1 is on.
1
0
0
1
The LCD segments for COM1 and COM4 are on.
1
0
1
0
The LCD segments for COM1 and COM3 are on.
1
0
1
1
The LCD segments for COM1, COM3 and COM4 are on.
1
1
0
0
The LCD segments for COM1 and COM2 are on.
1
1
0
1
The LCD segments for COM1, COM2 and COM4 are on.
1
1
1
0
The LCD segments for COM1, COM2 and COM3 are on.
1
1
1
1
The LCD segments for COM1, COM2, COM3 and COM4 are on.
No.A1391-14/36
LC75886PW
2. 1/3 duty
Output pin
COM1
COM2
COM3
Output pin
COM1
COM2
COM3
S1/P1
D1
D2
D3
S31
D91
D92
D93
S2/P2
D4
D5
D6
S32
D94
D95
D96
S3/P3
D7
D8
D9
S33
D97
D98
D99
S4/P4
D10
D11
D12
S34
D100
D101
D102
S5
D13
D14
D15
S35
D103
D104
D105
S6
D16
D17
D18
S36
D106
D107
D108
S7
D19
D20
D21
S37
D109
D110
D111
S8
D22
D23
D24
S38
D112
D113
D114
S9
D25
D26
D27
S39
D115
D116
D117
S10
D28
D29
D30
S40
D118
D119
D120
S11
D31
D32
D33
S41
D121
D122
D123
S12
D34
D35
D36
S42
D124
D125
D126
S13
D37
D38
D39
S43
D127
D128
D129
S14
D40
D41
D42
S44
D130
D131
D132
S15
D43
D44
D45
S45
D133
D134
D135
S16
D46
D47
D48
S46
D136
D137
D138
S17
D49
D50
D51
S47
D139
D140
D141
S18
D52
D53
D54
S48
D142
D143
D144
S19
D55
D56
D57
S49
D145
D146
D147
S20
D58
D59
D60
S50
D148
D149
D150
S21
D61
D62
D63
S51
D151
D152
D153
S22
D64
D65
D66
S52
D154
D155
D156
S23
D67
D68
D69
S53
D157
D158
D159
S24
D70
D71
D72
COM4/S54
D160
D161
D162
S25
D73
D74
D75
KS1/S55
D163
D164
D165
S26
D76
D77
D78
KS2/S56
D166
D167
D168
S27
D79
D80
D81
P5/S57
D169
D170
D171
S28
D82
D83
D84
S29
D85
D86
D87
S30
D88
D89
D90
Note: This is for the case where the S1/P1 to S4/P4, COM4/S54, KS1/S55, KS2/S56, P5/S57 output pins are selected
for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31
D32
D33
0
0
0
The LCD segments for COM1, COM2, and COM3 are off.
0
0
1
The LCD segment for COM3 is on.
0
1
0
The LCD segment for COM2 is on.
0
1
1
The LCD segments for COM2 and COM3 are on.
1
0
0
The LCD segment for COM1 is on.
1
0
1
The LCD segments for COM1 and COM3 are on.
1
1
0
The LCD segments for COM1 and COM2 are on.
1
1
1
The LCD segments for COM1, COM2 and COM3 are on.
No.A1391-15/36
LC75886PW
Serial Data Output
1. When CL is stopped at the low level
CE
CL
DI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
DO
X
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
X: don’t care
Note: B0 to B3, A0 to A3 … CCB address
2. When CL is stopped at the high level
CE
CL
DI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
DO
X KD1 KD2 KD3
KD28 KD29 KD30 SA
Output data
Note: B0 to B3, A0 to A3 … CCB address
X
X: don’t care
• CCB address ······ “43H”
• KD1 to KD30 ····· Key data
• SA ······················ Sleep acknowledge data
Note: If a key data read operation is executed when DO is high (DO does not generate a key data read request output),
the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
Output Data
1. KD1 to KD30 … Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and KI1 to KI5 input pins and one of
those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship
between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1/S55
KD1
KD2
KD3
KD4
KD5
KS2/S56
KD6
KD7
KD8
KD9
KD10
KS3
KD11
KD12
KD13
KD14
KD15
KS4
KD16
KD17
KD18
KD19
KD20
KS5
KD21
KD22
KD23
KD24
KD25
KS6
KD26
KD27
KD28
KD29
KD30
When the KS1/S55 and KS2/S56 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA … Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial
data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in
sleep mode and 0 in normal mode.
No.A1391-16/36
LC75886PW
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. When sleep mode is set up, both the segment and
common outputs will go to the low level. In RC oscillator operating mode (OC=0), the oscillator on the OSC pin will
stop (although it will operate during key scan operations), and in exeternal clock operating mode (OC=1), acceptance of
the external clock signal on the OSC pin will stop (although the clock signal will be accepted during key scan
operations). Thus this mode reduces power consumption. However, the S1/P1 to S4/P4, P5/S57 output pins can be used
as general-purpose output ports under control of the P0 to P2, PC50 and PC51 bits in the control data even in sleep
mode (The P5/S57 output pin can not be used as clock output port). Sleep mode is cancelled by setting both S0 and S1
in control data to 0.
Key Scan Operation Functions
1. Key scan timing
The key scan period is 288T[s]. To reliably determine the on/off state of the keys, the LC75886PW scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 615T[s] after starting a key scan. If the key data does not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75886PW cannot detect a key press shorter than 615T[s].
KS1
*3
KS2
*3
KS3
*3
KS4
*3
KS5
*3
1
*3
1
2
*3
2
3
*3
3
4
*3
4
5
6
KS6
Key on
*3
5
6
1
1
T= f
=
OSC fCK
576T[s]
Note: *3. These are set to the high or low level by the S0 and S1 bits in the control data.
Key scan output signals are not output from pins that are set to the low level.
No.A1391-17/36
LC75886PW
2. Normal mode, when key scan operations are enabled
(1) The KS1 to KS6 pins are set high. (See the description of the control data.)
(2) When a key is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
(3) If a key is pressed for longer than 615T[s] (Where T=1/fOSC or T=1/fCK), the LC75886PW outputs a key data read
request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
(4) After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75886PW
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and
10kΩ).
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
615T[s]
CE
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=0)
Key
address(43H)
Serial data transfer
(KSC=0)
Key
address(43H)
Key
address(43H)
DI
DO
Key data read
Key data read request
Key data read
Key data read
Key data read request
Key data read request
1
1
T= f
=
OSC fCK
3. Sleep mode, when key scan operations are enabled
(1) The KS1 to KS6 pins are set to high or low level by the S0 and S1 bits in the control data.
(See the description of the control data.)
(2) If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC
pins starts in RC oscillator operating mode (the IC starts accepting the external clock signal in external clock
operating mode) and a key scan is performed. Keys are scanned until all keys are released.
Multiple key presses are recognized by determining whether multiple key data bits are set.
(3) If a key is pressed for longer than 615T[s] (Where T=1/fOSC or T=1/fCK), the LC75886PW outputs a key data read
request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
(4) After the controller reads the key data, the key data read request is cleared (DO is set high) and the
LC75886PW performs another key scan. However, this does not clear sleep mode. Also note that DO, being an
open-drain output, requires a pull-up resistor (between 1 and 10kΩ).
(5) Sleep mode key scan example
Example: S0=0, S1=1 (Sleep with only KS6 high)
“L” KS1
“L” KS2
“L” KS3
“L” KS4
“L” KS5
“H” KS6
*4
When any one of these keys is pressed, the
oscillator on the OSC pins starts in RC oscillator
operating mode (the IC starts accepting the external
clock signal in external clock operating mode) and a
key scan operation is performed.
KI1
KI2
KI3
KI4
KI5
Note: *4. These diodes are required to reliably recognize multiple key presses on the KS6 line when sleep mode state
with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak
currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
No.A1391-18/36
LC75886PW
Key input
(KS6 line)
Key scan
615T[s]
615T[s]
CE
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=0)
Key
Serial data transfer
address(43H)
(KSC=0)
Key
address(43H)
DI
1
1
T= f
=
OSC fCK
DO
Key data read
Key data read request
Key data read
Key data read request
4. Normal/sleep mode, when key scan operations are disabled
(1) The KS1 to KS6 pins are set to high or low level by the S0 and S1 bits in the control data.
(2) No key scan operation is performed, whichever key is pressed.
(3) If the key scan disabled state (KSC=1 in the control data) is set during a key scan, the key scan is stopped.
(4) If the key scan disabled state (KSC=1 in the control data) is set when a key data read request (a low level on DO) is
output to the controller, all the key data is set to 0 and the key data read request is cleared (DO is set high).
Note that DO, being an open-drain output, requires a pull-up resister (between 1 to 10kΩ).
(5) The key scan disabled state is cleared by setting KSC in the control data to 0.
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
CE
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=1)
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=1)
Serial data transfer
(KSC=0)
Key
address(43H)
DI
DO
Key data read request
Key data read
Key data read request
1
1
T= f
=
OSC fCK
Multiple Key Presses
Although the LC75886PW is capable of key scanning without inserting diodes for dual key presses, triple key presses
on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other
than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
No.A1391-19/36
LC75886PW
1/4 Duty, 1/3 Bias Drive Technique
fO[Hz]
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
COM1
COM2
COM3
COM4
LCD driver output when all LCD
segments corresponding to COM1,
COM2, COM3, and COM4 are turned off.
LCD driver output when only
LCD segments corresponding to
COM1 are on.
LCD driver output when only
LCD segments corresponding to
COM2 are on.
LCD driver output when
LCD segments corresponding to
COM1 and COM2 are on.
LCD driver output when only
LCD segments corresponding to
COM3 are on.
LCD driver output when
LCD segments corresponding to
COM1 and COM3 are on.
LCD driver output when
LCD segments corresponding to
COM2 and COM3 are on.
LCD driver output when
LCD segments corresponding to
COM1, COM2, and COM3 are on.
LCD driver output when only
LCD segments corresponding to
COM4 are on.
LCD driver output when
LCD segments corresponding to
COM2 and COM4 are on.
LCD driver output when all
LCD segments corresponding to
COM1, COM2, COM3, and COM4 are on.
Control data
Common and segment output waveform
FC0
FC1
FC2
frame frequency fO[Hz]
1
1
0
fOSC/768, fCK/768
1
1
1
fOSC/576, fCK/576
0
0
0
fOSC/384, fCK/384
0
0
1
fOSC/288, fCK/288
0
1
0
fOSC/192, fCK/192
No.A1391-20/36
LC75886PW
1/3 Duty, 1/3 Bias Drive Technique
fO[Hz]
VDD
VDD1
COM1
VDD2
0V
VDD
VDD1
VDD2
COM2
0V
VDD
VDD1
COM3
VDD2
0V
VDD
VDD1
LCD driver output when all LCD
segments corresponding to COM1,
COM2, and COM3 are turned off.
VDD2
0V
VDD
VDD1
LCD driver output when only
LCD segments corresponding to
COM1 are on.
VDD2
0V
VDD
VDD1
LCD driver output when only
LCD segments corresponding to
COM2 are on.
VDD2
0V
VDD
VDD1
LCD driver output when
LCD segments corresponding to
COM1 and COM2 are on.
VDD2
0V
VDD
VDD1
LCD driver output when only
LCD segments corresponding to
COM3 are on.
VDD2
0V
VDD
VDD1
LCD driver output when
LCD segments corresponding to
COM1 and COM3 are on.
VDD2
0V
VDD
VDD1
LCD driver output when
LCD segments corresponding to
COM2 and COM3 are on.
VDD2
0V
VDD
LCD driver output when all
LCD segments corresponding to
COM1, COM2, and COM3 are on.
VDD1
VDD2
0V
Control data
Common and segment output waveform
FC0
FC1
FC2
frame frequency fO[Hz]
1
1
0
fOSC/768, fCK/768
1
1
1
fOSC/576, fCK/576
0
0
0
fOSC/384, fCK/384
0
0
1
fOSC/288, fCK/288
0
1
0
fOSC/192, fCK/192
No.A1391-21/36
LC75886PW
Clock Signal Output Waveform
Control data
PC50
PC51
0
1
The state of P5/S57 output pin
Clock output port (P5) (Clock frequency is fOSC/2 or fCK/2)
P5
Tc=
Tc/2
1
fc
Tc
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e.,
when the power supply voltage is less than or equal to the power down detection voltage VDET, which is 2.3V, typical.
To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power
supply voltage VDD rise time when the power is first applied and the power supply voltage VDD fall time when the
voltage drops are both at least 1ms. (See Figure 5 and Figure 6.)
System Reset
The LC75886PW supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, all the key data is reset to low, and the general-purpose output ports are fixed at the low level (The
S1/P1 to S4/P4 pins are forcibly set to the segment output port function and fixed at the low level. The P5/S57 pin is
forcibly set to the general-purpose output port function and fixed at the low level). When the reset is cleared, display is
turned on, key scanning is enabled and the general-purpose output ports state setting is enabled.
1. Reset methods
(1) Reset method by the voltage detection type reset circuit (VDET)
If at least 1ms is assured as the supply voltage VDD rise time when power is applied, a system reset will be applied
by the VDET output signal when the supply voltage is brought up. If at least 1 ms is assured as the supply voltage
VDD fall time when power drops, a system reset will be applied in the same manner by the VDET output signal
when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (1/4 duty: the
display data D1 to D224 and the control data, 1/3 duty: the display data D1 to D171 and the control data) has been
transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has
been transferred. (See Figure 5 and Figure 6.)
• 1/4 duty
t1
t2
VDD
VDET
VDET
CE
VIL1
Display and control data transfer
D1 to D56
Internal data OC, PC50, PC51, KSC,
S0, S1, K0, K1, P0 to P2, SC
Undefined
Defined
Undefined
Internal data (D57 to D112, FC0 to FC2)
Undefined
Defined
Undefined
Internal data (D113 to D168)
Undefined
Defined
Undefined
Internal data (D169 to D224)
Undefined
Defined
Undefined
System reset period
Note: t1≥1 [ms](Power supply voltage VDD rise time)
t2≥1 [ms](Power supply voltage VDD fall time)
[Figure 5]
No.A1391-22/36
LC75886PW
• 1/3 duty
t1
t2
VDD
VDET
VDET
VIL1
CE
Display and control data transfer
D1 to D57
Internal data OC, PC50, PC51, KSC,
S0, S1, K0, K1, P0 to P2, SC
Undefined
Defined
Undefined
Internal data (D58 to D114, FC0 to FC2)
Undefined
Defined
Undefined
Internal data (D115 to D171)
Undefined
Defined
Undefined
System reset period
Note: t1≥1 [ms](Power supply voltage VDD rise time)
t2≥1 [ms](Power supply voltage VDD fall time)
[Figure 6]
(2) Reset method by the RES pin
When power is applied, a system reset is applied by setting the RES pin low level. The reset is cleared by setting the
RES pin high level after all the serial data (1/4 duty: the display data D1 to D224 and the control data, 1/3 duty: the
display data D1 to D171 and the control data) has been transferred.
In the allowable operating range (VDD=4.5 to 6.0V), A reset is applied by setting the RES pin low level.
and the reset is cleared by setting the RES pin high level
2. Internal block states during the reset period
• CLOCK GENERATOR
A reset is applied and either the OSC pin oscillator is stopped or external clock reception is stopped
• COMMON DRIVER, SEGMENT DRIVER & LATCH
A reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
A reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
A reset is applied and all the key data is set to low.
• GENERAL PURPOSE PORT
A reset is applied, the circuit is set to the initial state.
• CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER
Since serial data transfer is possible, these circuits are not reset.
No.A1391-23/36
VDD
GENERAL
PURPOSE
PORT
SEGMENT DRIVER & LATCH
VDD1
COMMON
DRIVER
VDD2
P5/S57
S1/P1
S2/P2
S3/P3
S5
S4/P4
S53
COM1
COM2
COM3
COM4/S54
LC75886PW
VSS
CLOCK
GENERATOR
OSC
CONTROL
REGISTER
DO
SHIFT REGISTER
CCB
INTERFACE
DI
CL
KEY BUFFER
CE
RES
KEY SCAN
VDD
VDET
KS6
KS5
KS4
KS3
S56/KS2
S55/KS1
Blocks that are reset
KI5
KI4
KI3
KI2
KI1
TEST
No.A1391-24/36
LC75886PW
3. Pin states during the reset period
Pin
State during reset
S1/P1 to S4/P4
L *5
S5 to S53
L
COM1 to COM3
L
COM4/S54
L *6
KS1/S55, KS2/S56
L *5
KS3 to KS6
L *7
P5/S57
L *8
OSC
Z *9
DO
H *10
Note: *5. These output pins are forcibly set to the segment output function and held low.
*6. This output pin is forcibly set to the common output function and held low.
*7. These output pins are forcibly held fixed at the low level.
*8. This output pin is forcibly set to the general-purpose output port function and held low.
*9. This I/O pin is forcibly set to the high-impedance state.
*10.Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10kΩ is required. This pin
remains high during the reset period even if a key data read operation is performed.
Notes on the OSC Pin Peripheral Circuit
1. RC oscillator operationg mode (Control data bit OC=0)
When RC oscillator operationg mode is selected, an external resistor ROSC and an external capacitor COSC must be
connected between the OSC pin and GND.
OSC
ROSC
COSC
2. External clock operating mode (Control data bit OC=1 )
When selecting the external clock operating mode, connect a current protection resistor Rg (4.7 to 47kΩ) between the
OSC pin and the external clock output pin (external oscillator). Determine the value of the resistance according to the
maximum allowable current value of the external clock output pin. Also make sure that the waveform of the external
clock is not excessively distorted.
External clock output pin
OSC
Rg
External oscillator
Note: Allowable current value at external clock output pin >
VDD
Rg
No.A1391-25/36
LC75886PW
Sample Application Circuit 1
1/4 duty, 1/3 bias (for use with normal panels)
(P1)
(P2)
(P3)
(P4)
P5
OSC
*13
VDD
*11
COM1
COM2
COM3
VSS
S54/COM4
TEST
P1/S1
P2/S2
P3/S3
P4/S4
S5
VDD1
VDD2
C≥0.047μF
C
S53
C
(S55)
(S56)
RES *12
*15
From the
controller
CE
CL
DI
*15
To the controller
To the controller
power supply
DO
Used with the
backlight controller
or other circuit.
KK K K K
I I I I I
5 4 3 2 1
S
5
6
/
K K K K K
S S S S S
6 5 4 3 2
S
5
5
/
K
S
1
P5/S57
(S57)
LCD panel (up to 224 segments)
+5V
(Genenal-purpose
output port)
*14
Key matrix
(up to 30 keys)
Note: *11. Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1ms, as the
LC75886PW is reset by the VDET.
*12. If the RES pin is not used for system reset, it must be connected to the power supply VDD.
*13. When RC oscillator operating mode is used, the external resistor ROSC and the external capacitor COSC
must be connected between the OSC pin and GND, and when external clock operating mode is selected the
current protection resistor Rg (4.7 to 47kΩ) must be connected between the OSC pin and the external clock
output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*14. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*15. The pins to be connected to the controller (CE, CL, DI, DO, RES) can handle 3.3V or 5V.
No.A1391-26/36
LC75886PW
Sample Application Circuit 2
1/4 duty, 1/3bias (for use with large panels)
(P1)
(P2)
(P3)
(P4)
10kΩ≥R≥1kΩ
C≥0.047μF
P5
OSC
*13
VDD
R
COM1
COM2
COM3
VDD1
S54/COM4
R
*11
C
C
VDD2
P1/S1
R
P2/S2
P3/S3
P4/S4
VSS
S5
TEST
S53
(S55)
(S56)
RES
*15
From the
controller
To the controller
power supply
*12
CE
CL
DI
*15
To the controller
Used with the
backlight controller
or other circuit.
DO
K K K K K
I I I I I
5 4 3 2 1
S
5
6
/
K K K K K
S S S S S
6 5 4 3 2
S
5
5
/
K
S
1
P5/S57
(S57)
LCD panel (up to 224 segments)
+5V
(Genenal-purpose
output port)
*14
Key matrix
(up to 30 keys)
Note: *11. Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1ms, as the
LC75886PW is reset by the VDET.
*12. If the RES pin is not used for system reset, it must be connected to the power supply VDD.
*13. When RC oscillator operating mode is used, the external resistor ROSC and the external capacitor COSC
must be connected between the OSC pin and GND, and when external clock operating mode is selected the
current protection resistor Rg (4.7 to 47kΩ) must be connected between the OSC pin and the external clock
output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*14. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*15. The pins to be connected to the controller (CE, CL, DI, DO, RES) can handle 3.3V or 5V.
No.A1391-27/36
LC75886PW
Sample Application Circuit 3
1/3 duty, 1/3 bias (for use with normal panels)
(P1)
(P2)
(P3)
(P4)
P5
OSC
*13
VDD
*11
COM1
COM2
COM3
VSS
TEST
P1/S1
P2/S2
P3/S3
P4/S4
S5
VDD1
S53
VDD2
C≥0.047μF
C
C
CE
CL
DI
*15
To the controller
To the controller
power supply
COM4/S54
RES *12
*15
From the
controller
DO
Used with the
backlight controller
or other circuit.
K K K K K
I I I I I
5 4 3 2 1
S
5
6
/
K K K K K
S S S S S
6 5 4 3 2
S
5
5
/
K
S
1
P5/S57
(S54)
(S55)
(S56)
(S57)
LCD panel (up to 171 segments)
+5V
(Genenal-purpose
output port)
*14
Key matrix
(up to 30 keys)
Note: *11. Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1ms, as the
LC75886PW is reset by the VDET.
*12. If the RES pin is not used for system reset, it must be connected to the power supply VDD.
*13. When RC oscillator operating mode is used, the external resistor ROSC and the external capacitor COSC
must be connected between the OSC pin and GND, and when external clock operating mode is selected the
current protection resistor Rg (4.7 to 47kΩ) must be connected between the OSC pin and the external clock
output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*14. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*15. The pins to be connected to the controller (CE, CL, DI, DO, RES) can handle 3.3V or 5V.
No.A1391-28/36
LC75886PW
Sample Application Circuit 4
1/3 duty, 1/3bias (for use with large panels)
(P1)
(P2)
(P3)
(P4)
10kΩ≥R≥1kΩ
C≥0.047μF
P5
OSC
*13
VDD
R
COM1
COM2
COM3
VDD1
R
*11
C
C
P1/S1
VDD2
P2/S2
R
P3/S3
P4/S4
S5
VSS
TEST
S53
COM4/S54
RES *12
*15
From the
controller
CE
CL
DI
*15
To the controller
To the controller
power supply
DO
Used with the
backlight controller
or other circuit.
K K K K K
I I I I I
5 4 3 2 1
S
5
6
/
K K K K K
S S S S S
6 5 4 3 2
S
5
5
/
K
S
1
P5/S57
(S54)
(S55)
(S56)
(S57)
LCD panel (up to 171 segments)
+5V
(Genenal-purpose
output port)
*14
Key matrix
(up to 30 keys)
Note: *11. Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1ms, as the
LC75886PW is reset by the VDET.
*12. If the RES pin is not used for system reset, it must be connected to the power supply VDD.
*13. When RC oscillator operating mode is used, the external resistor ROSC and the external capacitor COSC
must be connected between the OSC pin and GND, and when external clock operating mode is selected the
current protection resistor Rg (4.7 to 47kΩ) must be connected between the OSC pin and the external clock
output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*14. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*15. The pins to be connected to the controller (CE, CL, DI, DO, RES) can handle 3.3V or 5V.
Notes on Transferring Display Data from The Controller
When using the LC75886PW in 1/4 duty, applications transfer the display data (D1 to D224) in four operations, and in
1/3 duty, they transfer the display data (D1 to D171) in three operations. In either case, applications should transfer all
of the display data within 30ms to maintain the quality of displayed image.
No.A1391-29/36
LC75886PW
Notes on the Controller Key Data Read Techniques
1. Timer based key data acquisition
(1) Flowchart
CE=”L”
NO
DO=”L”
YES
Key data read
processing
(2) Timing chart
Key on
Key on
Key input
Key scan
t3
t4
t3
t3
CE
t6
Key
address
DI
t5
t6
Key data read
t6
t5
t5
DO
Key data read request
t7
Controller
determination
(Key on)
t7
Controller
determination
(Key on)
t7
Controller
determination
(Key off)
t7
Controller
determination
(Key on)
Controller
determination
(Key off)
t3 ······· Key scan execution time when the key data agreed for two key scans. (615T[s])
t4 ······· Key scan execution time when the key data did not agree for two key scans and the key scan was executed
again. (1230T[s])
t5 ······· Key address (43H) transfer time
1
1
T= f
=
t6 ······· Key data read time
OSC fCK
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller
must check the DO state when CE is low every t7 period without fail. If DO is low, the controller recognizes that a
key has been pressed and executes the key data read operation.
The period t7 in this technique must satisfy the following condition.
t7>t4+t5+t6
If a key data read operation is executed when DO is high (DO does not generate a key data read request output), the
read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
No.A1391-30/36
LC75886PW
2. Interrupt based key data acquistion
(1) Flowchart
CE=”L”
NO
DO=”L”
YES
Key data read
processing
Wait for
at least t8
CE=”L”
NO
DO=”H”
YES
Key OFF
(2) Timing chart
Key on
Key on
Key input
Key scan
t3
t4
t3
t3
CE
t6
Key
address
DI
t5
t6
Key data read
t6
t5
t6
t5
t5
DO
Key data read request
Controller
determination
(Key on)
t8
Controller
determination
(Key off)
Controller
determination
(Key on)
t8
t8
t8
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
t3 ······· Key scan execution time when the key data agreed for two key scans. (615T[s])
t4 ······· Key scan execution time when the key data did not agree for two key scans and the key scan was executed
again. (1230T[s])
t5 ······· Key address (43H) transfer time
1
1
T= f
=
t6 ········ Key data read time
OSC fCK
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data.
The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been
pressed and executes the key data read operation. After that the next key on/off determination is performed after the
time t8 has elapsed by checking the DO state when CE is low and reading the key data. The period t8 in this
technique must satisfy the following condition.
t8>t4
If a key data read operation is executed when DO is high (DO does not generate a key data read request output), the
read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
No.A1391-31/36
LC75886PW
About Data Communication Method with The Controller
1. About data communication method of 4 line type CCB format
The 4 line type CCB format is the data communication method of before. The LC75886PW must connect to the
controller as followings.
*17
(INT)
Controller
*16
Rup
DI
DO
DO
DI
CL
CL
CE
CE
LC75886PW
Note: *16. Connect the pull-up resistor Rup. Select a resistance
(between 1 to 10kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
*17. The (INT) pin is an input port for the key data read request
signal (a low level on DO) detection.
2. About data communication method of 3 line type CCB format
The 3 line type CCB format is the data communication method that made a common use of the data input DI in the
data output DO. The LC75886PW must connect to the controller as followings.
*17
(INT)
*16
Rup
DIO
DO
Controller
DI
CL
CL
CE
CE
LC75886PW
Note: *16. Connect the pull-up resistor Rup. Select a resistance
(between 1 to 10kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
*17. The (INT) pin is an input port for the key data read request
signal (a low level on DO) detection.
In this case, Applications must transfer the data communication start command before the serial data input (CCB
address “42H”, display data and control data transfer) or serial data output (CCB address “43H” transfer, key data read)
to avoid the collision of the data input signal DI and the data output signal DO.
Then applications must transfer the data communication stop command when the controller wants to detect the key data
read request signal (a low level on DO) during a movement stop of the serial data input and the serial data output.
<1> Data communication start command
(1) When CL is stopped at the low level
(2) When CL is stopped at the high level
CE
CE
CL
CL
DI/DO
0 0 0 0 0 0 0 0
0
CCB address “00H”
0 1 1 0 1 1 1
Command data
<2> Data communication stop command
(1) When CL is stopped at the low level
DI/DO
CL
CL
1
1 0 0 0 1 1 1
Command data
0 0 1 1 0 1 1 1
Command data
(2) When CL is stopped at the high level
CE
0 0 0 0 0 0 0 0
CCB address “00H”
0
CCB address “00H”
CE
DI/DO
0 0 0 0 0 0 0
DI/DO
0 0 0 0 0 0 0
CCB address “00H”
0
1 1 0 0 0 1 1 1
Command data
No.A1391-32/36
LC75886PW
Data Communication Flowchart of 4 Line Type or 3 Line Type CCB Format
1. Flowchart of the initial setting when power is turned on.
Power on
(Applications must observe that the power
supply VDD rise time is at least 1ms.)
Power supply stability
(Applications must wait till the level of
the power supply is stable)
Serial data input
(Display and control data transfer)
Note: The flowchart of initial setting when power is
turned on is same regardless of the 4 line type
or 3 line type CCB format.
Take explanation about "system reset" into account.
System reset clear
(Display on, Key scanning is enabled,
General-purpose output port state
setting are enabled)
2. Flowchart of the serial data input
Data communication start
command transfer
*18
Serial data input
(Display and control data transfer)
NO
The controller
wants to detect the key
data read request signal
(a low level on DO).
YES
Data communication stop
command transfer
*18
Note: *18. In the case of the 4 line type CCB format,
the transfers of data communication start
command and data communication stop
command are unnecessary, and, in the case
of the 3 line type CCB format, these transfers
are necessary.
3. Flowchart of the serial data output
NO
The controller
acknowledges the key data read
request (When the CE is low,
the DO is low)
YES
Data communication start
command transfer
*19
Serial data output
(Key data and sleep
acknowledge data read)
*20
Note: *19. In the case of the 4 line type CCB format,
the transfer of data communication start
command is unnecessary, and, in the case
of the 3 line type CCB format, the transfer
is necessary.
*20. Because the serial data output has the role
of the data communication stop command,
it is not necessary to transfer the data
communication stop command some other
time.
No.A1391-33/36
LC75886PW
Timing Chart of 4 Line Type and 3 Line Type CCB Format
1. Timing chart of 4 line type CCB format
<Example 1>
Key on
Key off
Key input
Key scan
Key scan execution
*21
CE
CCB address
(42H)
Key scan execution
*21
CCB address CCB address
(42H)
(42H)
CCB address
(43H)
DI
DO
Serial data input
(Display and control data transfer)
Serial data output
(Key data read)
Key data read
request
Key data read
request
<Example 2>
Key input
Key off
Key off
Key on
Key on
Key scan
Key scan execution
*21
Key scan execution *21
CE
CCB address
(42H)
CCB address CCB address
(42H)
(42H)
CCB address
(43H)
CCB address
(43H)
DI
DO
Serial data input
(Display and control
data tranfer)
Serial data output
(Key data read)
Key data read
request
Serial data output
(Key data read)
Key data read
request
<Example 3>
Key on
Key input
Key off
Key off
Key scan
CE
Key scan execution
*21
Key scan execution
*21
CCB address
(42H)
CCB address CCB address
(42H)
(42H)
CCB address
(43H)
CCB address
(43H)
DI
DO
Key data read
request
Serial data input
(Display and control
data transfer)
Serial data output
(Key data read)
Key data read
request
Note: *21. When the key data agrees for two key scans, the key scan execution time is 615T[s].
And, when the key data does not agree for two key scans and the key scan is executed
again, the key scan execution time is 1230T[s].
Serial data output
(Key data read)
1
1
T= f
=
OSC fCK
No.A1391-34/36
LC75886PW
2. Timing chart of 3 line type CCB format
<Example 1>
Key on
Key off
Key input
Key scan
Key scan execution
*21
CE
CCB address
(42H)
CCB address
(42H)
CCB address
(42H)
Key scan execution
*21
CCB address
(43H)
DI/DO
Data communication
start command
Serial data input
(Display and control
data transfer)
Data communication
stop command
Data
communication
start command
Key data read
request
Serial data
output
(Key data
read)
Key data read
request
<Example 2>
Key on
Key on
Key off
Key input
Key off
Key scan
Key scan execution *21
Key scan execution
*21
CE
CCB address
(42H)
CCB address
(42H)
CCB address
(42H)
CCB address
(43H)
CCB address
(43H)
DI/DO
Data communication
start command
Serial data input
(Display and control
data transfer)
Data
communication
stop command
Data
communication
start command
Key data read
request
Serial data
Data
output
communication
(Key data
start command
read)
Key data read
request
Serial data
output
(Key data
read)
<Example 3>
Key on
Key input
Key off
Key off
Key scan
CE
Key scan execution
*21
Key scan execution
*21
CCB address
(42H)
CCB address CCB address CCB address
(42H)
(42H)
(43H)
CCB address
(43H)
DI/DO
Data
communication
start command
Key data read
request
Serial data input
(Display and control
data transfer)
Serial data
output
(Key data
read)
Data
communication
start command
Key data read
request
Note: *21. When the key data agrees for two key scans, the key scan execution time is 615T[s].
And, when the key data does not agree for two key scans and the key scan is executed
again, the key scan execution time is 1230T[s].
Serial data
output
(Key data
read)
1
1
T= f
=
OSC fCK
No.A1391-35/36
LC75886PW
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