TCC 106 D

TCC-106
Six-Output PTIC Control IC
Introduction
ON Semiconductor’s PTIC Controller IC is a six−output
high−voltage digital to analog control IC specifically designed to
control and bias ON Semiconductor’s Passive Tunable Integrated
Circuits (PTICs).
These tunable capacitive circuits are intended for use in mobile
phones and dedicated RF tuning applications. The implementation of
ON Semiconductor’s tunable circuits in mobile phones enables
significant improvement in terms of antenna radiated performance.
The tunable capacitors are controlled through a bias voltage ranging
from 2 V to 20 V. The TCC−106 high−voltage PTIC control IC has
been specifically designed to cover this need, providing six
independent high−voltage outputs that control up to six different
tunable PTICs in parallel. The device is fully controlled through a
multi−protocol digital interface.
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RDL Ball Array
CASE 567HL
MARKING DIAGRAM
Key Features
• Controls ON Semiconductor’s PTIC Tunable Capacitors
• Compliant with Timing Needs of Cellular and Other Wireless System
TC6x
ALYW
Requirements
• Integrated Boost Converter with 6 Programmable Outputs
(up to 24 V)
RDL
• Low Power Consumption
• Auto−detection of SPI (30− or 32−bit) or MIPI RFFE Interfaces
(1.2 V or 1.8 V)
• Available in WLCSP (RDL ball arrays) and for Stand−alone or
•
Module Integration
This is a Pb−Free Device
TC6
x
A
L
Y
W
O
= Product Code
= MIPI ID
= Assembly Location
= Wafer Lot Code
= Year Code
= Week Code
= Pin 1 Marker
Typical Applications
• Multi−band, Multi−standard, Advanced and Simple Mobile Phones
• Tunable Antenna Matching Networks
• Compatible with Closed−loop and Open−loop Antenna Tuner
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 23 of this data sheet.
Applications
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 5
1
Publication Order Number:
TCC−106/D
TCC−106
L_BOOST
VHV
GND_BOOST
VREG
Booster
AVDD
Regulator
Bandgap
vio_on
GNDA
VREG
POR
ibias_start/vref_start
4 bit
DAC
VIO
POR
VIO
por_vreg
Start
Reference
GNDIO
Registers
8
7−bit
DAC
OUTA
8
7−bit
DAC
OUTB
8
7−bit
DAC
OUTC
8
7−bit
DAC
OUTD
8
7−bit
DAC
OUTE
8
7−bit
DAC
OUTF
Interface
Level
Shifter
TRIG
IDB0
CS
CLK
OTP
DATA
ATEST
Figure 1. Control IC Functional Block Diagram
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2
VIO
AVDD
VREG
VHV
TCC−106
RDL Pin Out
Table 1. PAD DESCRIPTIONS
1.
2.
3.
4.
Bump
Name
Type
Description
Max Voltage
(Note 1)
RDL
1
L_BOOST
AOH
Boost Inductor
25
B4
2
AVDD
P
Analog Supply
5.5
B3
3
GNDA
P
Analog Ground
0
C3
4
TRIG
DIO
Trigger Signal Input (Note 2)
VIO
C4
5
CLK
DI
MIPI RFFE / SPI Clock
VIO
D4
6
CS
DI
Chip Select for SPI
VIO
D3
7
DATA
DIO
Digital IO (SPI and MIPI RFFE)
VIO
E4
8
VIO
P
Digital IO Supply
3
E3
9
IDB0
DI
MIPI RFFE ID Bit 0 (Note 3)
VIO
C2
10
GNDIO
P
Digital IO Ground
VIO
D2
11
OUTA
AOH
High Voltage Output A
VHV
E2
12
OUTB
AOH
High Voltage Output B
VHV
E1
13
OUTC
AOH
High Voltage Output C
VHV
D1
14
OUTD
AOH
High Voltage Output D
VHV
C1
15
OUTE
AOH
High Voltage Output E
VHV
B1
16
OUTF
AOH
High Voltage Output F
VHV
A1
17
ATEST
AO
Analog Test Out (Note 4)
VREG
B2
18
VREG
AO
Regulator Output
3.6
A2
19
GND_BOOST
P
Ground for Booster
0
A3
20
VHV
AOH / AIH
Boost High Voltage can be Forced Externally
25
A4
For information only.
To be grounded when not in use.
This pin has to be connected to either GNDIO or VIO level, even if only SPI protocol is used. Never let it float.
To be grounded in normal operation.
Electrical Performance Specifications
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Unit
Analog Supply Voltage
−0.3 to +6.0
V
VIO
IO Reference Supply Voltage
−0.3 to +3.6
V
VI/O
Input Voltage Logic Lines (DATA, CLK, CS)
−0.3 to VIO+0.3
V
−0.3 to 30
V
2,000
V
200
V
−55 to +150
°C
+110
°C
AVDD
VHVH
Parameter
VHV Maximum Voltage
VESD (HBM)
Human Body Model, JESD22−A114, All I/O
VESD (MM)
Machine Model, JESD22−A115
TSTG
TAMB_OP_MAX
Storage Temperature
Max Operating Ambient Temperature without Damage
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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TCC−106
Table 3. RECOMENDED OPERATING CONDITIONS
Rating
Symbol
Parameter
Min
Typ
Max
Unit
TAMB_OP
Operating Ambient Temperature
−30
−
+85
°C
TJ_OP
Operating Junction Temperature
−30
−
+125
°C
AVDD
Analog Supply Voltage
2.3
−
5.5
V
IO Reference Supply Voltage
1.1
−
3.0
V
VIO
Table 4. DC CHARACTERISTICS (TA = −30 to +85°C; VOUTX = 15 V for each output; 2.3 V<AVDD< 5.5 V; 1.1 V<VIO<3.0 V; RLOAD
= equivalent series load of 5.6 kohm and 2.7 nF; CHV = 22 nF; LBOOST = 15 mH; TRIG pin grounded; unless otherwise specified)
Parameter
Min
Typ
Max
Unit
Comment
AVDD Supply Current
−
−
1.5
mA
VIO Supply is Low
L_BOOST Leakage
−
−
1.5
Battery Current
−
−
2.5
IVIO
VIO Supply Current
−1
−
1
ICLK
CLK Leakage
−1
−
1
IDATA
DATA Leakage
−1
−
1
Average battery current, 3 outputs actively switching 16 V for 1205 ms to 2 V
for 1705 ms to 8 V for 1705 ms and 3
outputs are @ 16 V steady state
−
1,760
2,350
mA
At VHV = 20 V
AVDD = 3.3 V
IBATT_SS0
Average battery current, 6 outputs @
0 V steady state
−
800
1,130
IBAT_SS2
Average battery current, 6 outputs @
2 V steady state
−
850
1,200
IBATT_SS16
Average battery current, 6 outputs @
16 V steady state
−
1,190
1,560
At VHV = 20 V
AVDD = 3.3 V
IL_BOOST
Average inductor current, 3 outputs actively switching 16 V for 1205 ms to 2 V
for 1705 ms to 8 V for 1705 ms and 3
outputs are @ 16 V steady state
−
1,480
2,050
At VHV = 20 V
AVDD = 3.3 V
IL_BOOST_SS0
Average inductor current, 6 outputs @
0 V steady state
−
500
790
At VHV = 20 V
AVDD = 3.3 V
IL_BOOST_SS2
Average inductor current, 6 outputs @
2 V steady state
−
560
850
At VHV = 20 V
AVDD = 3.3 V
IL_BOOST_SS16
Average inductor current, 6 outputs @
16 V steady state
−
930
1,270
At VHV = 20 V
AVDD = 3.3 V
IVIO_INACT
VIO average inactive current
−
−
3
VIO is high, no bus activity
IVIO_ACTIVE
VIO average active current
−
−
250
VIO = 1.8 V, master sending
data at 26 MHz
2.05
−
2.3
V
AVDD Supply Current
−
−
8
mA
L_BOOST Leakage
−
−
6
Battery Current
−
−
14
IAVDD + IL_BOOST
VIO Supply Current
−
−
3
No bus activity
2.0
−
3.3
Symbol
SHUTDOWN MODE
IAVDD
IL_BOOST
IBATT
ACTIVE MODE
IBATT
VVREG
At VHV = 20 V
AVDD = 3.3 V
mA
At VHV = 20 V
AVDD = 3.3 V
No external load allowed
LOW POWER MODE
IAVDD
IL_BOOST
IBATT
IVIO
VVREG
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4
V
No external load allowed
TCC−106
Table 5. BOOST CONVERTER CHARACTERISTICS
(AVDD from 2.3 V to 5.5 V; VIO from 1.1 V to 3.0 V; TA = –30 to +85°C; CHV = 22 nF; LBOOST = 15 mH; unless otherwise specified)
Symbol
Conditions
Min
Typ
Max
Unit
VHV_min
Minimum programmable output voltage (average), DAC Boost = 0h
Parameter
Active mode
−
9
−
V
VHV_max
Maximum programmable output voltage (average), DAC Boost = Fh
Active mode
−
24
−
Resolution
Boost voltage resolution
4−bit DAC
−
1
−
−
200
−
IL_BOOST_LIMIT
Inductor current limit
mA
Table 6. ANALOG OUTPUTS (OUT A, OUT B, OUT C)
(AVDD from 2.3 V to 5.5 V; VIO from 1.1 V to 3.0 V; VHV = 24 V; TA = –30 to +85°C; Rload = ∞ unless otherwise specified)
Description
Parameter
Min
Typ
Max
Unit
7
−
−
megaohm
Comment
SHUTDOWN MODE
ZOUT
OUT A, OUT B, OUT C , OUT D,
OUT E,OUT F output impedance
DAC disabled
ACTIVE MODE
VOH
Maximum output voltage
22.0
−
−
V
DAC A, B, C, D, E or F = 7Fh,
DAC Boost = Fh, IOH<10 mA
VOL
Minimum output voltage
−
−
1
V
DAC A, B C, D, E or F = 01h, DAC
Boost = 0h to Fh, IOH<10 mA
−
6.5
10
ms
2 V to 20 V step, measured at
VOUT = 15.2 V,
RLOAD = equivalent series load of
2.7 kohm and 5.6 nF, Turbo enabled
OUT A, OUT B, OUT C, OUT D,
OUT E, OUT F set in pull−down
mode
−
−
800
ohm
DAC A, B C, D, E or F = 00h, DAC
Boost = 0h to Fh, selected output(s)
is disabled
Voltage resolution (1−bit)
−
188
−
mV
(1 LSB = 1−bit)
Zero scale, least squared best fit
−1
−
+1
LSB
−3.0
−
+3.0
%VOUT
Over 2 V – 20 V VO range
−0.9
−
+0.9
LSB
Over 2 V – 20 V VO range
Slew Rate
RPD
Resolution
VOFFSET
Error
DNL
Differential non−linearity least
squared best fit
INL
Integral non−linearity least squared
best fit
−1
−
+1
LSB
Over 2 V – 20 V VO range
ISC
Over current protection
−
35
65
mA
Any DAC output shorted to ground
Output ripple with all outputs at
steady state
−
−
40
mV RMS
Over 2 V – 20 V for VHV = 23.5 V
VRIPPLE
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TCC−106
Theory of Operation
Overview
2. Startup Mode: Startup is only a transitory mode.
Startup mode is entered upon a VIO high state. In
startup mode all registers are reset to their default
states, the digital interface is functional, the boost
converter is activated, outputs OUT A, OUT B,
OUT C, OUT D, OUT E and OUT F are disabled
and the DAC outputs are placed in a high Z state.
Control software can request a full hardware and
register reset of the TCC−106 by sending an
appropriate PWR_MODE command to direct the
chip from either the active mode or the low power
mode to the startup mode. From the startup mode
the device automatically proceeds to the active mode.
3. Active Mode: All blocks of the TCC−106 are
activated and the DAC outputs are fully controlled
through the digital interface, DACs remain off
until enabled. The DAC settings can be
dynamically modified and the HV outputs will be
adjusted according to the specified timing
diagrams. Each DAC can be individually
controlled and/or switched off according to
application requirements. Active mode is
automatically entered from the startup mode.
Active mode can also be entered from the low
power mode under control software command.
4. Low Power Mode: In low power mode the serial
interface stays enabled, the DAC outputs are
disabled and are placed in a high Z state and the
boost voltage circuit is disabled. Control software
can request to enter the low power mode from the
active mode by sending an appropriate
PWR_MODE command. The contents of all
registers are maintained in the low power mode.
The control IC outputs are directly controlled by
programming the six DACs (DAC A, DAC B, DAC C, DAC
D, DAC E and DAC F) through the digital interface.
The DAC stages are driven from a reference voltage,
generating an analog output voltage driving a high−voltage
amplifier supplied from the boost converter (see Figure 1 −
Control IC Functional Block Diagram).
The control IC output voltages are scaled from 0 V to
24 V, with 128 steps of 188 mV (2 V x 24 V / 255 V =
0.188235 V). The nominal control IC output can be
approximated to 188 mV x (DAC value).
For performance optimization the boost output voltage
(VHV) can be programmed to levels between 9 V and 24 V
via the DAC_boost register (4 bits with 1 V steps). The
startup default level for the boosted voltage is VHV = 24 V.
For proper operation and to avoid saturation of the output
devices and noise issues it is recommended to operate the
boosted VHV voltage at least 2 V above the highest
programmed VOUT voltage of any of the six outputs.
When the DAC output value is set to 00h the
corresponding output is disabled and the output is pulled to
GND through an effective impedance of less than 800 ohms.
Operating Modes
The following operating modes are available:
1. Shutdown Mode: All circuit blocks are off, the
DAC outputs are disabled and placed in high Z
state and current consumption is limited to
minimal leakage current. The shutdown mode is
entered upon initial application of AVDD or upon
VIO being placed in the low state. The contents of
the registers are not maintained in shutdown mode.
Battery insertion
VDDA = 0
VIO = HIGH
Startup
(Registers reset)
Shutdown
PWR_MODE =
0b01
VIO = LOW
PWR_MODE =
0b01
VIO = LOW
automatic
PWR_MODE = 0b00
Active
(User Defined)
Low Power
(User Defined)
PWR_MODE = 0b10
Figure 2. Modes of Operation
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TCC−106
AVDD Power−On Reset (POR)
VIO Power−On Reset and Startup Conditions
Upon application of AVDD the TCC−106 will be in
shutdown mode. All circuit blocks are off and the chip draws
only minimal leakage current.
A high level on VIO places the chip in startup mode which
provides a POR to the TCC−106. POR resets all registers to
their default settings as described in Table 8. VIO POR also
resets the serial interface circuitry. POR is not a brown−out
detector and VIO needs to be brought back to a low level to
enable the POR to trigger again.
Table 7. VIO POWER−ON RESET AND STARTUP
Register
Default State for
VIO POR
DAC Boost
[1111]
Power Mode
[01]>[00]
Transitions from shutdown to startup and then automatically to active mode
DAC Enable
[000000]
VOUT A, B, C, D, E and F Disabled
Comment
VHV = 24 V
DAC A
Output in High−Z Mode
DAC B
Output in High−Z Mode
DAC C
Output in High−Z Mode
DAC D
Output in High−Z Mode
DAC E
Output in High−Z Mode
DAC F
Output in High−Z Mode
VIO Shutdown
A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the
registers are not maintained in shutdown mode.
Table 8. VIO THRESHOLDS (AVDD from 2.3 V to 5.5 V; TA = –30 to +85°C unless otherwise specified)
Parameter
Description
Min
Typ
Max
Unit
VIORST
VIO Low Threshold
−
−
0.2
V
Comments
When VIO is lowered below this threshold level the
chip is reset and placed into the shutdown state
Power Supply Sequencing
The AVDD input is typically directly supplied from the battery and thus is the first on. After AVDD is applied and before VIO
is applied to the chip, all circuits are in the shutdown state and draw minimum leakage currents. Upon application of VIO, the
chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface.
Table 9. TIMING (AVDD from 2.3 V to 5.5 V; VIO from 1.1 V to 3.0 V; TA = –30 to +85°C; OUT A, OUT B, OUT C, OUT D, OUT E &
OUT F; CHV = 22 nF; LBOOST = 15 mH; VHV = 20 V; Turbo−Charge mode off unless otherwise specified)
Parameter
Description
Min
Typ
Max
Unit
Comments
TPOR_VREG
Internal bias settling time from shutdown to active mode
−
50
120
ms
For info only
Time to charge CHV @ 95% of set VHV
−
130
−
ms
For info only
Startup time from shutdown to active mode
−
180
300
ms
TSET+
Output A, B, C, D, E, F positive settling time to within
5% of the delta voltage, equivalent series load of
2.7 kohm and 5.6 nF, VOUT from 2 V to 20 V; 0Bh
(11d) to 55h (85d)
−
50
60
ms
Voltage settling time
connected on VOUT
A, B, C, D, E, F
TSET−
Output A, B, C, D, E, F negative settling time to within
5% of the delta voltage, equivalent series load of
2.7 kohm and 5.6 nF, VOUT from 20 V to 2 V; 55h
(85d) to 0Bh (11d)
−
50
60
ms
Voltage settling time
connected on VOUT
A, B, C, D, E, F
TSET+
Output A, B, C, D, E, F positive settling time with Turbo
−
35
−
ms
Voltage settling time
connected on VOUT
A, B, C, D, E, F
TSET−
Output A, B, C, D, E, F negative settling time with Turbo
−
35
−
ms
Voltage settling time
connected on VOUT
A, B, C, D, E, F
TBOOST_START
TSD_TO_ACT
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TCC−106
Figure 3. Output Settling Diagram
Figure 4. Startup Timing Diagram
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TCC−106
Boost Control
Due to the slow response time of the control loop, the
VHV voltage may drop below the set voltage before the
control loop compensates for it. In the same manner, VHV
can rise higher than the set value. This effect may reduce the
maximum output voltage available. Please refer to Figure 6
below.
The asynchronous control reduces switching losses and
improves the output (VHV) regulation of the DC/DC
converter under light load, particularly in the situation
where the TCC−106 only maintains the output voltages to
fixed values.
The TCC−106 integrates an asynchronous current control
boost converter. It operates in a discontinuous mode and
features spread−spectrum circuitry for Electro−Magnetic
Interference (EMI) reduction. The average boost clock is
2 MHz and the clock is spread between 0.8 MHz and 3.2 MHz.
Boost Output Voltage (VHV) Control Principle
The asynchronous control starts the boost converter as
soon as the VHV voltage drops below the reference set by
the 4−bit DAC and stops the boost converter when the VHV
voltage rises above the reference again.
CHV
Recharge
CHV
Discharge
VHV
Set VHV
Delay
Delay
Delay
Time
Boost
Running
Figure 5. VHV Voltage Waveform
High Impedance (High Z) Feature
In shutdown mode the OUT pins are set to a high
impedance mode (high Z). Following is the principle of
operation for the control IC:
1. The DAC output voltage VOUT is defined by:
V OUT +
DAC code
255
24 V
2
(eq. 1)
2. The voltage VHV defines the maximum supply
voltage of the DAC supply output regulator and is
set by a 4−bit control.
3. The maximum DAC DC output voltage VOUT is
limited to (VHV – 2 V).
4. The minimum output DAC voltage VOUT is 1.0 V
max.
Figure 7. DAC Output Range Example B
Digital Interface
The control IC is fully controlled through a digital
interface (DATA, CLK, CS). The digital interface auto−
matically detects and responds to MIPI RFFE interface
commands, 3−wire 30−bit serial interface commands or
3−wire 32−bit serial interface commands. Auto−detection is
accomplished on a frame by frame basis. The digital
interface is described in the following sections of this
document, for detailed programming instructions please
refer to the programming guide, available by contacting
ON Semiconductor.
3−Wire Serial Interface
The 3−wire serial interface operates in a synchronous
write−only 3−wire slave mode. 30−bit or 32−bit message
length is automatically detected for each frame. If CS
changes state before all bits are received then all data bits are
ignored. Data is transmitted most significant bit first and
DATA is latched on the rising edge of CLK. Commands are
latched on the falling edge of CS.
Figure 6. DAC Output Range Example A
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TCC−106
Table 10. 3−WIRE SERIAL INTERFACE SPECIFICATION
(TA = −30 to +85°C; 2.3 V<AVDD<5.5 V; 1.1 V<VIO<3.0 V; unless otherwise specified)
Parameter
Description
Min
Typ
Max
Unit
−
−
26
MHz
FCLK
Clock Frequency
TCLK
Clock Period
38.4
−
−
ns
NBIT
Bits Number
−
30/32
−
bits
Comments
Auto−detection 30−bit or
32−bit
THIGH
Clock High Time
13
−
−
ns
TLOW
Clock Low Time
13
−
−
ns
TCSSETUP
CS Set−up Time
5
−
−
ns
70% rising edge of CS to
30% rising edge of first
clock cycle
TCSHOLD
CS Hold Time
5
−
−
ns
30% falling edge of last
clock cycle to 70% falling
edge of CS
TDSETUP
Data Set−up Time
4
−
−
ns
Relative to 30% of CLK
rising edge
TDHOLD
Data Hold Time
4
−
−
ns
relative to 70% of CLK rising edge
TSUCC
CS Low Time Between
Successive Writes
38.4
−
−
ns
70% falling edge of CS to
70% rising edge of CS
TSUCC
CS Low Time Between
Successive DAC Update Writes
1,500
−
−
ns
Time between groups of
DAC update reg [00000] &
[00001] writes
CCLK
Input Capacitance
−
−
5
pF
CLK pin
CDATA
Input Capacitance
−
−
8.3
pF
DATA pin
CCS
Input Capacitance
−
−
5
pF
CS pin
CTRIG
Input Capacitance
−
−
10
pF
TRIG pin
V
DATA, CLK, CS
VIH
Input Logic Level High
0.7 x VIO
−
VIO + 0.3
VIL
Input Logic Level Low
−0.3
−
0.3 x VIO
V
DATA, CLK, CS
IIH_DATA
Input Current High
−2
−
10
mA
DATA
IIL_DATA
Input Current Low
−2
−
1
mA
DATA
IIH_CLK,CS
Input Current High
−1
−
10
mA
CLK, CS
IIL_CLK,CS
Input Current Low
−1
−
1
mA
CLK, CS
VTP_TRIG
Positive Going Threshold Voltage
0.4 x VIO
−
0.7 x VIO
V
TRIG
VTN_TRIG
Negative Going Threshold Voltage
0.3 x VIO
−
0.6 x VIO
V
TRIG
VH_TRIG
Hysteresis Voltage (VTP – VTN)
0.1 x VIO
−
0.4 x VIO
V
TRIG
IIH_TRIG
TRIG Input Current High
−2
−
10
mA
TRIG=0.8 x VIO
IIL_TRIG
TRIG Input Current Low
−2
−
1
mA
TRIG=0.2 x VIO
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TCC−106
Figure 8. 3−wire Serial Interface Signal Timing
SPI Frame Length Decoding
rising edges while CS is kept high. The TCC−106 will not
respond to a SPI command if the length of the frame is not
exactly 30 bits or 32 bits. SPI registers are write only.
30−bit or 32−bit frame length is automatically detected.
The length of the frame is defined by the number of clock
SPI Frame Structure
Table 11. 32 BITS FRAME: ADDRESS DECODING (1, 2, 3, 4, 5 or 6 OUTPUTS)
H0
H1
R/W
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
1
0
1
0
1
0
0
1
0
0
X
X
X
X
X
ON Semiconductor Header
R/W
Device ID
Specific Device ID
Register Address for Operation
Table 12. 30 BITS FRAME: ADDRESS DECODING (1, 2, 3, 4, 5 or 6 OUTPUTS)
R/W
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
1
0
0
1
0
0
X
X
X
X
X
R/W
Device ID
Specific Device ID
Register Address for Operation
Table 13. 3−WIRE SERIAL INTERFACE ADDRESS MAP
A4
A3
A2
A1
A0
Data[15:8]
Data[7:0]
0
0
0
0
0
Turbo−Charge Settings for DAC A, B, C
DAC C
0
0
0
0
1
DAC B
DAC A
0
0
0
1
0
Turbo−Charge Settings for DAC D, E, F
DAC F
0
0
0
1
1
DAC E
DAC D
0
0
1
0
0
Turbo−Charge Delay Parameters for DAC A, B, C
Turbo Threshold Delay Settings for A, B, C
0
0
1
0
1
Turbo−Charge Delay Parameters for DAC D, E, F
Turbo Threshold Delay Settings for A, B, C
1
0
0
0
0
Mode Select + Control IC Setup
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11
TCC−106
Table 13. 3−WIRE SERIAL INTERFACE ADDRESS MAP
1
0
0
1
0
1
1
Reserved
Reserved
to
1
1
1
Turbo−Charge Mode
The TCC−106 control IC has a Turbo−Charge mode that
significantly shortens the system settling time when
changing programming voltages. In Turbo−Charge mode
the DAC output target voltage is temporarily set to either a
delta voltage above or a delta voltage below the actual
desired target for the TCDLY time. It is recommended that
VHV be set to 24 V when using Turbo−Charge mode.
During glide mode the output voltage of a DAC is either
increased or decreased to its set end point, in max 255 steps,
where each DAC time step can be programmed between
2 ms to 64 ms. For programming the glide mode refer to the
application note (coming soon). A programming input is not
required to maintain a glide transition, all step controls are
maintained by the part. Only the inputs to define the glide
need to be programmed.
Glide Mode
RF Front−End Control Interface (MIPI RFFE Interface)
Unlike turbo mode, which is intended to reduce the
charging time, the glide mode extends the transition time of
each DAC output. Each DAC has an individual control for
turbo mode, glide mode or regular voltage switching. The
glide mode can be enabled for a particular DAC through the
INDEX register, by setting DAC State to ‘1’ when glide
mode is enabled, turbo mode is off for a particular DAC, but
one DAC can be gliding while the other is turbo.
The TCC−106 is a read/write slave device which is fully
compliant to the MIPI Alliance Specification for RF
Front−End Control Interface (RFFE) Version 1.10.00 26
July 2011. This device is rated at full−speed operation for
1.65 V<VIO<1.95 V and at half−speed operation for
1.1 V<VIO<1.65 V. When using the MIPI RFFE interface
the CS pin must be grounded externally.
CLK
TDSETUP
TDSETUP
TDHOLD
TDHOLD
DATA
Figure 9. MIPI−RFFE Signal Timing during Master Writes to PTIC Control IC
CLK
CLK
TREAD_ACCESS
TSDATAOTR
TREAD_ACCESS
TSDATAZ
TSDATAOTR
DATA
DATA
Bus Park Cycle
Figure 10. MIPI−RFFE Signal Timing during Master
Reads from PTIC Control IC
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12
Figure 11. Bus Park Cycle Timing
when MIPI−RFFE Master Reads
from PTIC Control IC
TCC−106
Table 14. MIPI RFFE INTERFACE SPECIFICATION
(TA = −30 to +85°C; 2.3 V<AVDD<5.5 V; 1.1 V<VIO<1.95 V; unless otherwise specified)
Parameter
Min
Typ
Max
Unit
FSCLK
Clock Full−Speed
Frequency
Description
0.032
−
26
MHz
Full−Speed Operation:
1.65 V<VIO<1.95 V
Comments
TSCLK
Clock Full−Speed Period
0.038
−
32
ms
Full−Speed Operation:
1.65 V<VIO<1.95 V
TSCLKIH
CLK Input High Time
11.25
−
−
ns
Full−Speed
TSCLKIL
CLK Input Low Time
11.25
−
−
ns
Full−Speed
FSCLK_HALF
Clock Half−Speed
Frequency
0.032
−
13
MHz
TSCLK_HALF
Clock Half−Speed Period
0.038
−
64
ms
TSCLKIH
CLK Input High Time
24
−
−
ns
Half−Speed
TSCLKIL
CLK Input Low Time
24
−
−
ns
Half−Speed
VTP
Positive Going Threshold
Voltage
0.4 x VIO
−
0.7 x VIO
V
CLK, DATA, TRIG, 1.2 or 1.8 V Bus
VTN
Negative Going Threshold Voltage
0.3 x VIO
−
0.6 x VIO
V
CLK, DATA, TRIG, 1.2 or 1.8 V Bus
VH
Hysteresis Voltage
(VTP – VTN)
0.1 x VIO
−
0.4 x VIO
V
CLK, DATA, TRIG, 1.2 or 1.8 V Bus
IIH
Input Current High
−2
−
+10
mA
TRIG,SDATA = 0.8 x VIO
−1
−
+10
mA
SCLK = 0.8 x VIO
−2
−
+1
mA
TRIG,SDATA = 0.2 x VIO
−1
−
+1
mA
SCLK=0.2 x VIO
IIL
Input Current Low
CCLK
Input Capacitance
−
−
5
pF
CLK Pin
CDATA
Input Capacitance
−
−
8.3
pF
DATA Pin
CTRIG
Input Capacitance
−
−
10
pF
TRIG Pin
TDSETUP
Write DATA Setup Time
1
−
−
ns
Full−Speed
TDHOLD
Write DATA Hold Time
5
−
−
ns
Full−Speed
TDSETUP
Write DATA Setup Time
2
−
−
ns
Half−Speed
TDHOLD
Write DATA Hold Time
Half−Speed
TSUCC
TREAD_ACCESS
TSDATAOTR
TSDATAZ
TREAD_ACCESS
TSDATAOTR
TSDATAZ
5
−
−
ns
1,500
−
−
ns
Read DATA valid from
CLK rising edge
−
−
100
ns
Full or Half Speed at VIO = 1.10 V,
and max 15 pF load on DATA pin
Read DATA output
transition
−
−
65
ns
Full or Half Speed at VIO = 1.10 V,
and max 15 pF load on DATA pin
Read DATA drive
release time
−
−
180
ns
Full or Half Speed at VIO = 1.10 V,
and max 15 pF load on DATA pin
Read DATA valid from
CLK rising edge
−
−
31
ns
Full or Half Speed at VIO = 1.80 V,
and max 15 pF load on DATA pin
Read DATA output
transition
−
−
14
ns
Full or Half Speed at VIO = 1.80 V,
and max 15 pF load on DATA pin
Read DATA drive
release time
−
−
50
ns
Full or Half Speed at VIO = 1.80 V,
and max 15 pF load on DATA pin
Time Between Successive DAC Update Writes
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13
TCC−106
The control IC contains twenty−four 8−bit registers. Register content is described in Table 15. Some additional registers
implemented as provision, are not described in this document.
Table 15. MIPI RFFE ADDRESS MAP
Register
Address
Description
Purpose
Access
Type
Size (bits)
0x00
DAC Configuration (Enable Mask)
High voltage output enable mask
Write
7
0x01
Turbo Register DAC A, B & C
Turbo−charge configuration DAC A, B & C
Write
8
0x02
DAC A Register
OUT A value [6:0], Turbo Index [7]**
Write
8
0x03
DAC B Register
OUT B value [6:0], Turbo Index [7]**
Write
8
0x04
DAC C Register
OUT C value [6:0], Turbo Index [7]**
Write
8
0x05
Turbo Register DAC D, E & F
Turbo−charge configuration DAC D,E & F
Write
8
0x06
DAC D Register
OUT D value [6:0], Turbo Index [7]**
Write
8
0x07
DAC E Register
OUT E value [6:0], Turbo Index [7]**
Write
8
0x08
DAC F Register
OUT F value [6:0], Turbo Index [7]**
Write
8
0x10
DAC Boost (VHV)
Settings for the boost high voltage
Write
8
0x11
Trigger register
Trigger configuration
Write
8
0x12
Turbo−Charge Delay DAC A, B, C
Turbo−charge delay steps
DAC A, B, C
Write
8
0x13
Turbo−Charge Delay DAC A, B, C
Turbo−charge delay, multiplication
DAC A, B, C
Write
8
0X14
Turbo−Charge Delay DAC D, E, F
Turbo−charge delay steps
DAC D, E, F
Write
8
0X15
Turbo−Charge Delay DAC D, E, F
Turbo−charge delay multiplication
DAC D, E, F
Write
8
0x1C
Power Mode and Trigger Register
Power mode & trigger control
PWR_MODE [7:6]
TRIG_REG [5:0]
Write
8
0x1D
Product ID Register
Product number *
Hard coded into ASIC
Write
8
0x1E
Manufacturer ID Register
MN (10 bits long)
Manufacturer ID[7:0]
Hard Coded into ASIC
Write
8
0x1F
Unique Slave Identifier Register (USID)
Spare [7:6]
[5,4] = Manufacturer ID [9:8]
USID [3:0]
Write
8
*The second least significant bit can be programmed in OTP during manufacture
** The details for configuration of Turbo mode should be ascertained from the Programming Guide, available from ON Semiconductor
Configuration Settings
Table 16. DAC CONFIGURATION (ENABLE MASK) at [0x00] Defaults shown as (x)
Bit 6 (1)
Bit 5 (0)
Bit 4 (0)
Bit 3 (0)
Bit 2 (0)
Bit 1 (0)
Bit 0 (0)
SSE
DAC E
DAC F
DAC A
DAC B
DAC C
DAC D
SSE = 0 spread spectrum disabled, SSE = 1 spread spectrum enabled (default), this controls the average boost clock which
is nominally 2 MHz and spread between 0.8 MHz and 3.2 MHz when enabled (default). The hardware does not limit driving
more than three DACs at the same time, however it is recommended to have max three DACs changing outputs at one time,
no restrictions exist as to which three.
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14
TCC−106
Table 17. DAC MODE SETUP: DAC ENABLE
Bit3
Bit2
Bit1
DAC A
DAC B
DAC C
0
0
0
Off
Off
Off
0
0
1
Off
Off
Enabled
0
1
0
Off
Enabled
Off
0
1
1
Off
Enabled
Enabled
1
0
0
Enabled
Off
Off
1
0
1
Enabled
Off
Enabled
1
1
0
Enabled
Enabled
Off
1
1
1
Enabled
Enabled
Enabled
(Default)
Table 18. DAC MODE SETUP: DAC ENABLE
Bit5
Bit4
Bit0
DAC E
DAC F
DAC D
0
0
0
Off
Off
Off
0
0
1
Off
Off
Enabled
0
1
0
Off
Enabled
Off
0
1
1
Off
Enabled
Enabled
1
0
0
Enabled
Off
Off
1
0
1
Enabled
Off
Enabled
1
1
0
Enabled
Enabled
Off
1
1
1
Enabled
Enabled
Enabled
(Default)
Table 19. BOOST DAC MODE SETUP (VHV) at [0x10] (Note 5)
Bit 7*
Bit 6*
Bit 5*
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VHV (V)
0
0
0
1
0
0
0
0
9
0
0
0
1
0
0
0
1
10
0
0
0
1
0
0
1
0
11
0
0
0
1
0
0
1
1
12
0
0
0
1
0
1
0
0
13
0
0
0
1
0
1
0
1
14
0
0
0
1
0
1
1
0
15
0
0
0
1
0
1
1
1
16
0
0
0
1
1
0
0
0
17
0
0
0
1
1
0
0
1
18
0
0
0
1
1
0
1
0
19
0
0
0
1
1
0
1
1
20
0
0
0
1
1
1
0
0
21
0
0
0
1
1
1
0
1
22
0
0
0
1
1
1
1
0
23
0
0
0
1
1
1
1
1
24 (Default)
5. Bit 4 is fixed at logic 1 for reverse software compatibility
*Indicates reserved bits
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15
TCC−106
MIPI RFFE TRIG Operation
improve interfacing options the polarity of external TRIG is
programmable via [0x11] bit 1.
If the external trigger function is not needed in the
application, the TRIG pin should be grounded and the TRIG
function disabled. When TRIG pin is disabled by register
[0x11] ‘TRIG Select’ = ‘1’ (default) and register [0x10]
‘Trigger Mask 0, 1, 2’ = ‘1’:
• The requested DAC voltage levels for DAC A, B, C are
applied to the outputs all together at the same time,
after DAC C value is written. This event will not affect
the outputs of DAC D, E, F.
• The requested DAC voltage levels for DAC D, E, F are
applied to the outputs all together at the same time,
after DAC F value is written. This event will not affect
the outputs of DAC A, B, C.
• Optionally a configuration register can select the last
DAC to be written in order to trigger internally the
update of all six DACs at the same time. For example
the configuration register can select that a write to DAC
B value will trigger internally the update of all six
DACs outputs.
The MIPI RFFE Trigger mode can be used as a
synchronization signal to ensure that new DAC settings are
applied to the outputs at appropriate times in the overall
transceiver system. When the MIPI RFFE TRIG function is
enabled via [0x11] bit 4 the requested DAC voltage levels
are set up in the shadow registers and not transferred to the
destination registers until the trigger condition is met. In this
manner the change in output voltage levels are synchronized
with the MIPI RFFE TRIG command. If multiple DAC
voltage level requests are received before the TRIG event
occurs, only the last fully received DAC output voltage level
will be applied to the outputs.
The trigger configuration also provides for an additional
external TRIG pin to be used as a synchronization signal.
The external TRIG is independent from the built−in triggers
available within the MIPI RFFE interface. When the TRIG
input pin is enabled via [0x11] bit 4 the requested DAC
voltage levels are set up in the shadow registers and are not
transferred to the destination registers until the external
trigger condition is met. In this manner the change in output
voltage levels are synchronized with the external TRIG
event. The external TRIG input is referenced to VIO. To
Table 20. TRIGGER CONFIGURATION at [0x11]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Res*
0
Res*
0
Res*
0
TRIG Select
0 = Ext TRIG Pin
1 = RFFE Trigger
Bit 2
Reserved
0
Bit 1
Bit 0
TRIG Edge
0 = Active Falling
1 = Active Rising
Mask Ext TRIG
1 = Mask Trig Pin
*Reserved bits
Table 21. EXTERNAL TRIGGER CONFIGURATION BIT SETTING AT [0x11]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
0
−
−
X
0
External trigger pin is enabled. Sending the RFFE message will load a ‘shadow’
register only. Only upon an active signal on external TRIG pin are the output registers loaded with the new voltage settings which are then applied to the outputs.
1
−
−
X
X
The MIPI RFFE trigger is enabled (Default)
0
−
−
0
0
External TRIG pin signal is active falling
0
−
−
1
0
External TRIG pin signal is active rising (Default)
X
−
−
X
0
External trigger pin is not masked
X
−
−
X
1
Mask external trigger pin (Default)
Table 22. POWER MODE AND TRIGGER REGISTER [0x1C]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PM1
PM0
Trigger Mask 2
Trigger Mask 1
Trigger Mask 0
Trigger 2
Trigger 1
Trigger 0
All three triggers behave in the same way as the external
pin TRIG. When each of these triggers is set using the MIPI
RFFE interface the results are the same as when an active
edge is applied to the TRIG pin when external pin TRIG is
selected
Writing a logic one (‘1’) to the bits 0, 1 or 2 (Trigger 0, 1
or 2) moves data from the shadow registers into the
destination registers. Default for bit 0, 1 and 2 is logic low.
If trigger mask bit 0, 1 or 2 is set (‘1’) the trigger 0, 1 or
2 are disabled respectively and the data goes directly to the
destination register. Default for bit 3, 4 and 5 is logic low.
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16
TCC−106
Table 23. POWER MODE BIT SETTING IN REGISTER [0x1C]
PM1
PM0
State
Description
0
0
Active
Boost Control Active, VHV set by Digital Interface
VOUT A, B, C, D, E, F Enabled and Controlled by Digital Interface (Default)
0
1
Startup
Boost Control Active, VHV set by Digital Interface
VOUT A, B, C, D, E, F Disabled
1
0
Low Power
1
1
Reserved
Digital Interface is Active While All Other Circuits are in Low Power Mode
State of Hardware Does Not Change
Command Sequences
Register 0 Write Command Sequence
• Register 0 Write (used to access the Register 0 DAC
•
•
The Command Sequence starts with a Sequence Start
Condition (SSC) which is followed by the Register 0 Write
Command Frame. This Frame contains the Slave address, a
logic one, and the seven bit word that will be written to
Register 0. The Command Sequence is depicted below.
Configuration − Enable Mask). Register 0 can be also
be accessed using Register Write or/and Extended
Register Write.
Register Write (used to access only one register at the
time)
Extended Register Write (used to access a group of
contiguous registers with one command)
Figure 12. Register 0 Write Command Sequence
Table 24. MIPI RFFE COMMAND FRAME FOR REGISTER 0 WRITE COMMAND SEQUENCE
Description
SSC
SSE & DAC
Configuration
1
0
Command Frame
SA [3,0]
1
SSE
DAC_E
DAC_F
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17
DAC_A
BP
DAC_B
DAC_C
DAC_D
P
BP
TCC−106
Register Write Command Sequence
The write register command sequence may be used to access each register (addresses 0−31).
Figure 13. Register Write Command Sequence
Table 25. MIPI RFFE COMMAND FRAME FOR REGISTER WRITE COMMAND SENTENCE
Description
SSC
Command Frame
Data Frame
BP
Turbo−Charge
Settings
1
0
SA
[3,0]
0
1
0
0
0
0
0
1
P
TC_INDX_L [7:0]
P
BP
Register Write
DAC A
1
0
SA
[3,0]
0
1
0
0
0
0
1
0
P
TC_INDX_L [8] & DAC_A
[6:0]
P
BP
Register Write
DAC B
1
0
SA
[3,0]
0
1
0
0
0
0
1
1
P
TC_INDX_L [9] & DAC_B
[6:0]
P
BP
Register Write
DAC C
1
0
SA
[3,0]
0
1
0
0
0
1
0
0
P
TC_INDX_L [10] & DAC_C
[6:0]
P
BP
Table 26. MIPI RFFE COMMAND FRAME FOR REGISTER WRITE COMMAND SENTENCE
Description
SSC
Command Frame
Data Frame
BP
Turbo−Charge
Settings
1
0
SA
[3,0]
0
1
0
0
0
1
0
1
P
TC_INDX_U [7:0]
P
BP
Register Write
DAC D
1
0
SA
[3,0]
0
1
0
0
0
1
1
0
P
TC_INDX_U [8] & DAC_D
[6:0]
P
BP
Register Write
DAC E
1
0
SA
[3,0]
0
1
0
0
0
1
1
1
P
TC_INDX_U [9] & DAC_E
[6:0]
P
BP
Register Write
DAC F
1
0
SA
[3,0]
0
1
0
0
1
0
0
0
P
TC_INDX_U [10] & DAC_F
[6:0]
P
BP
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18
TCC−106
Extended Register Write Command Sequence
If more than one byte is to be written, the register address
in the command sequence contains the address of the first
extended register that will be written to and the slave’s local
extended register address shall be automatically
incremented by one for each byte written up to address 0x1F,
starting from the address indicated in the address frame.
In order to access more than one register in one sequence
this message could be used. Most commonly it will be used
for loading three DAC registers at the same time. The four
LSBs of the extended register write command frame
determine the number of bytes that will be written by the
command sequence. A value of 0b0000 would write one
byte and a value of 0b1111 would write 16 bytes.
Figure 14. Extended Register Write Command Sequence
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19
TCC−106
Table 27. EXTENDED REGISTER WRITE TO UPDATE DAC A, B, C (Note 6)
Description
Extended Register
Write TC_INDX_L
and DAC A, B, C
SSC
Command Frame
Op Code
1
0
SA [3,0]
Data Frame
0
0
0
Address Frame
<Byte Count>
0
0
0
Data Frame
1
P
1
<Starting Address>
P
0
0
0
Data Frame
0
0
P
0
0
1
Data Frame
P
BP
<Data 8−bit>
P
<Data 8−bit>
P
<Data 8−bit>
P
<Data 8−bit>
P
BP
Turbo−Charge
P
DAC_A [7,0]
P
DAC_B [7,0]
P
DAC_C [7,0]
P
BP
Table 28. EXTENDED REGISTER WRITE TO UPDATE DAC D, E, F (Note 6)
Description
Extended Register
Write TC_INDX_U
and DAC D, E, F
SSC
Command Frame
Op Code
1
0
SA [3,0]
Data Frame
0
0
0
Address Frame
<Byte Count>
0
0
0
Data Frame
1
P
1
<Starting Address>
P
0
0
0
Data Frame
0
0
P
1
0
1
Data Frame
P
BP
<Data 8−bit>
P
<Data 8−bit>
P
<Data 8−bit>
P
<Data 8−bit>
P
BP
Turbo−Charge
P
DAC_D [7,0]
P
DAC_E [7,0]
P
DAC_F [7,0]
P
BP
6. The six DACs can be updated either all together in the same time by using one Extended Register Write command of 8 bytes, or separately
by using two Extended Register Write commands of 4 bytes each, where one command is to update DAC A, B, C and the other command
to update DAC D, E, F.
Figure 15. Register Read Command Sequence
Table 29. REGISTER READ COMMAND
Description
Read
MIPI−RFFE
Status Register
SSC
1
Command Frame
0
SA[3:0]
0
1
Description
Read
MIPI−RFFE
Status Register
(Continued)
1
1
1
0
1
0
P
BP
Data Frame
0
CFPE
CLE
AFPE
DFPE
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20
RURE
WURE
BGE
BP
TCC−106
Following picture shows TCC−106 and all the necessary external components
Figure 16. TCC−106 with External Components
Table 30. RECOMMENDED EXTERNAL BOM
Component
Description
CBOOST
Boost Supply Capacitor, 10 V
LBOOST
Boost Inductor
RFILT
Filtering resistor, 5%
CVIO
VIO Supply Decoupling, 10 V
Nominal Value
Package
Recommended P/N
1 mF
0402
TDK: C1005X5R1A105K
15 mH
0603
ABCO: LPS181210T−150M, Sunlord
SPH201610H150MT
3.3 ohms
0402
Vishay : CRCW04023R30JNED
100 nF
0201
Murata: GRM033R61A104ME15D
CAVDD
VAVDD Supply Decoupling, 10 V
1 mF
0402
TDK: C1005X5R1A105K
CVREG
VVREG Supply Decoupling, 10 V
220 nF
0201
TDK: C0603X5R1A224M
Boost Tank Capacitor, 50 V
47 nF
1005
Murata: GRM155C71H473KE19
Decoupling Capacitor, 50 V (Note 7)
100 pF
0201
Murata: GRM0335C1H101JD01D
CHV
CdacA,B,C,D,E,F
7. Recommended for noise reduction only – not essential
www.onsemi.com
21
TCC−106
7
L
Y
W
•
Pb-Free (96.8% Sn/2.6% Ag/0.6% Cu)
2600 mm
±10 mm
TC6x
7LYW
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
E4
500 mm
400 mm
400 mm
400 mm
MIPI RFFE ID Bit 1
250 mm dia
a = 0
530 mm
400 mm
2250 mm ±10 mm
400 mm
= Product Code
= MIPI ID
(see MIPI Version Table)
= Assembly Location
= Wafer Lot Code
= Year Code
= Week Code
= Pin 1 Marker
400 mm
TC6
x
530 mm
Mechanical Description: Ball Array Package
400 mm
500 mm
b = 1
380 mm ±25 mm
200 mm ±20 mm
Figure 17. Ball Array Package − Top View
NOTE: Die dimensions include an assumed 60 mm wide sawing kerf, this kerf width is subject to change without notice.
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22
580 mm
TCC−106
Tape & Reel Dimensions
Figure 18. WLCSP Carrier Tape Drawings
Table 31. ORDERING INFORMATION
Device
Package
Shipping†
TCC−106A−RT
RDL
(Pb−Free)
3000 / Tape & Reel
TCC−106B−RT
RDL
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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23
TCC−106
PACKAGE DIMENSIONS
WLCSP20, 2.58x2.23
CASE 567HL
ISSUE O
E
È
È
PIN A1
REFERENCE
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
DIM
A
A1
A3
b
D
E
e
D
0.05 C
2X
0.05 C
2X
MILLIMETERS
MIN
MAX
0.65
−−−
0.18
0.22
0.38 REF
0.23
0.29
2.58 BSC
2.23 BSC
0.40 BSC
TOP VIEW
A
0.10 C
A1
0.08 C
NOTE 3
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
PACKAGE
OUTLINE
A1
e/2
e
20X
0.40
PITCH
b
0.05 C A B
0.03 C
E
e
D
20X
C
0.25
B
0.40
PITCH
A
DIMENSIONS: MILLIMETERS
1
2
3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
4
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
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24
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
TCC−106/D