TCP 4133UB D

TCP-4133UB
3.3 pF Passive Tunable
Integrated Circuits (PTIC)
Introduction
ON Semiconductor’s PTICs have excellent RF performance and
power consumption, making them suitable for any mobile handset or
radio application. The fundamental building block of our PTIC
product line is a tunable material called ParaScant, based on Barium
Strontium Titanate (BST). PTICs have the ability to change their
capacitance from a supplied bias voltage generated by the Control IC.
The 3.3 pF ultra−high tuning PTICs are available as wafer-level chip
scale packages (WLCSP).
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WLCSP4
0.626x0.609
CASE 567LN
Key Features
•
•
•
•
•
•
•
Ultra−High Tuning Range and Operation up to 24 V
Usable Frequency Range: from 700 MHz to 2.7 GHz
High Quality Factor (Q) for Low Loss
High Power Handling Capability
Compatible with PTIC Control IC TCC-10x, 20x
WLCSP Package: 0.609 x 0.626 x 0.310 mm (4 bump)
These devices are Pb−Free and RoHS Compliant
MARKING DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
Typical Applications
•
•
•
•
Multi-band, Multi-standard, Advanced and Simple Mobile Phones
Tunable Antenna Matching Networks
Tunable RF Filters
Active Antennas
PTIC
RF1
RF2
Bias
PTIC Functional Block Diagram
ORDERING INFORMATION
Device
TCP−4133UB−DT
Package
Shipping†
WLCSP4
(Pb−Free)
4000 Units /
7” Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 0
1
Publication Order Number:
TCP−4133UB/D
TCP−4133UB
DC Bias 1
A1
A2
NC
RF2
B1
B2
RF1
Figure 1. PTIC Functional Block Diagram
Table 1. SIGNAL DESCRIPTIONS
Ball / Pad Number
Pin Name
A1
DC Bias 1
DC Bias Voltage
B1
RF2
RF Input / Output
A2
NC
Not Connected
B2
RF1
RF Input / Output
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2
Description
TCP−4133UB
TYPICAL SPECIFICATIONS
Representative Performance Data at 255C
Table 2. PERFORMANCE DATA
Parameter
Operating Bias Voltage
Min
Typ
1.0
Units
24
V
Capacitance (Vbias = 2 V)
2.97
3.30
3.63
pF
Capacitance (Vbias = 24 V)
0.660
0.733
0.807
pF
Tuning Range (1 V - 24 V)
4.70
5.10
5.80
Tuning Range (2 V - 24 V)
4.10
4.50
5.20
Leakage Current (WLCSP)
Operating Frequency
700
0.5
mA
2700
MHz
Quality Factor @ 700 MHz, 10 V
90
Quality Factor @ 2.4 GHz, 10 V
60
IP3 (Vbias = 2 V) [1,3]
70
dBm
80
dBm
-65
dBm
-75
dBm
-40
dBm
IP3 (Vbias = 24 V) [1,3]
2nd Harmonic (Vbias = 2 V)
[2,3]
2nd Harmonic (Vbias = 24 V)
3rd Harmonic (Vbias = 2 V)
[2,3]
[2,3]
3rd Harmonic (Vbias = 24 V)
1.
2.
3.
4.
Max
[2,3]
-70
dBm
Transition Time (Cmin ³ Cmax) [4]
80
ms
Transition Time (Cmax ³ Cmin) [4]
70
ms
f1 = 850 MHz, f2 = 860 MHz, Pin 25 dBm/Tone
850 MHz, Pin +34 dBm
IP3 and Harmonics are measured in the shunt configuration in a 50 W environment
RFIN and RFOUT are both connected to DC ground
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TCP−4133UB
Representative performance data at 255C for 3.3 pF WLCSP Package
Figure 2. Capacitance
Figure 3. Harmonic Power*
Figure 4. IP3*
Figure 5. Q*
*Data shown is representative only.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Input Power
+40
dBm
Bias Voltage
+25 (Note 5)
V
Operating Temperature Range
−30 to +85
°C
Storage Temperature Range
−55 to +125
°C
ESD − Human Body Model
Class 1B JEDEC HBM Standard (Note 6)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. WLCSP: Recommended Bias Voltage not to exceed 24 V.
6. Class 1B defined as passing 500 V, but may fail after exposure to 1000 V ESD pulse.
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TCP−4133UB
ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE
The following assembly considerations should be observed:
Cleanliness
These chips should be handled in a clean environment.
Electro-static Sensitivity
ON Semiconductor’s PTICs are ESD Class 1B sensitive.
The proper ESD handling procedures should be used.
Mounting
The WLCSP PTIC is fabricated for Flip Chip solder
mounting. Connectivity to the RF and Bias terminations on
the PTIC die is established through SAC305 solder balls
with 65 mm nominal height (45 mm to 85 mm height
variation). The PTIC die is RoHS-compliant and compatible
with lead-free soldering profile.
Molding
The PTIC die is compatible for over-molding or
under-fill.
Figure 6. Reflow Profile
ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES
RF
When configuring the PTIC in your specific circuit
design, at least one of the RF terminals must be connected
to DC ground. If minimum transition times are required, DC
ground on both RF terminals is recommended. To minimize
losses, the PTIC should be oriented such that RF2 is at the
lower RF impedance of the two RF nodes. A shunt PTIC, for
example, should have RF2 connected to RF ground.
ANT
RF1
(PTIC Pad)
RF2
(PTIC Pad)
Bias
Figure 7. PTIC Orientation Functional Block
Diagram
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TCP−4133UB
PART NUMBER DEFINITION
Table 4. PART NUMBERS
Capacitance
Part Number
TCP−4133UB-DT
2V
24 V
Package*
3.30
0.733
4-bump WLCSP
*See PTIC package dimensions on following page.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
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6
TCP−4133UB
PACKAGE DIMENSIONS
WLCSP4, 0.626x0.609
CASE 567LN
ISSUE O
È
PIN A1
REFERENCE
E
A B
4X
b1
b
0.05 C A B
4X
D
0.03 C
0.05 C
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4. BACKSIDE TAPE (OPTIONAL) APPLIED TO
IMPROVE PIN 1 MARKING.
DIM
A
A1
b
b1
D
E
e
e1
DETAIL A
2X
0.05 C
TOP VIEW
NOTE 4
TAPE
DETAIL C
A
0.06 C
0.05 C
A1
NOTE 3
SIDE VIEW
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.345
0.275
0.045
0.085
0.079
0.129
0.044
0.094
0.626 BSC
0.609 BSC
0.420 BSC
0.400 BSC
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL C
4X
0.55
0.15
A1
e
0.55
DETAIL A
e1
PACKAGE
OUTLINE
B
4X
0.13
DIMENSIONS: MILLIMETERS
A
1
2
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ParaScan is a trademark of Paratek Microwave, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
TCP−4133UB/D