NB3N51034 D

NB3N51034
3.3V, Crystal to 100MHz/
200MHz Quad HCSL/LVDS
Clock Generator
The NB3N51034 is a high precision, low phase noise clock generator
that supports spread spectrum designed for PCI Express applications.
This device takes a 25 MHz fundamental mode parallel resonant crystal
and generates 4 differential HCSL/LVDS outputs at 100 MHz or
200 MHz (See Figure 8 for LVDS interface). The NB3N51034 provides
selectable spread options of −0.5%, −1.0%, −1.5%, for applications
demanding low Electromagnetic Interference (EMI) as well as
optimum performance with no spread option.
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MARKING
DIAGRAM
NB3N
1034
ALYWG
G
Features
•
•
•
•
•
•
•
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
TSSOP−20
Power Down Mode
DT SUFFIX
CASE 948E
4 Low Skew HCSL or LVDS Outputs
A
= Assembly Location
OE Tri−States Outputs
L
= Wafer Lot
Spread of −0.5%, −1.0%, −1.5% and No Spread
Y
= Year
PCIe Gen 1, Gen 2, Gen 3 Compliant
W
= Work Week
G
= Pb−Free Package
Phase Noise (SS OFF) @ 100 MHz:
(Note:
Microdot
may be in either location)
Offset
Noise Power
100 Hz
−110 dBc/Hz
ORDERING INFORMATION
1 kHz
−123 dBc/Hz
See detailed ordering and shipping information in the package
10 kHz
−134 dBc/Hz
dimensions section on page 10 of this data sheet.
100 kHz −137 dBc/Hz
1 MHz
−138 dBc/Hz
10 MHz −154 dBc/Hz
• Operating Supply Voltage Range 3.3 V ±5%
• Computing and Peripherals
• Industrial Temperature Range −40°C to +85°C
• Industrial Equipment
• Functionally Compatible with IDT557−05,
• PCIe Clock Generation Gen 1, Gen 2 and Gen 3
IDT5V41066, IDT5V41236 with enhanced performance
End Products
• These are Pb−Free Devices
• Switch and Router
Applications
• Set Top Box, LCD TV
• Networking
• Servers, Desktop Computers
• Consumer
• Automated Test Equipment
VDD
S0
S1
S2
PD
Spread Spectrum
Circuit
X1/CLK
25 MHz Clock
or Crystal
Clock Buffer
Crystal Oscillator
Charge
Pump
Phase
Detector
VCO
X2
BN
VDD = VDDODA = VDDXD
GND = GNDODA = GNDXD GND
Figure 1. NB3N51034 Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 2
1
OE
HCSL
Output
CLK0
CLK0
HCSL
Output
CLK1
CLK1
HCSL
Output
CLK2
CLK2
HCSL
Output
CLK3
CLK3
IREF
Publication Order Number:
NB3N51034/D
NB3N51034
VDDXD
1
20
CLK0
S0
2
19
CLK0
S1
3
18
CLK1
S2
4
17
CLK1
X1/CLK
5
16
GNDODA
X2
6
15
VDDODA
PD
7
14
CLK2
OE
8
13
CLK2
GNDXD
9
12
CLK3
10
11
CLK3
IREF
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Symbol
I/O
Description
1
VDDXD
Power
2
S0
Input
LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDDXD. See output select
table 2 for details.
3
S1
Input
LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDDXD. See output select
Table 2 for details.
4
S2
Input
LVTTL/LVCMOS frequency select input 2. Internal pullup resistor to VDDXD. See output select
Table 2 for details.
5
X1/CLK
Input
Crystal interface or single−ended reference clock input.
6
X2
Output
7
PD
Input
LVTTL/LVCMOS power down input. Assert this pin LOW to enter power down mode. Internal
pull−up resistor to VDDXD.
8
OE
Input
Output enable. Tri−state output (High=enable outputs, Low=disable outputs). Internal pull−up
resistor.
Connect to a +3.3 V source.
Crystal interface. Float this pin for reference clock input CLK.
9
GNDXD
Power
Connect to digital circuit ground.
10
IREF
Output
Precision resistor attached to this pin is connected to the internal current reference.
11
CLK3
HCSL or
LVDS Output
Inverted clock output. (For LVDS levels see Figure 8)
12
CLK3
HCSL or
LVDS Output
Noninverted clock output. (For LVDS levels see Figure 8)
13
CLK2
HCSL or
LVDS Output
Inverted clock output. (For LVDS levels see Figure 8)
14
CLK2
HCSL or
LVDS Output
Noninverted clock output. (For LVDS levels see Figure 8)
15
VDDODA
Power
Connect to a +3.3 V analog source.
16
GNDODA
Power
Output and analog circuit ground.
17
CLK1
HCSL or
LVDS Output
Inverted clock output. (For LVDS levels see Figure 8)
18
CLK1
HCSL or
LVDS Output
Noninverted clock output. (For LVDS levels see Figure 8)
19
CLK0
HCSL or
LVDS Output
Inverted clock output. (For LVDS levels see Figure 8)
20
CLK0
HCSL or
LVDS Output
Noninverted clock output. (For LVDS levels see Figure 8)
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NB3N51034
Recommended Crystal Parameters
Table 2. OUTPUT FREQUENCY AND SPREAD
SPECTRUM SELECT TABLE
S2*
S1*
S0*
Spread%
Spread
Type
Output
Frequency
0
0
0
−0.5
Down
100
0
0
1
−1.0
Down
100
0
1
0
−1.5
Down
100
0
1
1
No Spread
N/A
100
1
0
0
−0.5
Down
200
1
0
1
−1.0
Down
200
1
1
0
−1.5
Down
200
1
1
1
No Spread
N/A
200
Crystal
Frequency
Load Capacitance
Shunt Capacitance, C0
Equivalent Series Resistance
Initial Accuracy at 25 °C
Temperature Stability
Aging
Fundamental AT−Cut
25 MHz
16−20 pF
7 pF Max
50 W Max
±20 ppm
±30 ppm
±20 ppm
*Pins S2, S1 and S0 default high when left open.
Table 3. ATTRIBUTES
Characteristic
Value
Internal Input Default State Resistor (OE, Sx, PD)
ESD Protection
Human Body Model
Moisture Sensitivity, Indefinite Time Out of Dray Pack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
110 kW
2 kV
Level 1
UL 94 V−0 @ 0.125 in
132,000
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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NB3N51034
Table 4. MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Rating
Units
VDD
Positive Power Supply with respect to GND (VDDXD and VDDODA)
4.6
V
VI
Input Voltage with respect to GND (VIN)
−0.5 V to VDD+0.5 V
V
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient) (Note 3)
70
61
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
50
°C/W
Tsol
Wave Solder
265
°C
0 lfpm
500 lfpm
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 5. DC CHARACTERISTICS (VDD = 3.3 V ±5%, GND = 0 V, TA = −40°C to +85°C, Note 4)
Symbol
Characteristic
Min
Typ
Max
Unit
3.135
3.3
3.465
V
VDD
Power Supply Voltage (VDDXD and VDDODA)
GND
Power Supply Ground (GNDXD and GNDODA)
IDD
Power Supply Current, 200 MHz output, −1.5% spread
IDDOE
IDDPD
VIH
Input HIGH Voltage (X1/CLK, S0, S1, S2 and OE)
2000
VDD + 300
mV
VIL
Input LOW Voltage (X1/CLK, S0, S1, S2 and OE)
GND − 300
800
mV
Vmax
Absolute Maximum Output Voltage (Notes 5, 6)
1150
mV
Vmin
Absolute Minimum Output Voltage (Notes 5, 7)
−300
Vrb
Ringback Voltage (Notes 8, 9)
−100
100
mV
VOH
Output High Voltage (Note 5)
660
850
mV
VOL
Output Low Voltage (Note 5)
−150
27
mV
VCROSS
Absolute Crossing Voltage (Notes 5, 9, 10)
250
550
mV
DVCROSS
Total Variation of VCROSS (Notes 5, 9, 11)
140
mV
0
V
135
mA
Power Supply Current when OE is Set Low
60
mA
Power Supply Current (PD = Low, no load)
1.5
mA
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. VDDXD and VDDODA power pins must be shorted to power supply voltage VDD and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken with outputs terminated with RS = 33.2 W, RL = 50 W, with test load capacitance of 2 pF
and current biasing resistor set at 475 W. See Figure 7. Guaranteed by characterization.
5. Measurement taken from single-ended waveform
6. Defined as the maximum instantaneous voltage value including positive overshoot
7. Defined as the maximum instantaneous voltage value including negative overshoot
8. Measurement taken from differential waveform
9. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx-.
10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
11. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx-. This is maximum allowed variance in the VCROSS for
any particular system.
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NB3N51034
Table 6. AC CHARACTERISTICS (VDD = 3.3 V ±5%, GND = 0 V, TA = −40°C to +85°C; Note 12)
Characteristic
Symbol
Min
fCLKIN
Clock/Crystal Input Frequency
fCLKOUT
Output Clock Frequency
fNOISE
Phase−Noise Performance SS OFF
tJIT(F)
Phase RMS Jitter, Integration Range 12 kHz to 20 MHz
fMOD
Spread Spectrum Modulation Frequency
fCLKOUT = 100 MHz
@ 100 Hz offset from carrier
@ 1 kHz offset from carrier
@ 10 kHz offset from carrier
@ 100 kHz offset from carrier
@ 1 MHz offset from carrier
@ 10 MHz offset from carrier
Typ
Max
25
MHz
100/200
MHz
dBc/Hz
−110
−123
−134
−137
−138
−154
0.4
30
3rd
Unit
Harmonic
31.5
ps
33.33
−10
kHz
SSCRED
Spectral Reduction, fCLKOUT of 100 MHz with −0.5% spread,
(Note 13)
dB
tSKEW
Within Device Output to Output Skew
Eppm
Frequency Synthesis Error, All Outputs
tSPREAD
Spread Spectruction Transition Time
(Stablization Time After Spread Spectrum Changes)
tOE
Output Enable/Disable Time (All outputs) (Note 14)
tDUTY_CYCLE
Output Clock Duty Cycle (Measured at cross point)
45
50
55
%
tR
Output Risetime (Measured from 175 mV to 525 mV, Figure 9)
175
340
700
ps
tF
Output Falltime (Measured from 525 mV to 175 mV, Figure 9)
175
400
700
ps
DtR
Output Risetime Variation (Single−Ended)
125
ps
DtF
Output Falltime Variation (Single−Ended)
125
ps
Stabilization
Time
Stabilization Time From Powerup VDD = 3.3 V
40
0
7
3.0
ps
ppm
30
ms
10
ms
ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12. VDDXD and VDDODA power pins must be shorted to power supply voltage VDD and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 50
W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 7. Guaranteed by characterization.
13. Spread spectrum clocking enabled.
14. Output pins are tri−stated when OE is asserted LOW. Output pins are driven differentially when OE is HIGH unless device is in power down
mode, PD = Low.
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NB3N51034
Table 7. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS,
VDD = 3.3 V ± 5%, TA = −40°C to 85°C
Symbol
tj (PCIe Gen 1)
Parameter
Max
SSOFF
10
20
86
ps
SSON
(−0.5%)
19
28
SSOFF
1.0
1.8
3.1
ps
SSON
(−0.5%)
1.1
1.9
SSOFF
0.1
0.15
3.0
ps
SSON
(−0.5%)
0.8
1.1
SSOFF
0.35
0.7
1.0
ps
SSON
(−0.5%)
0.55
0.8
Test Conditions
Phase Jitter
Peak−to−Peak
(Notes 16
and 19)
f = 100 MHz, 25 MHz Crystal
Input Evaluation Band:
0 Hz − Nyquist (clock
frequency/2)
Phase Jitter
RMS (Notes 17
and 19)
f = 100 MHz, 25 MHz Crystal
Input High Band:
1.5 MHz − Nyquist (clock
frequency/2)
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS (Notes 17
and 19)
f = 100 MHz, 25 MHz Crystal
Input Low Band:
10 kHz − 1.5 MHz
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS (Notes 18
and 19)
f = 100 MHz, 25 MHz Crystal
Input Evaluation Band: 0 Hz −
Nyquist (clock frequency/2)
tREFCLK_HF_RMS
(PCIe Gen 2)
Typ
PCIe
Industry
Spec
Min
Unit
15. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
16. Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps
peak−to−peak for a sample size of 106 clock periods.
17. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the
worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band)
and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
18. RMS jitter after applying system transfer function for the common clock architecture.
19. VDDXD and VDDODA power pins must be shorted to power supply voltage VDD and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 50
W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 7. This parameter is guaranteed by
characterization. Not tested in production.
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NB3N51034
NOISE POWEER (dBc/Hz)
PHASE NOISE
OFFSET FREQUENCY (Hz)
NOISE POWEER (dBc/Hz)
Figure 3. Typical Phase Noise Plot at 100 MHz; (fCLKIN = 25 MHz Crystal , fCLKOUT = 100 MHz SS OFF,
RMS Phase Jitter for Integration Range 12 kHz to 20 MHz = 414 fs, Output Termination = HCSL type)
OFFSET FREQUENCY (Hz)
Figure 4. Typical Phase Noise Plot at 200 MHz; (fCLKIN = 25 MHz Crystal , fCLKOUT = 200 MHz SS OFF,
RMS Phase Jitter for Integration Range 12 kHz to 20 MHz = 406 fs, Output Termination = HCSL type)
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NB3N51034
APPLICATION INFORMATION
Crystal Input Interface
as nominal values, assuming approximately 2 pF of stray
capacitance per trace and approximately 8 pF of internal
capacitance.
CL = (C1 + Cstray + Cin) / 2; C1 = C2
The frequency accuracy and duty cycle skew can be
fine-tuned by adjusting the C1 and C2 values. For example,
increasing the C1 and C2 values will reduce the operational
frequency.
Figure 5 shows the NB3N51034 device crystal oscillator
interface using a typical parallel resonant crystal. The device
crystal connections should include pads for small capacitors
from X1 to ground and from X2 to ground. These capacitors,
C1 and C2, need to consider the stray capacitances of the
board and are used to match the nominally required crystal
load capacitance CL. A parallel crystal with loading
capacitance CL = 18 pF would use C1 = 26 pF and C2 = 26 pF
C1 = 26 pF
X1
Fundamental Mode
Parallel Resonant Crystal
18 pF Load
X2
C2 = 26 pF
Figure 5. Crystal Interface Loading
Power Supply Filter
and 6). It is recommended to place decoupling capacitors as
close as possible to the device to minimize lead inductance.
In order to isolate the NB3N51034 from system power
supply, noise decoupling is required. The 10 mF and a 0.1 mF
cap from supply pins to GND decoupling capacitor has to be
connected between VDD (pins 1 and 15) and GND (pins 9
Termination
The output buffer structure is shown in the Figure 6.
2.6 mA
14 mA
IREF
RREF
CLKx
CLKx
HCSL / LVDS
termination
475 W
Figure 6. Simplified Output Structure
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NB3N51034
require the 100 W near the LVDS receiver if the receiver has
internal 100 W termination. An optional series resistor RL
may be connected to reduce the overshoots in case of
impedance mismatch.
The outputs can be terminated to drive HCSL receiver
(see Figure 7) or LVDS receiver (see Figure 8). HCSL output
interface requires 49.9 W termination resistors to GND for
generating the output levels. LVDS output interface may not
HCSL INTERFACE
CLK0
RL* = 33.2 W
Zo = 50 W
RL* = 33.2 W
Zo = 50 W
CLK0
RL = 50 W
RL = 50 W
NB3N51034
Receiver
CLK3
RL* = 33.2 W
Zo = 50 W
RL* = 33.2 W
Zo = 50 W
CLK3
IREF
RL = 50 W
*Optional
RL = 50 W
RREF = 475 W
Figure 7. Typical Termination for HCSL Output Driver and Device Evaluation
LVDS COMPATIBLE INTERFACE
CLK0
RL* = 33.2 W
Zo = 50 W
100 W
RL* = 33.2 W
100 W**
Zo = 50 W
CLK0
RL = 150 W
RL = 150 W
NB3N51034
Receiver
CLK3
RL* = 33.2 W
Zo = 50 W
100 W
RL* = 33.2 W
CLK3
IREF
RREF = 475 W
100 W**
Zo = 50 W
RL = 150 W
*Optional
**Not required if LVDS receiver
has 100 Ohm internal termination
RL = 150 W
LVDS Device Load
Figure 8. Typical Termination for LVDS Device Load
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9
NB3N51034
700 mV
525 mV
525 mV
175 mV
175 mV
0 mV
tR
tF
Figure 9. HCSL Output Parameter Characteristics
ORDERING INFORMATION
Package
Shipping†
NB3N51034DTG
TSSOP−20
(Pb−Free)
75 Units / Rail
NB3N51034DTR2G
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3N51034
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
L
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K
K1
10
M
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
−W−
C
G
D
H
0.100 (0.004)
−T− SEATING
DETAIL E
SOLDERING FOOTPRINT
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
7.06
1
0.65
PITCH
16X
0.36
16X
DIMENSIONS: MILLIMETERS
1.26
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