CS5124 D

CS5124
High Performance,
Integrated Current Mode
PWM Controllers
The CS5124 is a fixed frequency current mode controller designed
specifically for DC−DC converters found in the telecommunications
industry. The CS5124 integrates many commonly required current
mode power supply features and allows the power supply designer to
realize substantial cost and board space savings.
The CS5124 integrates the following features: Internal Oscillator,
Slope Compensation, Sleep On/Off, Undervoltage Lock Out, Thermal
Shutdown, Soft−Start Timer, Low Voltage Current Sense for Resistive
Sensing, Second Current Threshold for Pulse−by−Pulse overcurrent
Protection, a Direct Optocoupler Interface and Leading Edge Current
Blanking.
The CS5124 has supply range of 7.7 V to 20 V and is available in 8
pin SOIC narrow package.
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8
1
PIN CONNECTIONS AND
MARKING DIAGRAM
BIAS
UVLO
1
8
CS512
ALYW4
G
VCC
SS
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
SOIC−8
D SUFFIX
CASE 751
400 kHz Oscillating Frequency
Line UVLO Monitoring
Low Current Sense Voltage for Resistive Current Sensing
Bias for Startup Circuitry
Thermal Shutdown
Sleep On/Off Pin
Soft−Start Timer
Leading Edge Blanking
Direct Optocoupler Interface
90 ns Propagation Delay
35 ns Driver Rise and Fall Times
Sleep Mode
Pb−Free Packages are Available
A
L
Y
W
G
GND
GATE
ISENSE
VFB
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
CS5124XD8
SOIC−8
95 Units/Rail
CS5124XD8G
SOIC−8
(Pb−Free)
95 Units/Rail
CS5124XDR8
SOIC−8
2500 Tape & Reel
SOIC−8
(Pb−Free)
2500 Tape & Reel
CS5124XDR8G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
July, 2009 − Rev. 7
1
Publication Order Number:
CS5124/D
CS5124
36−75VIN
CTX15−14514
T1
L1
10 mH
R2
200 k
C1
0.1 mF
100 V
R1
510 k
R4
10 W
R3
47 W
BAS16LT1
R5
17.4 k
Q2
IRFR220
C4
0.47 mF
25 V
VCC
GND
BIAS
GATE
C3
0.022 mF
R7
30.1 k
R6
1.0 k
R8
0.39 W
C5
47 mF
10 V
C6
U2
IS
UVLO
ENABLE
5VOUT
MBRD360CT
Q1
ZVN3310A D4
C2
1.5 mF
100 V
D1
0.01 mF
CS5124
C9
1000 pF
VFB
SS
C7
0.1 mF
C8
1000 pF
TPS5908
R9
10 k
48VRTN
ISOLATED
RTN
Figure 1. Application Diagram
MAXIMUM RATINGS
Rating
Value
Unit
Operating Junction Temperature, TJ
−40 to 135
°C
Storage Temperature Range, TS
−40 to 150
°C
2.0
kV
230 peak
°C
ESD Susceptibility (Human Body Model)
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
VCC Power Input
VCC
20 V
−0.3 V
1.0 mA
1.5 A Peak
200 mA DC
VCC Clamp Output
VBIAS
20 V
−0.3 V
1.0 mA
1.0 mA
UVLO Shutdown Input
UVLO
6.0 V
−0.3 V
1.0 mA
1.0 mA
Soft−Start Capacitor Input
SS
6.0 V
−0.3 V
1.0 mA
2.0 mA
Voltage Feedback Input
VFB
6.0 V
−0.3 V
3.0 mA
20 mA
Current Sense Input
ISENSE
6.0 V
−0.3 V
1.0 mA
1.0 mA
Ground
GROUND
0V
0V
1.5 A peak
200 mA DC
1.0 mA
Gate Drive Output
GATE
20 V
−0.3 V
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
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CS5124
ELECTRICAL CHARACTERISTICS (−40°C ≤ TJ ≤ 125°C; −40°C ≤ TA ≤ 105°C, 7.60 V ≤ VCC ≤ 20 V, UVLO = 3.0 V,
ISENSE = 0 V, CV(CC) = 0.33 mF, CGATE = 1.0 nF (ESR = 10 W); CSS = 470 pF; CV(FB) = 100 pF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
ICC Operating − VGATE not switching
−
−
10
13
mA
General
ICC at VCC Low
VCC = 6.0 V
−
500
750
mA
ICC Sleep
VUVL = 1.0 V
−
210
275
mA
Low VCC Lockout
VCC Turn−on Threshold Voltage
−
7.2
7.7
8.3
V
VCC Turn−off Threshold Voltage
−
6.8
7.3
7.8
V
VCC Hysteresis
−
350
425
500
mV
UVLO
Sleep Threshold Voltage
UVLO decreasing
1.5
1.8
2.3
V
Sleep Threshold Voltage
UVLO increasing
−
1.88
2.45
V
35
85
150
mV
Sleep Hysteresis
−
UVLO Turn−off Threshold Voltage
(Note 2)
2.3
2.45
2.6
V
UVLO Turn−on Threshold Voltage
(Note 2)
2.50
2.63
2.76
V
UVLO Hysteresis
Turn−on − Turn−off (−40°C ≤ TJ ≤ 100°C) (Note 2)
170
185
200
mV
UVLO Hysteresis
Turn−on − Turn−off (100°C ≤ TJ ≤ 125°C) (Note 2)
50
185
400
mV
−1.0
−
1.0
mA
5.0
7.5
12
V
7.275
7.9
8.625
V
UVLO Input Bias Current
UVLO Clamp
VCC Clamp and BIAS Pin
−
With UVLO sinking 1.0 mA
Connect an NFET as follows: BIAS = G, VCC = S, VIN = D.
VCC Clamp Voltage
36 V ≤ VIN ≤ 60 V, 200 nF ≤ CSS ≤ 500 nF,
R = 500 k
BIAS Minimum Voltage
Measure Voltage on BIAS with:
10 V ≤ VCC ≤ 20 V & 50 mA ≤ IBIAS ≤ 1.0 mA
1.6
2.8
4.0
V
BIAS Clamp
With BIAS pin sinking 1.0 mA
12
15
20
V
Difference between Regulated VCC
& VCC Turn−on Threshold Voltage
(VCC Clamp Voltage) − (VCC Turn−on Threshold)
100
−
−
mV
Operating Frequency
−
360
400
440
kHz
Max Duty Cycle Clamp
−
80.0
82.5
85.0
%
Slope Compensation
−
15
21
26
mV/m
σ
400 kHz Oscillator
2. Not tested in production. Specification is guaranteed by design.
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3
CS5124
ELECTRICAL CHARACTERISTICS (continued) (−40°C ≤ TJ ≤ 125°C; −40°C ≤ TA ≤ 105°C, 7.60 V ≤ VCC ≤ 20 V, UVLO = 3.0 V,
ISENSE = 0 V, CV(CC) = 0.33 mF, CGATE = 1.0 nF (ESR = 10 W); CSS = 470 pF; CV(FB) = 100 pF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
−
7.0
10
13
mA
0.5
10.0
−
mA
1.40
1.62
1.80
V
Soft−Start
Soft−Start Charge Current
Soft−Start Discharge Current
VSS Voltage when VFB Begins to
Rise
−
VFB = 300 mV
Peak Soft−Start Charge Voltage
−
4.7
4.9
−
V
Valley Soft−Start Discharge Voltage
−
200
275
400
mV
170
195
215
mV
−
250
275
315
mV
ISENSE to GATE Prop. Delay
0 to 700 mV pulse into ISENSE (after blanking time)
60
90
130
ns
Leading Edge Blanking Time
0 to 400 mV pulse into ISENSE
90
130
180
ns
Internal Offset
Note 3
−
60
−
mV
2.9
4.3
8.1
kW
2.63
2.90
3.15
V
460
490
520
mV
−
1.2
2.0
V
Current Sense
First Current Sense Threshold
At max duty cycle
Second Current Sense Threshold
Voltage Feedback
VFB Pull−up Res.
−
VFB Clamp Voltage
VFB Fault Voltage Threshold
−
Output Gate Drive
Maximum Sleep Pull−down Voltage
VCC = 6.0 V, IOUT = 1.0 mA
GATE High (AC)
Series resistance < 1.0 W, (Note 3)
VCC − 1.0
VCC − 0.5
−
V
GATE Low (AC)
Series resistance < 1.0 W, (Note 3)
−
0.0
0.5
V
GATE High Clamp Voltage
VCC = 20 V
11.0
13.5
16.0
V
Rise Time
Measure GATE rise time,
1.0 V < GATE < 9.0 V VCC = 12 V
−
45
65
ns
Fall TIme
Measure GATE fall time,
9.0 V > GATE > 1.0 V VCC = 12 V
−
25
55
ns
Thermal Shutdown
Thermal Shutdown Temperature
(Note 3) GATE low
135
150
165
°C
Thermal Enable Temperature
(Note 3) GATE switching
100
125
150
°C
Thermal Hysteresis
(Note 3)
15
25
35
°C
3. Not tested in production. Specification is guaranteed by design.
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CS5124
PACKAGE PIN DESCRIPTION
PIN #
Pin
Description
1
VCC
VCC Power Input Pin.
2
BIAS
VCC Clamp Output Pin. This pin will control the gate of an N−channel MOSFET that in turn regulates Vcc. This pin is
internally clamped at 15 V when the IC is in sleep mode.
3
UVLO
Sleep and under voltage lockout pin. A voltage greater than 1.8 V causes the chip to “wake up” however the GATE
remains low. A voltage greater than 2.6 V on this pin allows the output to switch.
4
SS
Soft−Start Capacitor Pin. A capacitor placed between SS and GROUND is charged with 10 mA and discharged with
10 mA. The Soft−Start capacitor controls both Soft−Start time and hiccup mode frequency.
5
VFB
Voltage Feedback Pin. The collector of an optocoupler is typically tied to this pin. This pin is pulled up internally by a
4.3 kW resistor to 5.0 V and is clamped internally at 2.9 V (2.65 V). If VFB is pulled > 4.0 V, the oscillator is disabled
and GATE will stay high. If the VFB pin is pulled < 0.49 V, GATE will stay low.
6
ISENSE
Current Sense Pin. This pin is connected to the current sense resistor on the primary side. If VFB is floating, the
GATE will go low if ISENSE = 195 mV (335 mV). If ISENSE > 275 mV (525 mV), Soft−Start will be initiated.
7
GATE
Gate Drive Output Pin. Capable of driving a 3.0 nF load. GATE is nominally clamped to 13.5 V.
8
GND
Ground Pin.
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5
CS5124
VCC UVLO COMP
VCC
VCC
+
G2
−
+
LINE UVLO COMP
+
G7
G3
V5REF
2.62 V/2.45 V
4500 W
−
+
10 mA
VFB COMP
PWM COMP
+
V 490 mV 1/10
÷
−
+
+
−
60 mV
2ND
ICOMP
Soft−Start LATCH
VFB
V
+
+
V 1.91 V/1.83 V
V5REF
170 mV/ms
REMOTE
(SLEEP) COMP
BIAS
GATE
Q
RESET DOMAIN
+
UVLO
S
R
S
−
VREFOK
+
+
150°C/125°C
+
V
G1
Q
F1
V5REF
V
−
DRIVER
F3
R
RAMP
VREF = 5.0 V
ENABLE
V 7.7 V/7.275 V
TSHUT
OSC
DIS
1000 W
ISENSE
275 mV
−
+
V
F2
G5
VCC
BLANK
SET DOMAIN
−
2.90 V
V5REF
−
+
R
SS COMP
+
2.0 V
BLANKING
Q
R
2.9 R
LINE AMP
S
V
+
+
V
+
G6
SS AMP
GND
+
275 mV V
−
1.32 V
+
SS
V
Figure 2. Block Diagram
THEORY OF OPERATION
Powering the IC
regulated to 8.0 V by the BIAS pin, but the IC remains in a
UVLO state and the output driver does not switch. When the
UVLO pin exceeds 2.6 V and the VCC pin exceeds 7.7 V, the
GATE pin is released from a low state and can begin
switching based on the comparison of the ISENSE and VFB
pins. The Soft−Start capacitor begins charging from 0 V at
10 mA. As the capacitor charges, a buffered version of the
capacitor voltage appears on the VFB pin and the VFB
voltage begins to rise. As VFB rises the duty cycle increases
until the supply comes into regulation.
VCC can be powered directly from a regulated supply and
requires 500 mA of startup current. The CS5124 includes a
line bias pin (BIAS) that can be used to control a series pass
transistor for operation over a wide input voltage. The BIAS
pin will control the gate voltage of an N−channel MOSFET
placed between VIN and VCC to regulate VCC at 8.0 V.
VCC and UVLO Pins
The UVLO pin has three different modes; low power
shutdown, Line UVLO, and normal operation. To illustrate
how the UVLO pin works; assume that VIN, as shown in the
application schematic, is ramped up starting at 0 V with the
UVLO pin open. The SS and ISENSE pins also start at 0 V.
While the UVLO is below 1.8 V, the IC will remain in a low
current sleep mode and the BIAS pin of the CS5124 is
internally clamped to a maximum of 15 V. When the voltage
on the UVLO pin rises to between 1.8 V and 2.6 V the
reference for the VCC UVLO is enabled and VCC is
Soft−Start
Soft−Start is accomplished by clamping the VFB pin 1.32 V
below the SS pin during normal start up and during restart
after a fault condition. When the CS5124 starts, the
Soft−Start capacitor is charged from a 10 mA source from 0
V to 4.9 V. The VFB pin follows the Soft−Start pin offset
by −1.32 V until the supply comes into regulation or until
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6
CS5124
Second Threshold Comparator
the Soft−Start error amp is clamped at 2.9 V. During fault
conditions the Soft−Start capacitor is discharged at 10 mA.
Since the maximum dynamic range of the ISENSE signal
in normal operation is 195 mV, any voltage exceeding this
threshold on the ISENSE pin is considered a fault and the
PWM cycle is terminated. The 2nd ICOMP compares the
ISENSE signal with a 275 mV threshold. If the ISENSE
voltage exceeds the second threshold, F2 is set, the driver
turns off, and the Soft−Start capacitor discharges. After the
Soft−Start capacitor has discharged to less than 0.275 V
Soft−Start will begin. If the fault condition has been
removed the supply will operate normally. If the fault
remains the supply will operate in hiccup mode until the
fault condition is removed.
Fault Conditions
The CS5124 recognizes the following faults: UVLO off,
Thermal Shutdown, VREF(OK), and Second Current
Threshold. Once a fault is recognized, fault latch F2 is set
and the IC immediately shuts down the output driver and
discharges the Soft−Start capacitor. Soft−Start will begin
only after all faults have been removed and the Soft−Start
capacitor has been discharged to less than 0.275 V. Each
fault will be explained in the following sections.
Under Voltage Lockout (UVLO)
The UVLO pin is tied to typically the midpoint of a
resistive divider between VIN and GROUND. During a start
up sequence, this pin must be above 2.6 V in order for the IC
to begin normal operation. If the IC is running and this pin
is pulled below 1.8 V, F2 shuts down the output driver and
discharges the Soft−Start capacitor in order to insure proper
startup. If the UVLO pin is pulled high again before the
Soft−Start capacitor discharges, the IC will complete the
Soft−Start discharge and, if no other faults are present, will
immediately restart the power supply. If the UVLO pin stays
low, then it will enter either the low current sleep mode or the
UVLO state depending on the level of the UVLO pin.
VFB Comparator
The VFB comparator detects when the output voltage is
too high. When the regulated output voltage is too high, the
feedback loop will drive VFB low. If VFB is less than 0.49 V
the output of the VFB comparator will go high and shut the
output driver off.
Oscillator
The internally trimmed, 400 kHz provides the slope
compensation ramp as well as the pulse for enabling the
output driver.
PWM Comparator and Slope Compensation
The CS5124 provides a fixed internal slope compensation
ramp that is subtracted from the feedback signal. The PWM
comparator compares peak primary current to a portion of
the difference of the feedback voltage and slope
compensation ramp. The 170 mV/ms slope compensation
ramp is subtracted from the voltage feedback signal
internally. The difference signal is then divided by ten before
the PWM comparator to provide high noise rejection with a
low voltage across the current sense network. The effective
ramp is 21 mV/ms. A 60 mV nominal offset on the positive
input to the PWM comparator allows for operation with the
ISENSE pin at, or even slightly below GND.
A 4.3 kW pull−up resistor internally connected to a 5.0 V
nominal reference provides the bias current to for an
optocoupler connection to the VFB pin.
Thermal Shutdown
If the IC junction temperature exceeds approximately
150°C the thermal shutdown circuit sets F2, which shuts
down the output driver and discharges the Soft−Start
capacitor. If no other faults are present the IC will initiate
Soft−Start when the IC junction temperature has been
reduced by 25°C.
VREF(OK)
VREF(OK) is an internal monitor that insures the internal
regulator is running before any switching occurs. This
function does not trip the fault comparator like the other fault
functions. To insure that Soft−Start will occur at low line
conditions the UVLO divider should be set up so that the
VCC UVLO comparator turns on before the LINE UVLO
comparator.
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CS5124
APPLICATION INFORMATION
UVLO and Thermal Shutdown Interaction
8.5
The UVLO pin and thermal shutdown circuit share the
same internal comparator. During high temperature
operation (TJ > 100°C) the UVLO pin will interact with the
thermal shutdown circuit. This interaction increases the
turn−on threshold (and hysteresis) of the UVLO circuit. If
the UVLO pin shuts down the IC during high temperature
operation, higher hysteresis (see hysteresis specification)
might be required to enable the IC.
Peak Voltage
8.0
7.5
7.0
6.5
BIAS Pin
The bias pin can be used to control VCC as shown in the
main application diagram in Figure 1. In order to provide
adequate phase margin for the bias control loop, the pole
created by the series pass transistor and the VCC bypass
capacitor should be kept above 10 kHz. The frequency of
this pole can be calculated by Formula (1).
Pole Frequency +
Transconductance of pass Transistor
2 p CV(CC)
6.0
0
0.3
0.5
2.5
Gate Resistor Value
5.0
11
Figure 4. Gate Drive vs. Gate Resistor Driving an
IRF220 (VCC = 8.0 V)
A large negative dv/dt on the power MOSFET drain will
couple current into the gate driver through the gate to drain
capacitance. If this current is kept within absolute maximum
ratings for the GATE pin it will not damage the IC. However
if a high negative dv/dt coincides with the start of a PWM
duty cycle, there will be small variations in oscillator
frequency due to current in the controller substrate. If
required, this can be avoided by choosing the transformer
ratio and reset circuit so that a high dv/dt does not coincide
with the start of a PWM cycle, or by clamping the negative
voltage on the GATE pin with a Schottky diode
(1)
The Line BIAS pin shows a significant change in the
regulated VCC voltage when sinking large currents. This will
show up as poor line regulation with a low value pull−up
resistor. Typical regulated VCC vs BIAS pin sink current is
shown in Figure 3.
8.3
First Current Sense Threshold
8.2
VCC
During normal operation the peak primary current is
controlled by the level of the VFB pin (as determined by the
control loop) and the current sense network. Once the signal
on the ISENSE pin exceeds the level determined by VFB pin
the PWM cycle terminates. During high output currents the
VFB pin will rise until it reaches the VFB clamp. The first
current sense threshold determines the maximum signal
allowed on the ISENSE pin before the PWM cycle is
terminated. Under this condition the maximum peak current
is determined by the VFB Clamp, the slope compensation
ramp, the PWM comparator offset voltage and the PWM on
time. The nominal first current threshold varies with on time
and can be calculated from Formulas (2) and (3) below.
8.1
8.0
7.9
5.0 mΑ
10 mΑ
20 mΑ
50 mΑ
Bias Current (IBIAS)
100 mΑ
200 mΑ
Figure 3. Regulated VCC vs. BIAS Sink Current
The BIAS pin and associated components form a high
impedance node. Care should be taken during PCB layout to
avoid connections that could couple noise into this node. To
ensure adequate design margin between the regulated VCC
and the Low VCC Lockout voltage, a guaranteed minimum
differential between the two values is specified (see
electrical characteristcs).
1st Threshold +
2.9 V * 170 mVńms
10
TON
* 60 mV
(2)
When the output current is high enough for the ISENSE pin
to exceed the first threshold, the PWM cycle terminates
early and the converter begins to function more like a current
source. The current sense network must be chosen so that the
peak current during normal operation does not exceed the
first current sense threshold.
Gate Drive
Rail to rail gate driver operation can be obtained (up to
13.5 V) over a range of MOSFET input capacitance if the
gate resistor value is kept low. Figure 5 shows the high gate
drive level vs. the series gate resistance with VCC = 8.0 V
driving an IRF220.
Second Current Sense Threshold
The second threshold is intended to protect the converter
from overheating by switching to a low duty cycle mode
when there are abnormally high fast rise currents in the
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CS5124
converter. If the second current sense threshold is tripped,
the converter will shut off and restart in Soft−Start mode
until the high current condition is removed. The dead time
after a second threshold overcurrent condition will primarily
be determined by the time required to charge the Soft−Start
cap from 0.275 V nominal to 1.32 V.
The second threshold will only be reached when a high
dv/dt is present at the current sense pin. The signal must be
fast enough to reach the second threshold before the first
threshold turns off the driver. This will normally happen if
the forward inductor saturates or when there is a shorted
load.
Excessive filtering of the current sense signal, a low value
current sense resistor, or even an inductor that does not
saturate during heavy output currents can prevent the second
threshold from being reached. In this case the first current
sense threshold will trip during each cycle of high output
current conditions. The first threshold will limit output
current but some components, especially the output rectifier,
can overheat due to higher than normal average output
current.
1
20 mVńms
RSENSE
1.0 + 13.2 mH
(5)
There are numerous ways to power the CS5124 from a
transformer winding to enable the converter to be operated
at high efficiency over a wide input range.
The CS5124 application circuit in Figure 1 is a flyback
converter that uses a second flyback winding to power VCC.
R4 improves VCC regulation with load changes by snubbing
the turn off spike. Once the turn off spike has subsided the
voltage of this winding is voltage proportional to the voltage
on the main flyback winding. This voltage is regulated
because the main winding is clamped by the regulated output
voltage.
A flyback winding from a forward transformer can also be
used to power VCC. Ideally the transformer volt−second
product of a forward converter would be constant over the
range of line voltages and load currents; and the transformer
inductance could be chosen to store the required level of
energy during each cycle to power VCC. Even though the
flyback energy is not directly regulated it would remain
constant. Unfortunately in a real converter there are many
nonideal effects that degrade regulation. Transformer
inductance varies, converter frequency varies, energy stored
in primary leakage inductance varies with output current,
stray transformer capacitances and various parasitics all
effect the level of energy available for VCC. If too little
energy is provided to VCC, the bootstrapping circuit must
provide power and efficiency will be reduced. If too much
energy is provided VCC rises and may damage the controller.
If this approach is taken the circuit must be carefully
designed and component values must be controlled for good
regulation.
NSECONDARY
NPRIMARY
Slope Value Factor + Inductor Value(H)
0.2 W
Powering the CS5124 from a Transformer Winding
Current mode converters operating at duty cycles in
excess of 50% require an artificial ramp to be added to the
current waveform or subtracted from the feedback
waveform. For the current loop to be stable the artificial
ramp must be equivalent to at least 50% of the inductor
current down slope and is typically chosen between 75% to
100% of the inductor down current down slope.
To choose an inductor value such that the internal slope
compensation ramp will be equal to a certain fraction of the
inductor down current slope use the Formula (4).
(VOUT ) VRECTIFIER)
1
4
To check that the slope compensation ramp will be greater
than 50% of the inductor down under all conditions,
substitute the minimum internal slope compensation value
and use 0.5 for the slope compensation value. Then check
that the actual inductor value will always be greater than the
inductor value calculated.
Slope Compensation
1
Internal Ramp
(5.0 V ) 0.3 V)
(4)
Calculating the nominal inductor value for an artificial
ramp equivalent to 100% of the current inductor down slope
at CS5124 nominal conditions, a 5.0 V output, a 200 mW
current sense resistor and a 4:1 transformer ratio yields
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9
CS5124
PACKAGE DIMENSIONS
−X−
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm Ǔ
ǒinches
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
PACKAGE THERMAL DATA
SOIC−8
Unit
RqJC
Typical
45
°C/W
RqJA
Typical
165
°C/W
Parameter
http://onsemi.com
10
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
CS5124
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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11
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CS5124/D
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