NCP81246 D

NCP81246
Three-Rail Controller
with Intel Proprietary
Interface for IMVP8 CPU
Applications
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The NCP81246 contains a two-phase, and two single-phase buck
regulators optimized for Intel IMVP8 compatible CPUs.
The two-phase controller combines true differential voltage sensing,
differential inductor DCR current sensing, input voltage feed-forward,
and adaptive voltage positioning to provide accurately regulated
power for IMVP8 Rail2.
The two single-phase controllers can be used for Rail1, Rail3 and
Rail4 rails. Both make use of ON Semiconductor’s patented enhanced
RPM operation. RPM control maximizes transient response while
allowing for smooth transitions between discontinuous frequency
scaling operation and continuous mode full power operation. The
single-phase rails have an ultralow offset current monitor amplifier
with programmable offset compensation for ultra high accuracy
current monitoring.
The NCP81246 offers three internal MOSFET drivers with a single
external PWM signal.
1 52
QFN52
MN SUFFIX
CASE 485BE
MARKING DIAGRAM
NCP81246
FAWLYYWW
G
Two-Phase Rail Features
• Dual Edge Modulation for Fastest Initial Response to Transient
•
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•
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Loading
High Performance Operational Error Amplifier
Digital Soft Start Ramp
Dynamic Reference Injection® (Patent #US7057381)
Accurate Total Summing Current Amplifier(Patent #US6683441)
Dual High Impedance Differential Voltage and Total Current Sense
Amplifiers
Phase-to-Phase Dynamic Current Balancing
True Differential Current Balancing Sense Amplifiers for Each Phase
Adaptive Voltage Positioning (AVP)
Switching Frequency Range of 300 kHz – 750 kHz
Vin range 4.5 V to 25 V
Start-Up into Pre-Charged Loads While Avoiding False OVP
UltraSonic Operation
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Single-Phase Rail Features
•
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Enhanced RPM Control System
Ultra Low Offset IOUT Monitor
Dynamic VID Feed-Forward
Programmable Droop Gain
Zero Droop Capable
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 1
1
NCP81246
F
A
WL
YY
WW
G
= Specific Device Code
= Wafer Fab
= Assembly Site
= Lot ID
= Year
= Work Week
= Pb-Free Package
ORDERING INFORMATION
Device
NCP81246MNTXG
Package
Shipping†
QFN52 5000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Thermal Monitor
UltraSonic Operation
Adjustable Vboot
Digitally Controlled Operating Frequency
Publication Order Number:
NCP81246/D
NCP81246
+5 V
+5 V
VCC
SKT_SNS+
VSP
GND
SKT_SNS−
VSN
PVCC
COMP
VIN
ILIM
IOUT
BST
VCC_Rail1
HG
SW
TSENSE
LG
NTC
NTC
VPU
CSP
CSN
VRHOT
VPU
VPU
SDIO
ALERT
SCLK
PSYS
Batt chrgr
VIN
BST
TSENSE
HG
NTC
NCP81246
VCC_Rail2
SW
LG
IOUT
CSP1
VIN
BST
SKT_SNS+
VSP
SKT_SNS−
VSN
HG
SW
DIFFOUT
LG
FB
CSP2
CSREF
COMP
CSSUM
VIN
EN
VRRDY
ILIM
CSCOMP
NTC
VRMP
VIN
VRDV
SKT_SNS+
VSP
SKT_SNS−
VSN
COMP
BST
PWM HG
SW
EN
PWM
DRON
VCC
IOUT
ILIM
LG
NCP81253
CSP
CSN
Figure 1. Application Schematic
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2
VCC_Rail3
NTC
NCP81246
VSP
VR_HOT#
1.3 V
VSN
Thermal
Monitor
OVP
S
+
DIFF
AMP
DRVON
SCLK
ENABLE
OCP
CSCOMP
VSN_2PH
DIFFOUT_2PH
DAC
Feed-Forward
OVP
PS#
−
ALERT#
VSP_2PH
DAC
DAC
Intel proprietary
interface
Interface
& Logic
VSP
VSN
S
−
ENABLE
SDIO
CSREF
OVP
FB_2PH
+
VR_RDY
Error
AMP 1.3 V
Data
Registers
VR Ready
Logic
COMP_2PH
CSCOMP_2PH
−
ROSC
ICCMAX_1B
ADDR_VBOOT
TSENSE_2PH
(VSP−VSN)
Current
Sense
AMP
OVP MAX
IOUT_2ph
IOUT_1a
IOUT_1b
MUX
ICCMAX_1A
+
ICCMAX_2PH
ADC
CSSUM_2PH
Buffer Over-Current
Programming
CSREF_2PH
ILIM_2PH
Over-Current
Comparators
OVP
ENABLE
TSENSE_1A
OCP
PSYS/TSENSE_1B
PS#
Oscillator
& RAMP
Generators
VRAMP
IOUT_2PH
DRVON
VRMP
COMP
OVP
OCP
ENABLE
DRVON
ADDR_VBOOT
CSP2_2PH
PVCC
PS#
PVCC
Zero Current
Detection
GND
Current
Monitor
Current Balance
Amplifiers
IPH2
IPH1
PWM
Generators
PVM1
EN
UVLO&EN
Comparators
PVM2
VCC
IOUT
Config
PS#
Power
State
Gate
Figure 2. 2-Phase Rail Block Diagram
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3
Gate
Drivers
CSP1_2PH
PWM
HG1
SW1
LG1
HG2
SW2
LG2
NCP81246
DAC Feed-Forward Current
DAC
Feed-Forward
DAC
DAC
+
+
gm
S
VSN
VSN_1x
VSP
VSP_1x
−
COMP_1x
Droop
Current
+
AV = 1
DAC
ILIM_1x
Over-Current
Comparators
OCP OCP REF
RAMP
IOUT
VRMP
FREQ
CURR
OCP
CSN_1x
Offset
Adjust
Over-Current Programming
OVP
PWM
Generator
CSP_1x
Current
Sense AMP
OVP OVP REF
COMP
DRVON
−
From Intel
proprietary
interface
Interface
RAMP
Generator
PWM
PS#
IOUT_1x
Current
Monitor
PVCC
Zero
Current
Detection
Gate
Driver
ADDR_VBOOT
Config
Figure 3. Single-Phase Block Diagram
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4
PVCC
Gate
Driver
HG3
SW3
LG3
1-Phase A
Only
PWM
HG2
SW2
LG2
1-Phase B
Only
EN
PWM/ADDR_VBOOT
52
51
50
49
48
47
46
45
44
43
42
41
40
VSN_2ph
VSP_2ph
PSYS
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
VR_RDY
NCP81246
1
2
3
4
5
6
7
8
9
10
11
39
38
37
36
35
34
33
32
31
30
29
28
27
NCP81246
TAB: GROUND
(Not to Scale)
DRON
SCLK
ALERT#
SDIO
VR_HOT#
IOUT_1a
CSP_1a
CSN_1a
ILIM_1a
COMP_1a
VSN_1a
VSP_1a
TSENSE_1a
BST1
HG1
SW1
LG1/ROSC
PVCC
LG2/ICCMAX_1a
SW2
HG2
BST2
LG3/ICCMAX_1b
SW3
HG3
BST3
25
26
12
13
14
15
16
17
18
19
20
21
22
23
24
IOUT_2ph
DIFFOUT_2ph/ICCMAX_2ph
FB_2ph
COMP_2ph
ILIM_2ph
CSCOMP_2ph
CSSUM_2ph
CSREF_2ph
CSP2_2ph
CSP1_2ph
TSENSE_2ph
VRMP
VCC
Figure 4. Pin Configuration
Table 1. NCP81246 PIN DESCRIPTIONS
Pin No.
Symbol
1
IOUT_2ph
2
DIFFOUT_2ph/
ICCMAX_2ph
Description
A resistor to ground programs IOUT gain for the two-phase regulator.
Output of the two-phase regulator’s differential remote sense amplifier.
During start-up, the two-phase regulator’s ICCMAX is programmed with a pull-down on this pin.
3
FB_2ph
4
COMP_2ph
Error amplifier voltage feedback for two-phase regulator.
Output of the error amplifier and the inverting inputs of the PWM comparators for two-phase
regulator.
5
ILIM_2ph
Over-current threshold setting − programmed with a resistor to CSCOMP_2ph for two-phase
regulator.
6
CSCOMP_2ph
7
CSSUM_2ph
Inverting input of total-current-sense amplifier for two-phase regulator.
8
CSREF_2ph
Total-current-sense amplifier reference voltage input for two-phase regulator.
9
CSP2_2ph
Non-inverting input to current-balance amplifier for Phase 2 of the two-phase regulator.
10
CSP1_2ph
Non-inverting input to current-balance amplifier for Phase 1 of the two-phase regulator.
11
TSENSE_2ph
12
VRMP
Feed-forward input of Vin for the ramp-slope compensation. The current fed into this pin is used to
control the ramp of the PWM slopes.
13
VCC
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.
14
BST1
High-side bootstrap supply for Phase 1 of the two-phase regulator.
15
HG1
High-side FET gate driver output for Phase 1 of the two-phase regulator.
Output of total-current-sense amplifier for two-phase regulator.
Temperature sense input for the two-phase regulator.
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NCP81246
Table 1. NCP81246 PIN DESCRIPTIONS (continued)
Pin No.
Symbol
16
SW1
17
LG1/ROSC
Description
Current return for high-side FET gate driver for Phase 1 of the two-phase regulator.
Low-side FET gate driver output for Phase 1 of the two-phase regulator.
During start-up ROSC is programmed with a pull-down resistor on this line.
18
PVCC
19
LG2/ICCMAX_1a
20
SW2
Current return for high-side FET gate driver for Phase 2 of the two-phase regulator, or for
single-phase regulator 1b.
21
HG2
High-side FET gate driver output for Phase 2 of the two-phase regulator, or for single-phase
regulator 1b.
22
BST2
High-side bootstrap supply for Phase 2 of the two-phase regulator, or for single-phase regulator 1b.
23
LG3/ICCMAX_1b
24
SW3
Current return for high-side FET gate driver for single-phase regulator 1a.
25
HG3
High-side FET gate driver output for single-phase regulator 1a.
26
BST3
High-side bootstrap supply for single-phase regulator 1a.
27
TSENSE_1a
Temperature sense input for the single-phase regulators.
28
VSP_1a
Differential Output Voltage Sense Positive for single-phase regulator 1a.
29
VSN_1a
Differential Output Voltage Sense Negative for single-phase regulator 1a.
30
COMP_1a
31
ILIM_1a
A resistor to ground programs the current-limit for single-phase regulator 1a.
32
CSN_1a
Differential current sense negative for single-phase regulator 1a.
33
CSP_1a
Differential current sense positive for single-phase regulator 1a.
34
IOUT_1a
A resistor to ground programs IOUT gain for single-phase regulator 1a.
35
VR_HOT#
Thermal logic output for over temperature.
36
SDIO
37
ALERT#
Power supply for all three internal FET gate drivers.
Low-side FET gate driver output for Phase 2 of the two-phase regulator, or output of single-phase
regulator 1b.
During start-up, regulator 1a’s ICCMAX is programmed with a pull-down on this pin.
Low-side FET gate driver output for single-phase regulator 1a.
During start-up, regulator 1b s ICCMAX is programmed with a pull-down on this pin.
Compensation for single-phase regulator 1a.
Serial VID data interface
Serial VID ALERT#
38
SCLK
Serial VID clock
39
DRON
Bi-directional FET driver enable
40
PWM/
ADDR_VBOOT
PWM output for phase 2 of the two-phase regulator or single-phase regulator 1b.
During start-up, a resistor to ground programs Intel proprietary interface address and VBOOT
options for all three rails.
41
EN
42
VR_RDY
Enable. High enables all three rails.
VR_RDY indicates all three rails are ready to accept Intel proprietary interface commands.
43
IOUT_1b
A resistor to ground programs IOUT gain for single-phase regulator 1b.
44
CSP_1b
Differential current sense positive for single-phase regulator 1b.
45
CSN_1b
Differential current sense negative for single-phase regulator 1b.
46
ILIM_1b
A resistor to ground programs the current-limit for single-phase regulator 1b.
47
COMP_1b
48
VSN_1b
Differential Output Voltage Sense Negative for single-phase regulator 1b.
49
VSP_1b
Differential Output Voltage Sense Positive for single-phase regulator 1b.
50
PSYS/TSENSE_1b
51
VSP_2ph
Differential Output Voltage Sense Positive for the two-phase regulator.
52
VSN−2ph
Differential Output Voltage Sense Negative for the two-phase regulator.
Compensation for single-phase regulator 1b.
System power signal input. Resistor to ground for scaling /
Temperature sense input for the single-phase regulators.
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NCP81246
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
COMP_2ph
VCC + 0.3 V
−0.3 V
2 mA
2 mA
CSCOMP_2ph
VCC + 0.3 V
−0.3 V
2 mA
2 mA
VSN_2ph
GND + 0.3 V
GND – 0.3 V
1 mA
1 mA
DIFFOUT_2ph /
IccMax_2ph
VCC + 0.3 V
−0.3 V
2 mA
2 mA
VCC
6.5 V
−0.3 V
100 mA
100 mA
PVCC
6.5 V
−0.3 V
100 mA
100 mA
VRMP
25 V
−0.3 V
100 mA
100 mA
SW_x
35 V
40 V ≤ 50 ns
−5 V
100 mA
100 mA
BST_x
35 V wrt / GND
40 V ≤ 50 ns wrt / GND
6.5 V wrt / SW
−0.3 V wrt / SW
100 mA
100 mA
LG_x / ICCMAX_x
VCC + 0.3 V
−0.3 V
−2 V ≤ 200 ns
100 mA
100 mA
HG_x
BST + 0.3 V
−0.3 V wrt / SW
−2 V ≤ 200 ns wrt /SW
100 mA
100 mA
All Other Pins
VCC + 0.3 V
−0.3 V
100 mA
100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to GND unless noted otherwise.
Table 3. THERMAL INFORMATION
Description
Symbol
Value
Unit
RqJA
68
_C/W
TJ
−40 to +125
_C
−40 to +100
_C
Maximum Storage Temperature Range
TSTG
− 40 to +150
_C
Moisture Sensitivity Level QFN Package
MSL
1
Thermal Characteristic QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct-Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct-Attach Method) with 0 LFM
Table 4. ELECTRICAL CHARACTERISTICS − GENERAL
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Test Conditions
Min
Typ
Max
Unit
4.75
−
5.25
V
PS0, PS1, PS2
−
26
−
mA
PS3
−
23
−
mA
PS4
−
145
200
mA
EN = Low
−
20
−
mA
VCC Rising
−
−
4.5
V
VCC Falling
4
−
−
V
Parameter
BIAS SUPPLY
VCC Voltage Range
VCC Quiescent Current
VCC UVLO
EN = High
PVCC Voltage Range
PVCC Quiescent Current
4.75
−
5.25
V
EN = Low (Shutdown)
−
−
1
mA
EN = High, No Switching
−
−
1.5
mA
5
−
20
V
VRAMP Rising
−
−
4.25
V
VRAMP Falling
3
−
−
V
VRAMP Voltage Range
VRAMP UVLO
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NCP81246
Table 4. ELECTRICAL CHARACTERISTICS − GENERAL (continued)
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Parameter
Test Conditions
Min
Typ
Max
Unit
Upper Threshold
0.8
−
−
V
Lower Threshold
−
−
0.3
V
Enable Delay Time
−
−
2.5
ms
Enable High Input Leakage Current
−
−
0.5
mA
CSP Pin Threshold Voltage
−
−
4.5
V
Phase Detect Timer
−
1.75
−
ms
Soft Start Slew Rate
−
15
−
mV/ms
Slew Rate Slow
−
15
−
mV/ms
Slew Rate Fast
−
30
−
mV/ms
3
−
−
V
ENABLE INPUT
PHASE DETECTION
DAC SLEW RATE
DRVON
Output High Voltage
Output Low Voltage
Rise Time
Fall Time
Internal Pull-Down Resistance
−
−
0.1
V
CL (PCB) = 20 pF
DVo = 10% to 90%
−
100
−
ns
−
2.5
−
ns
EN = Low
−
69.5
−
kW
TSENSE
115
120
125
mA
Alert# Assert Threshold
−
485
−
mV
Alert# De-Assert Threshold
−
513
−
mV
VR_Hot Assert Threshold
−
466
−
mV
VR_Hot De-Assert Threshold
−
490
−
mV
Bias Current
−40°C to 100°C
VR_Rdy OUTPUT
Output Low Saturation Voltage
IVR_RDY = −4 mA
−
−
0.3
V
Output Leakage Current When High
VR_RDY = 5 V
−1
−
1
mA
Rise Time
DVo = 10% to 90%
−
110
−
ns
Fall Time
1 kW Pull-Up to
3.3 V
CTOT = 45 pF
DVo = 90% to 10%
−
20
−
ns
VR_Rdy Delay Falling
Due to OVP
−
0.3
−
ms
Due to OCP
−
50
−
ms
VR_Hot#
Output Low Saturation Voltage
IVR_HOT = −4 mA
−
−
0.3
V
Output Leakage Current When High
VR_HOT = 5 V
−1
−
1
mA
0
−
2
V
−
−
1
LSB
ADC
Linear Input Voltage Range
Differential Non-Linearity (DNL)
8-Bits
Total Unadjusted Error (TUE)
−1
−
1
%
Conversion Time
−
10
−
ms
Conversion Rate
−
33
−
kHz
Power Supply Sensitivity
−
±1
−
%
Round Robin
−
90
−
ms
9.7
10
10.3
mA
IccMax
Bias Current
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NCP81246
Table 4. ELECTRICAL CHARACTERISTICS − GENERAL (continued)
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Parameter
Test Conditions
Min
Typ
Max
Unit
−
2.0
−
V
−
2.0
−
V
360
400
440
mV
IccMax
Full scale input voltage
OVP and UVP
Absolute Over Voltage Threshold
During Soft Start
Over Voltage Threshold Above DAC
VSP−VSN−VID Rising
Over Voltage Delay
VSP−VSN Rising to PWM Low
−
25
−
ns
Under Voltage Threshold Below
DAC
VSP−VSN−VID Falling
−
300
−
mV
−
5
−
ms
300
−
750
kHz
−
±10
−
%
VCC − 0.2
−
−
V
1.9
2
2.1
V
−
−
0.7
V
DVo = 10% to 90%
−
5
−
ns
DVo = 90% to 10%
−
5
−
ns
Under Voltage Delay
OSCILLATOR
Switching Frequency Range
Switching Frequency Accuracy
PWM OUTPUT
Output High Voltage
Sourcing 500 mA
Output Mid Voltage
No Load, Power State 2
Output Low Voltage
Sinking 500 mA
Rise Time
CL (PCB) = 50 pF
Fall Time
HIGH-SIDE MOSFET DRIVER
Pull-Up Resistance, Sourcing
Current
BST = PVCC
−
1.4
2.5
W
Pull-Down Resistance, Sinking
Current
BST = PVCC
−
0.9
2
W
HG Rise Time
PVCC = 5 V, CL = 3 nF, BST−SW = 5 V
6
12
27
ns
HG Fall Time
PVCC = 5 V, CL = 3 nF, BST−SW = 5 V
6
11
15
ns
HG Turn ON Propagation Delay
tpdhDRVH
CL = 3 nF
13
16
21
ns
SW Pull-Down Resistance
SW to GND
−
2
−
kW
HG Pull-Down Resistance
HG to SW, BST − SW = 0 V
−
292
−
kW
Pull-Up Resistance, Sourcing
Current
−
1.6
3.5
W
Pull-Down Resistance, Sinking
Current
−
0.5
1.5
W
LOW-SIDE MOSFET DRIVER
LGx Rise Time
3 nF Load
6
18
27
ns
LGx Fall Time
3 nF Load
6
12
25
ns
Dead-Time
LGx Turn-On Propagation Delay
tpdhDRVL
−
−
−
CLOAD = 3 nF
−
14
20
ns
EN = Low or EN = High and DRVL = HIGH
5
13
22
W
BOOST RECTIFIER
RON
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Based on design or characterisation data, not in production test.
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NCP81246
Table 5. ELECTRICAL CHARACTERISTICS − 2-PHASE RAIL SPECIFIC
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Test Conditions
Min
Typ
Max
Unit
−25
−
25
nA
VSP Input Voltage Range
−0.3
−
3
V
VSN Input Voltage Range
−0.3
−
0.3
V
Parameter
DIFFERENTIAL SUMMING AMP
Input Bias Current
VSP = VSN = 1.3 V
−3dB Bandwidth
CL = 20 pF, RL = 10 kW
−
22.5
−
MHz
Closed Loop DC Gain
VSP − VSN = 0.5 V to 1.3 V
−
1
−
V/V
ERROR AMPLIFIER
Input Bias Current
@1.3 V
−400
−
400
nA
Open Loop DC Gain
CL = 20 pF, RL = 10 kW
−
80
−
dB
Open Loop Unity Gain Bandwidth
CL = 20 pF, RL = 10 kW
−
20
−
MHz
Slew Rate
DVIN = 100 mV, G = −10 V/V
DVOUT = 1.5 V to 2.5 V, CL = 20 pF,
RL = 10 kW
−
5
−
V/ms
Maximum Output Voltage
ISOURCE = 2.0 mA
4
−
−
V
Minimum Output Voltage
ISINK = 2.0 mA
−
−
0.9
V
CSSUM = CSREF = 1.0 V
−8
−
8
mA
−2.5
−
2.5
mV
−
80
−
dB
−
10
−
MHz
3.5
−
−
V
−
−
0.1
V
−50
−
50
nA
0
−
2.3
V
CURRENT SUMMING AMPLIFIER
Input Bias Current
Offset Voltage (Vos) (Note 4)
Open Loop Gain
Open Loop Unity Gain Bandwidth
CL = 20 pF, RL = 10 kW
Maximum Output Voltage
ISOURCE = 2.0 mA
Minimum Output Voltage
ISINK = 0.5 mA
CURRENT BALANCE AMPLIFIERS
Input Bias Current
CSP1/2 = CSREF = 1.2 V
Common Mode Input Voltage Range
CSP1/2 = CSREF
Differential Mode Input Voltage
Range
CSREF = 1.2 V
−100
−
100
mV
Input Offset Voltage Matching
CSP1/2 = CSREF = 1.2 V
Measured from Average.
−1.6
−
1.6
mV
Current Sense Amplifier Gain
0 V < CSP1/2 − CSREF < 0.1 V
5.7
6
6.3
V/V
Multiphase Current Sense Gain
Matching
CSP1/2 = CSREF = 10 mV to 30 mV
−3.5
−
3.5
%
−
6
−
MHz
8.5
10
11.5
mA
−3dB Bandwidth
OVER−CURRENT PROTECTION
ILIM Threshold Current
(Delayed OCP Shutdown)
PS0
PS1, PS2, PS3
−
6.67
−
mA
ILIM Threshold Current
(Immediate OCP Shutdown)
PS0
13
15
17
mA
PS1, PS2, PS3
−
10
−
mA
Shutdown Delay
Immediate
−
300
−
ns
Shutdown Delay
Delayed
−
50
−
ms
ILIM Output Voltage Offset
ILIM sourcing 15 mA
Measured relative to CSREF
−1.5
−
1.5
mV
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10
NCP81246
Table 5. ELECTRICAL CHARACTERISTICS − 2-PHASE RAIL SPECIFIC (continued)
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Parameter
Test Conditions
Min
Typ
Max
Unit
−
−
0.25
mA
Iout OUTPUT
Output Offset Current
VILIM = 5 V
Output Source Current
ILIM Source Current = 20 mA
Current Gain
IIOUT / IILIM, RILIM = 20 kW RIOUT = 5 kW
DAC = 0.8 V, 1.25 V, 1.52 V
−
200
−
mA
9.5
10
10.5
A/A
V
MODULATORS
0% Duty Cycle
Comp Voltage for PWM Held Low
−
1.3
−
100% Duty Cycle
Comp Voltage for PWM Held High
VRAMP = 12 V
−
2.6
−
V
PWM Ramp Duty Cycle Matching
Comp = 2 V, PWM TON Matching
−
±3
−
%
PWM Phase Angle Error
−
±15
−
°
Ramp Feed Forward Voltage Range
5
−
20
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Based on design or characterisation data, not in production test.
Table 6. ELECTRICAL CHARACTERISTICS − SINGLE PHASE RAIL SPECIFIC
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Parameter
Test Conditions
Min
Typ
Max
Unit
Input Bias Current
−25
−
25
nA
VSP Input Voltage Range
−0.3
−
3
V
VSN Input Voltage Range
−0.3
−
0.3
V
gm
1.3
1.6
2.0
mS
Output Offset
−15
−
15
mA
ERROR AMPLIFIER
Open Loop Gain
ZL = (1 nF +1 kW) || 10 pF
−
73
−
dB
Source Current
DVIN = −200 mV
−
200
−
mA
Sink Current
DVIN = 200 mV
−
200
−
mA
−3dB Bandwidth
ZL = (1 nF +1 kW) || 10 pF
−
20
−
MHz
−50
−
50
nA
CURRENT SENSE AMPLIFIER
Input Bias Current
CSP = CSN = 1.2 V
Common Mode Input Voltage Range
CSP = CSN
0
−
2.3
V
Common Mode Rejection
CSP = CSN = 0.5 V to 1.2 V
60
80
−
dB
Differential Mode Input Voltage
Range
CSN = 1.2 V
−100
−
100
mV
Gain IOUT Output
0 V ≤ CSP−CSN ≤ 0.1 V
0.96
1
1.04
mS
Gain VSP and ILIM Outputs
0 V ≤ CSP−CSN ≤ 0.1 V
0.96
1
1.04
mS
−
6
−
MHz
−3dB Bandwidth
OVER-CURRENT PROTECTION
Output Offset Current
VILIM = 1.3 V
−1.5
−
1.5
mA
Maximum Output Current
0 V ≤ VILIM ≤ 1.3 V
130
−
−
mA
Maximum Output Voltage
IILIM = 100 mA
1.4
−
−
V
1.28
1.3
1.32
V
−
250
−
ns
−250
−
250
nA
Activation Threshold Voltage
Activation Delay
IOUT
Output Offset Current
0 V ≤ VIOUT ≤ 2.0 V
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11
NCP81246
Table 6. ELECTRICAL CHARACTERISTICS − SINGLE PHASE RAIL SPECIFIC (continued)
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Parameter
Test Conditions
Min
Typ
Max
Unit
IOUT
Maximum Output Current
0 V ≤ VIOUT ≤ 2.0 V
130
−
−
mA
Maximum Output Voltage
IIOUT = 100 mA
2.1
−
−
V
DROOP
Output Offset Current 1A
0 V ≤ VDROOP ≤ 1.8 V
−1800
−
1800
nA
Output Offset Current 1B
0 V ≤ VDROOP ≤ 1.8 V
−900
−
900
nA
Maximum Output Current
0 V ≤ VDROOP ≤ 1.8 V
130
−
−
mA
Maximum Output Voltage
IDROOP = 100 mA
1.8
−
−
V
−
±1.5
−
mV
ZCD COMPARATOR
Offset Accuracy
Referred to CSP − CSN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
tfDRVL
trDRVL
DRVL
tpdhDRVH trDRVH
DRVH−SW
tfDRVH
VTH
VTH
tpdhDRVL
SW
1V
NOTE: Timing is referenced to the 10% and the 90% points, unless otherwise stated.
Figure 5. Driver Timing Diagram
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12
NCP81246
Table 7. STATE TRUTH TABLE
State
VR_RDY Pin
Error AMP
Comp Pin
OVP & UVP
DRON Pin
POR
0 < VCC < UVLO
N/A
N/A
N/A
Resistive Pull
Down
Disabled
EN < Threshold
UVLO > Threshold
Low
Low
Disabled
Low
Start-Up Delay &
Calibration
EN > Threshold
UVLO > Threshold
Low
Low
Disabled
Low
DRON Fault
EN > Threshold
UVLO > Threshold
DRON < Threshold
Low
Low
Disabled
Resistive Pull
Up
Soft Start
EN > Threshold
UVLO > Threshold
DRON > High
High
Operational
Active/No Latch
High
Normal Operation
EN > Threshold
UVLO > Threshold
DRON > High
High
Operational
Active/Latching
High
Over Voltage
Low
N/A
DAC+OVP
High
Over Current
Low
Operational
Last DAC Code
Low
Vout = 0 V
Low: if Reg34h: bit 0 = 0;
High: if Reg34h: bit 0 = 1;
Clamped at
0.9 V
Disabled
High, PWM
Outputs in Low
State
www.onsemi.com
13
Method
of Reset
Driver Must
Release
DRON
to High
N/A
NCP81246
Controller
POR
VCC > UVLO
Disable
EN = 0
VCC < UVLO
EN = 1
Calibrate
Drive Off
2.5 ms and CAL DONE
Phase
Detect
OCP
Condition
VCCP > UVLO and DRON HIGH
Non-0 VBOOT
0 VBOOT
Soft Start
Ramp
Soft Start
Ramp
DAC = VID
DAC = VBOOT
OVP
VS > OVP
Normal
VR_RDY
VS > UVP
VS < UVP
UVP
Figure 6. State Diagram
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14
NCP81246
GENERAL
Configuration
Table 8 shows the available configurations, and the
pull-down resistor required on Pin 40 (PWM/
ADDR_VBOOT) to configure them.
The NCP81246 is a three-rail IMVP8 controller, with
three internal drivers. The NCP81246 is configured with the
two-phase, dual-edge controller providing V_Rail2.
Table 8. CONFIGURATIONS
2ph
Ph1
Ph2
1ph A
Addr
VBOOT
(V)
DRV1
PWM
TSENSE
1
0
x
x
2ph
16.2
1
1.2
x
x
22.1
1
0
x
28.7
1
0
x
35.7
1
0
x
43.2
1
1.2
51.1
1
61.9
1ph B
Addr
VBOOT
(V)
Addr
VBOOT
(V)
DRV3
TSENSE
0
0
x
1a
DRV2
2
1
x
N/A
(PSYS))
2ph
0
1.2
x
1a
2
1
x
N/A
(PSYS)
x
2ph
0
0
x
1a
2
1.05
x
N/A
(PSYS)
x
2ph
0
0
x
1a
2
0.95
x
N/A
(PSYS)
x
2ph
0
0
x
1a
2
1
x
N/A
(PSYS)
x
x
2ph
0
1.2
x
1a
2
1
x
N/A
(PSYS)
0
x
x
2ph
0
0
x
1a
2
1.05
x
N/A
(PSYS)
1
0
x
x
2ph
0
0
x
1a
2
0.95
x
N/A
(PSYS)
71.5
1
0
x
x
2ph
2
1
x
N/A
(PSYS)
0
0
x
1a
82.5
1
1.2
x
x
2ph
2
1
x
N/A
(PSYS)
0
1.2
x
1a
95.3
1
0
x
x
2ph
2
1.05
x
N/A
(PSYS)
0
0
x
1a
110
1
0
x
x
2ph
2
0.95
x
N/A
(PSYS)
0
0
x
1a
127
1
0
x
x
2ph
3
0
x
1a
0
0
x
1b
143
1
1.2
x
x
2ph
3
1.2
x
1a
0
1.2
x
1b
165
1
0
x
x
2ph
3
0
x
1a
0
0
x
1b
187
1
0
x
x
2ph
3
0
x
1a
0
0
x
1b
R
(kW)
10
DRV2
Switching Frequency Fsw
FSW is programmed on start-up with a pull-down on the
LG1 pin.
Table 9. SWITCHING FREQUENCY
Resistor
Rail1/Rail2
Rail3
6.81 kW
750 kHz
750 kHz
14 kW
600 kHz
600 kHz
21.5 kW
450 kHz
600 kHz
28.7 kW
300 kHz
450 kHz
Serial VID Interface (Intel proprietary interface)
For Intel proprietary interface communication details please contact Intel®, Inc.
www.onsemi.com
15
PWM
TSENSE
NCP81246
Interleaving
Two-Phase Rail Remote Sense Amplifier
In order to minimize stress on the input voltage and
simplify input filter design, the NCP81246 monitors the
phase-angle relationship between the rails used for Rail1
and Rail2. Small adjustments are made to keep phases of
both rails from turning on at the same time. Priority is given
to transient response, i.e. if a phase must turn on to respond
to a load increase, the phase will not be gated if the other rail
has a phase that is turned on. The feature is intended to
reduce loading on the input rail during steady-state
conditions. If either rail is operating in DCM mode, this
feature will be disabled.
A high performance high input impedance true
differential amplifier is provided to accurately sense the
output voltage of the regulator. The VSP and VSN inputs
should be connected to the regulator’s output voltage sense
points. The remote sense amplifier takes the difference of
the output voltage with the DAC voltage and adds the droop
voltage to
V DIFFOUT + ǒV VSP ) V VSNǓ ) ǒ1.3 V * V DACǓ )
) ǒV DROOP ) V CSREFǓ
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier. The non-inverting input of the error
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias.
Ultra-Sonic Mode
Ultra-Sonic Mode forces a minimum switching frequency
above audible range when a rail is in DCM mode.
Two-Phase Rail Voltage Compensation
The remote Sense Amplifier output is applied to a Type III
compensation network formed by the error amplifier and
external tuning components. The non-inverting input of the
error amplifier is connected to the same reference voltage
used to bias the Remote sense amplifier output.
Two-Phase Rail High Performance Voltage Error
Amplifier
A high performance error amplifier is provided for high
bandwidth transient performance. A standard type III
compensation circuit is normally used to compensate the
system.
RIN1
RF
CIN
(eq. 1)
CF
CF1
RIN2
−
VBIAS
+
COMP
ERROR AMP
Figure 7. Standard Type III Compensation Circuit
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16
NCP81246
Differential Current Feedback Amplifiers
sense element be no less than 0.5 mW for accurate current
balance. Fine tuning of this time constant is generally not
required. The individual phase current is summed into the
PWM comparator feedback this way current is balanced via
a current mode control approach.
Each phase of the two-phase rail has a low offset
differential amplifier to sense that phase current for current
balance and per phase OCP protection during soft-start.
The inputs to the CSNx and CSPx pins are high impedance
inputs. It is recommended that any external filter resistor
RCSN does not exceed 10 kW to avoid offset issues with
leakage current. It is also recommended that the voltage
RCSN
L PHASE
C CSN @ DCR
(eq. 2)
CSNx
CSPx
R CSN +
CCSN
VOUT
SWNx
DCR
LPHASE
1
2
Figure 8.
Two-Phase Rail Total Current Sense Amplifier
from the output side of the inductors to create a low
impedance virtual ground. The amplifier actively filters and
gains up the voltage applied across the inductors to recover
the voltage drop across the inductor series resistance (DCR).
Rth is placed near an inductor to sense the temperature of the
inductor. This allows the filter time constant and gain to be
a function of the Rth NTC resistor and compensate for the
change in the DCR with temperature.
The NCP81246 uses a patented approach to sum the phase
currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage
droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to
CSREF. The current signal is the difference between
CSCOMP and CSREF. The Rref(n) resistors sum the signals
CSN1
CSN2
RREF1
CREF
10 W
1 nF
RREF2
10 W
CSREF
SWN1
SWN2
−
RPH1
CSSUM
CSCOMP
+
CCS1
RPH2
CCS2
RCS2
RCS1
82.5 kW
35.7 kW
RTH
100 kW
Figure 9.
The DC gain equation for the current sensing:
R CS2 )
V CSCOMP*CSREF + *
R CS1@R TH
R CS1)R TH
R PH
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17
ǒ
@ I OUT
Total
@ DCR
Ǔ
(eq. 3)
NCP81246
Set the gain by adjusting the value of the RPH resistors.
The DC gain should be set to the output voltage droop. If the
voltage from CSCOMP to CSREF is less than 100 mV at
ICCMAX then it is recommend increasing the gain of the
CSCOMP amp. This is required to provide a good current
signal to offset voltage ratio for the ILIMIT pin. When no
droop is needed, the gain of the amplifier should be set to
provide ~100 mV across the current limit programming
resistor at full load. The NTC should be placed near the
closest inductor. The output voltage droop should be set with
the droop filter divider.
The pole frequency in the CSCOMP filter should be set
equal to the zero from the output inductor. This allows the
circuit to recover the inductor DCR voltage drop current
signal. CCS1 and CCS2 are in parallel to allow for fine tuning
of the time constant using commonly available values. It is
best to fine tune this filter during transient testing.
DCR @ 25°C
2
1
2
1
C67
510 pF
VSS_SENSE
Figure 10.
R VSN + C OUT @ R OUT @ 453.6 @ 10 6
C VSN +
R OUT @ C OUT
The signals CSCOMP and CSREF are differentially
summed with the output voltage feedback to add precision
voltage droop to the output voltage.
The current limit thresholds are programmed with
a resistor between the ILIMIT and CSCOMP pins.
The ILIMIT pin mirrors the voltage at the CSREF pin and
mirrors the sink current internally to IOUT (reduced by the
IOUT Current Gain) and the current limit comparators.
The 100% current limit trips if the ILIMIT sink current
exceeds 10 mA for 50 ms. The 150% current limit trips with
minimal delay if the ILIMIT sink current exceeds 15 mA. Set
the value of the current limit resistor based on the
CSCOMP-CSREF voltage as shown below.
R LIMIT +
R PH
CSREF
5
CSSUM
6
−
7
CSCOMP
+
Figure 11.
Droop + DCR @
R CS
(eq. 9)
R PH
Two-Phase Rail Programming IOUT
ǒ
@ I OUT
Total
@ DCR
10 m
Ǔ
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to ICC_MAX generates a 2 V signal on IOUT.
A pull-up resistor from 5 V VCC can be used to offset the
IOUT signal positive if needed.
(eq. 5)
or
R LIMIT +
(eq. 8)
R VSN
Two-Phase Rail Programming the Current Limit
R
@R
R CS2) CS1 TH
R CS1)R TH
(eq. 7)
Two-Phase Rail Programming DROOP
(eq. 4)
2 @ p @ L Phase
R68
2.1 kW
DROOP
FZ +
VSN
V CSCOMP*CSREF @ ILIMIT
10 m
(eq. 6)
(eq. 10)
2.0 V @ R LIMIT
R IOUT +
Two-Phase Rail Programming DAC Feed-Forward
Filter
10 @
The DAC feed-forward implementation is realized by
having a filter on the VSN pin. Programming RVSN sets the
gain of the DAC feed-forward and CVSN provides the time
constant to cancel the time constant of the system per the
following equations. COUT is the total output capacitance
and ROUT is the output impedance of the system.
www.onsemi.com
18
R
@R
R CS2) CS1 TH
R CS1)R TH
R PH
ǒ
@ I OUT
ICC_MAX
@ DCR
Ǔ
NCP81246
Programming ICC_MAX
resistor value must not produce a voltage at the FET gate that
will turn it on. Keeping the voltage less than 400 mV should
be safe.
IccMax_2ph:
A resistor to ground on the IMAX pin programs these
registers at the time the part is enabled. 10 mA is sourced
from these pins to generate a voltage on the program resistor.
The resistor value should be no less than 2 kW.
Design Note: Since ICC_MAX is multi-functioned with
LG, it is crucial that the LS FET is not turned on during
ICC_MAX programming. Source current and maximum
R IccMax2ph +
IccMax 2ph ) 32
127
@ 200 kW
IccMax_1ph: See Table 10 below.
Table 10. ICCMAX_1PH
Resistor
00h (IA)
Resistor
Other 02h/03h
6.8 kW
11 kW
23
5 kW
3
24
7.8 kW
4
14.1 kW
25
11 kW
5
17.2 kW
28
14.1 kW
6
22.6 kW
29
17.2 kW
7
26.5 kW
30
20.3 kW
8
29.5 kW
34
23.4 W
9
32.8 kW
35
36 kW
36
IccMax_2ph
DIFFOUT
FB
COMP
−
EA
+
RD
−
+
+
−
VSP
Detect
on
VSN
Figure 12.
www.onsemi.com
19
ROSC
Detect
(eq. 11)
NCP81246
Programming TSENSE
Temperature sense inputs are provided. A precision
current is sourced out the output of the TSENSE pin to
generate a voltage on the temperature sense network.
The voltage on the temperature sense input is sampled by the
internal A/D converter. A 100 k NTC similar to the VISHAY
ERT−J1VS104JA should be used. See the specification
table for the thermal sensing voltage thresholds and source
current.
TSENSE
RCOMP1
0.0 W
CFILTER
0.1 mF
RCOMP2
8.2 kW
AGND
RTNC
100 kW
AGND
Figure 13.
Precision Oscillator
feed-forward control by varying the ramp magnitude with
respect to the VRMP pin voltage. The VRMP pin also has
a UVLO function. The VRMP UVLO is only active after the
controller is enabled. The VRMP pin is high impedance
input when the controller is disabled.
The PWM ramp is changed according to the following,
A programmable precision oscillator is provided.
The clock oscillator serves as the master clock to the ramp
generator circuit. This oscillator is programmed during
start-up by a resistor to ground on the LG1/ROSC pin.
The oscillator generates triangle ramps that are 0.5~2.5 V
in amplitude depending on the VRMP pin voltage to provide
input voltage feed forward compensation.
V RAMPpk+pk
pp
+ 0.1 @ V VRMP
(eq. 12)
Programming the Ramp Feed-Forward Circuit
The ramp generator circuit provides the ramp used by the
PWM comparators. The ramp generator provides voltage
VIN
VRAMP_PP
Comp_IL
Duty
Figure 14.
Two-Phase Rail PWM Comparators
Gain Factor). The inverting input is connected to the
oscillator ramp voltage with a 1.3 V offset. The operating
input voltage range of the comparators is from 0 V to 3.0 V
and the output of the comparator generates the PWM output.
The non-inverting input of the comparator for each phase
is connected to the summed output of the error amplifier
(COMP) and each phase current (IL ⋅ DCR ⋅ Phase Balance
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20
NCP81246
frequency drift under all continuous mode operating
conditions. At light load the single-phase rails automatically
transition into DCM operation to save power.
During steady state operation, the duty cycle is centered
on the valley of the sawtooth ramp waveform. The steady
state duty cycle is still calculated by approximately
VOUT/VIN.
Single-Phase Rail Remote Sense Error Amplifier
A high performance, high input impedance, true
differential transconductance amplifier is provided to
accurately sense the regulator output voltage and provide
high bandwidth transient performance. The VSP and VSN
inputs should be connected to the regulator’s output voltage
sense points through filter networks describe in the Droop
Compensation and DAC Feedforward Compensation
sections. The remote sense error amplifier outputs a current
proportional to the difference between the output voltage
and the DAC voltage:
Two-Phase Rail Phase Detection Sequence
During start-up, the number of operational phases and
their phase relationship is determined by the internal
circuitry monitoring the CSP outputs. Normally, this rail
operates as a two-phase VCC_Rail2 PWM controller. If
CSP2_2ph is pulled high to VCC, the two-phase rail
operates as a single-phase rail.
Disable Single-Phase Rail
If the NCP81246 is to provide fewer than three rails, one
or both of the single-phase rails can be disabled by pulling
up their respective CSP pin. The main rail cannot be
disabled.
I COMP + gm @ ǒV DAC * ǒV VSP * V VSNǓǓ
(eq. 13)
This current is applied to a standard Type II compensation
network.
Single-Phase Rails
The architecture of the two single-phase rails makes use
of a digitally enhanced, high performance, current mode
RPM control method that provides excellent transient
response while minimizing transient aliasing. The average
operating frequency is digitally stabilized to remove
Single-Phase Rail Voltage Compensation
The Remote Sense Amplifier outputs a current that is
applied to a Type II compensation network formed by
external tuning components CLF, RZ and CHF.
DAC
+
gm
+
S
VSN
VSN
VSP
VSP
−
COMP
RZ
CHF
CLF
Figure 15.
Single-Phase Rail – Differential Current Feedback
Amplifier
Each single-phase controller has a low offset, differential
amplifier to sense output inductor current. An external
lowpass filter can be used to superimpose a reconstruction
of the AC inductor current onto the DC current signal sensed
across the inductor. The lowpass filter time constant should
match the inductor L/DCR time constant by setting the filter
pole frequency equal to the zero of the output inductor. This
makes the filter AC output mimic the product of AC inductor
current and DCR, with the same gain as the filter DC output.
It is best to perform fine tuning of the filter pole during
transient testing.
FZ +
FP +
2@p@
ǒ
DCR @ 25°C
(eq. 14)
2 @ p @ L Phase
1
Ǔ
R PHSP@ǒR TH)R CSSPǓ
R PHSP)R TH)R CSSP
(eq. 15)
@ C CSSP
Forming the lowpass filter with an NTC thermistor (RTH)
placed near the output inductor, compensates both the DC
gain and the filter time constant for the inductor DCR change
with temperature. The values of RPHSP and RCSSP are set
www.onsemi.com
21
NCP81246
based on the effect of temperature on both the thermistor and
inductor. The CSP and CSN pins are high impedance inputs,
but it is recommended that the lowpass filter resistance not
exceed 10 kW in order to avoid offset due to leakage current.
It is also recommended that the voltage sense element
(inductor DCR) be no less than 0.5 mW for sufficient current
accuracy. Recommended values for the external filter
components are:
C CSSP +
R PHSP)R TH)R CSSP
RPHSP = 7.68 kW
V CURR +
= 100 kW, Beta = 4300
R TH ) R CSSP
R PHSP ) R TH ) R CSSP
Current
Sense AMP
CSN
+
−
RAMP
@ I OUT @ DCR
(eq. 17)
RCSSP
CCSSP
COMP
PWM
Generator
@ DCR
RPHSP
CSP
AV = 1
(eq. 16)
Using 2 parallel capacitors in the lowpass filter allows fine
tuning of the pole frequency using commonly available
capacitor values.
The DC gain equation for the current sense amplifier
output is:
RCSSP = 14.3 kW
RTH
L PHASE
R PHSP@ǒR TH)R CSSPǓ
t
RTH
To Inductor
CURR
PWM
Figure 16.
The amplifier output signal is combined with the COMP
and RAMP signals at the PWM comparator inputs to
produce the Ramp Pulse Modulation (RPM) PWM signal.
maintain output voltage within limits during load transients
faster than those to which the regulation loop can respond.
In the NCP81246, a loadline is produced by adding a signal
proportional to output load current (VDROOP) to the output
voltage feedback signal – thereby satisfying the voltage
regulator at an output voltage reduced proportional to load
current. VDROOP is developed across a resistance between
the VSP pin and the output voltage sense point.
Single-Phase Rail – Loadline Programming (DROOP)
An output loadline is a power supply characteristic
wherein the regulated (DC) output voltage decreases by
a voltage VDROOP, proportional to load current. This
characteristic can reduce the output capacitance required to
+
+
VSN
VSN
VSP
VSP
CSNSSP
S
−
RDRPSP
To VCC_SENSE
gm
RDRPSP
CDRPSP
RPHSP
CSP
+
AV = 1
Current
Sense AMP
CSN
RCSSP
−
CCSSP
t
RTH
To Inductor
Figure 17.
V DROOP + R DRPSP @ gm @
R TH ) R CSSP
R PHSP ) R TH ) R CSSP
www.onsemi.com
22
@ I OUT @ DCR
(eq. 18)
NCP81246
upon each increment of the internal DAC following a DVID
UP command. A parallel RC network inserted into the path
from VSN to the output voltage return sense point,
VSS_SENSE, causes these current pulses to temporarily
decrease the voltage between VSP and VSN. This causes the
output voltage during DVID to be regulated slightly higher,
in order to compensate for the response of the Droop
function to the inductor current flowing into the charging
output capacitors. RFFSP sets the gain of the DAC
feed-forward and CFFSP provides the time constant to cancel
the time constant of the system per the following equations.
COUT is the total output capacitance of the system.
The loadline is programmed by choosing RDRPSP such
that the ratio of voltage produced across RDRPSP to output
current is equal to the desired loadline.
R DRPSP +
Loadline
gm @ DCR
@
R PHSP ) R TH ) R CSSP
(eq. 19)
R TH ) R CSSP
Single-Phase Rail − Programming the DAC
Feed-Forward Filter
The DAC feed-forward implementation for the
single-phase rail is the same as for the 2-phase rail.
The NCP81246 outputs a pulse of current from the VSN pin
DAC Feed-Forward Current
DAC
Feed-Forward
From Intel
proprietary
interface
Interface
DAC
DAC
CFFSP
+
+
gm
S
VSN
VSN
VSP
VSP
RFFSP
−
To VCC_SENSE
CSNSSP
Figure 18.
R FFSP +
Loadline @ C OUT
C FFSP +
(W)
1.35 @ 10 *9
200
R FFSP
(nF)
(eq. 20)
Single-Phase Rail – Programming the Current Limit
The current limit threshold is programmed with a resistor
(RILIMSP) from the ILIM pin to ground. The current limit
latches the single-phase rail off immediately if the ILIM pin
voltage exceeds the ILIM Threshold. Set the value of the
current limit resistor based on the equation shown below.
A capacitor must be placed in parallel with the
programming resistor to avoid false trips due to the effect of
the output ripple current.
RPHSP
CSP
+
AV = 1
Current
Sense AMP
CSN
RCSSP
−
CCSSP
gm
Over-Current
Programming
To Inductor
ILIM
RILIMSP
Over-Current
Comparators
OCP
t
RTH
OCP REF
Figure 19.
1.3 V
R ILIMSP +
gm @
R TH)R CSSP
R PHSP)R TH)R CSSP
(eq. 21)
@ I OUT
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23
LIMIT
@ DCR
NCP81246
Single-Phase Rail – Programming IOUT
scaled with an external resistor to ground such that a load
equal to ICCMAX generates a 2 V signal on IOUT.
A pull-up resistor from 5 V VCC can be used to offset the
IOUT signal positive if needed.
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
RPHSP
CSP
+
AV = 1
Current
Sense AMP
CSN
RCSSP
−
CCSSP
t
RTH
To Inductor
gm
IOUT
Current
Monitor
RIOUTSP
IOUT
Figure 20.
2V
R IOUTSP +
gm @
R TH)R CSSP
R PHSP)R TH)R CSSP
(eq. 22)
@ IccMax @ DCR
Single-Phase Rail PWM Comparators
inductor current, and stops when the artificial ramp plus
gained-up inductor current crosses the COMP voltage. Both
edges of the PWM signals are modulated. During a transient
event, the duty cycle can increase rapidly as the COMP
voltage increases with respect to the ramps, to provide
a highly linear and proportional response to the step load.
The non-inverting input of each comparator (one for each
phase) is connected to the summation of the output of the
error amplifier (COMP) and each phase current
(IL ⋅ DCR ⋅ Phase Current Gain Factor). The inverting input
is connected to the triangle ramp voltage of that phase.
The output of the comparator generates the PWM output.
A PWM pulse starts when the error amp signal (COMP
voltage) rises above the trigger threshold plus gained-up
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24
NCP81246
PROTECTION FEATURES
Under Voltage Lockouts
There are several under voltage monitors in the system.
Hysteresis is incorporated within the comparators.
The NCP81246 monitors the 5 V VCC supply as well as the
VRMP pin. The gate drivers monitor both the gate driver
VCC and the BST voltage. When the voltage on the gate
driver is insufficient it will pull DRON low and prevents the
controller from being enabled. The gate driver will hold
DRON low for a minimum period of time to allow the
controller to hold off it’s start-up sequence. In this case the
PWM is set to the MID state to begin soft start.
DAC
If DRON is Pulled Low
the Controller will Hold
Off its Start-Up
Gate Driver Pulls DRON Low during
Driver UVLO and Calibration
Figure 21. Gate Driver UVLO Restart
Soft Start
controller is enabled, the internal and external PWMs will be
set to 2.0 V MID state to indicate that the drivers should be
in diode mode. DRON will then be asserted. As the DAC
ramps the PWM outputs will begin to fire. Each phase will
move out of the MID state when the first PWM pulse is
produced. When a controller is disabled the PWM signal
will return to the MID state.
Soft start is implemented internally. A digital counter
steps the DAC up from zero to the target voltage based on the
predetermined SetVID_SLOW rate in the spec table.
The PWM signal will start out open with a test current to
collect data on Intel proprietary interface address and
VBOOT. After the configuration data is collected, if the
PWM Driver Disabled
Internal Test
Current Applied
MID State
until First PWM Pulse
or DAC Reaches Target
PWMx
DRON
VCC
Figure 22. Soft Start
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25
PWM Returns to MID State
when Controller is Disabled
NCP81246
Over Current Latch-Off Protection
CSSUM
Each of the NCP81246 rails compares a programmable
current-limit set point to the voltage from the output of its
current-summing amplifier. The level of current limit is set
with the resistor from the ILIM pin to CSCOMP (two-phase)
or to ground (single-phase rails).
RPH
RCS
RPH
−
+
Two-Phase Rail Over Current
RLIM
The current through the external resistor connected
between ILIM and CSCOMP is then compared to the
internal current-limit threshold. If the current generated
through this resistor into the ILIM pin (ILIM) exceeds the
internal current-limit threshold, an internal latch-off counter
starts, and the controller shuts down if the fault is not
removed after 50 ms (immediately shut down for 150% of
current-limit threshold) after which the outputs will remain
disabled until the VCC voltage or EN is toggled.
The voltage swing of CSCOMP cannot go below ground.
This limits the voltage drop across the DCR through the
current balance circuitry. An inherent per-phase current
limit protects individual phases if one or more phases stop
functioning because of a faulty component.
The over-current limit is programmed by a resistor on the
ILIM pin. The resistor value can be calculated by the
following equations.
Equation related to the NCP81246:
I LIM @ DCR @
R ILIM +
R CS
R PH
ILIM
CSREF
Figure 23.
Under Voltage Monitor
The output voltage is monitored at the output of the
differential amplifier for UVLO. If the output falls more
than 300 mV below the DAC−DROOP voltage the UVLO
comparator will trip sending the VR_RDY signal low.
Over Voltage Protection
The output voltage is also monitored at the output of the
differential amplifier for OVP. During normal operation, if
the output voltage exceeds the DAC voltage by 400 mV, the
VR_RDY flag goes low, and the output voltage will be
ramped down to 0 V. At the same time, the high side gate
drivers are all turned off and the low side gate drivers are all
turned on. The part will stay in this mode until the VCC
voltage or EN is toggled.
(eq. 23)
I CL
Where ICL =10 mA
VCC
UVLO Rising
OVP Threshold
2.0 V
CSCOMP
DAC + ~400 mV
DAC
DRON
Figure 24. OVP Threshold Behavior
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26
NCP81246
2.0 V
OVP Threshold
VOUT
DAC
DRON
PWM
Figure 25. OVP Behavior at Start-Up
OVP Threshold
DAC
VSP_VSN
OVP
Triggered
Latch Off
PWM
Figure 26. OVP during Normal Operation Mode
During start-up, the OVP threshold is set to 2.0 V. This allows the controller to start up without false triggering the OVP.
www.onsemi.com
27
NCP81246
PACKAGE DIMENSIONS
QFN52 6x6, 0.4P
CASE 485BE
ISSUE B
PIN ONE
LOCATION
ÉÉÉ
ÉÉÉ
ÉÉÉ
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
EXPOSED Cu
TOP VIEW
A
(A3)
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÉÉÉ
ÉÉÉ
0.10 C
0.10 C
L
L
A B
D
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
L2
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
0.08 C
A1
NOTE 4
SIDE VIEW
C
D2
DETAIL C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.15
0.25
6.00 BSC
4.60
4.80
6.00 BSC
4.60
4.80
0.40 BSC
0.30 REF
0.25
0.45
0.00
0.15
0.15 REF
K
14
L2
DETAIL A
L2
27
DETAIL C
8 PLACES
SOLDERING FOOTPRINT*
E2
52X
6.40
4.80
L
1
52
52X
0.63
40
52X
e
BOTTOM VIEW
b
0.07 C A B
0.05 C
NOTE 3
4.80
6.40
0.11
0.49
DETAIL D
PKG
OUTLINE
8 PLACES
0.40
PITCH
52X
DETAIL D
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
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NCP81246/D