NCV887200 Automotive Grade Non-Synchronous Boost Controller The NCV887200 is an adjustable output non−synchronous boost controller which drives an external N−channel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate driver. Protection features include internally−set soft−start, undervoltage lockout, cycle−by−cycle current limiting, hiccup−mode short−circuit protection and thermal shutdown. Additional features include low quiescent current sleep mode and externally−synchronizable switching frequency. Features • • • • • • • • • • • • • Peak Current Mode Control with Internal Slope Compensation 1.2 V ±2% Reference voltage Fixed Frequency Operation Wide Input Voltage Range of 4.8 V to 40 Vdc, 45 V Load Dump Input Undervoltage Lockout (UVLO) Extended UVLO Hysteresis Allows Continuous Operation with a Reverse Polarity Protection Diode Internal Soft−Start Low Quiescent Current in Sleep Mode Cycle−by−Cycle Current Limit Protection Hiccup−Mode Overcurrent Protection (OCP) Hiccup−Mode Short−Circuit Protection (SCP) Thermal Shutdown (TSD) This is a Pb−Free Device www.onsemi.com MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 8 1 887200 ALYW G 1 887200 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS EN/SYNC 1 8 VFB ISNS 2 7 VC GND 3 6 VIN GDRV 4 5 VDRV (Top View) ORDERING INFORMATION Device Package Shipping† NCV887200D1R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2015 December, 2015 − Rev. 8 1 Publication Order Number: NCV887200/D NCV887200 6 TEMP VDRV FAULT LOGIC EN/SYNC SYNC 1 OSC SC VC 5 CDRV VDRV Cg L D Vo CLK 7 DRIVE LOGIC PWM EN/ Vg VIN 4 2 CL CSA 3 + ISNS GND CC Co RSNS RF1 SCP RC Q GDRV 8 Gm VFB RF2 SS Vref Figure 1. Simplified Block Diagram and Application Schematic PACKAGE PIN DESCRIPTIONS Pin No. Pin Symbol 1 EN/SYNC 2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. An RGND = 15 kW (typical) GDRV−GND resistor is strongly recommended. 5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass with a 1.0 mF ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addition to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. Function Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled into sleep mode when this pin is brought low for longer than the enable time−out period. www.onsemi.com 2 NCV887200 ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated) Rating Value Unit −0.3 to 40 V Peak Transient Voltage (Load Dump on VIN) 45 V Dc Supply Voltage (VDRV, GDRV) 12 V −0.3 to 6 V −0.3 to 3.6 V −0.3 to 6 V Dc Supply Voltage (VIN) Peak Transient Voltage (VFB) Dc Voltage (VC, VFB, ISNS) Dc Voltage (EN/SYNC) Dc Voltage Stress (VIN − VDRV)* −0.7 to 45 V Operating Junction Temperature −40 to 150 °C Storage Temperature Range −65 to 150 °C Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C 265 peak °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage. PACKAGE CAPABILITIES Characteristic ESD Capability (All Pins) Human Body Model Machine Model Value Unit w2.0 w200 kV V 1 − 100 °C/W Moisture Sensitivity Level Package Thermal Resistance Junction−to−Ambient, RqJA (Note 1) 1. 1 in2, 1 oz copper area used for heatsinking. Device Variations The NCV8872 features several variants to better fit a multitude of applications. The table below shows the typical values of parameters for the parts that are currently available. TYPICAL VALUES Part No. Dmax fs tss Sa Vcl Isrc Isink VDRV SCE NCV887200 92% 675 kHz 1.9 ms 34 mV/ms 200 mV 575 mA 375 mA 8.4 V Y DEFINITIONS Symbol Dmax Characteristic Maximum Duty Cycle Symbol Characteristic fs Switching Frequency Current Limit Trip Voltage Sa Slope Compensating Ramp Vcl Isink Gate Drive Sinking Current VDRV Drive Voltage www.onsemi.com 3 Symbol Characteristic tss Soft−Start Time Isrc Gate Drive Sourcing Current SCE Short Circuit Enable NCV887200 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 4.8 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit GENERAL Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, TJ = 25°C − 2.0 − mA Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C − 2.0 6.0 mA Quiescent Current, No switching Iq,off Into VIN pin, EN = 1, No switching − 1.5 2.5 mA Quiescent Current, Switching, Normal Operation Iq,on Into VIN pin, EN = 1, Switching − 3.0 6.0 mA OSCILLATOR Minimum Pulse Width ton,min 90 115 140 ns Maximum Duty Cycle Dmax 91 92 93.5 % Switching Frequency fs 608 675 742 kHz Soft−Start Time tss 1.55 1.90 2.25 ms Soft−Start Delay tss,dly − 200 280 ms 30 34 38 mV/ms − 5.0 10 mA Slope Compensating Ramp From start of switching with VFB = 0 until reference voltage = VREF From EN → 1 until start of switching with VFB = 0 with VC pin compensation network disconnected Sa ENABLE/SYNCHRONIZATION EN/SYNC Pull−Down Current IEN/SYNC EN/SYNC Input High Voltage Vs,ih 2.0 − 5.0 V EN/SYNC Input Low Voltage Vs,il 0 − 800 mV EN/SYNC Time−Out Ratio %ten From SYNC falling edge, to oscillator control (EN high) or shutdown (EN low), Percent of typical switching period − − 350 % Percent of fs − − 80 % 1.1 − − MHz − 50 100 ns 25 − 75 % Input−to−output gain at dc, ISNS v 1 V 0.9 1.0 1.1 V/V 2.5 − − MHz SYNC Minimum Frequency Ratio SYNC Maximum Frequency %fsync,min VEN/SYNC = 5 V fsync,max Synchronization Delay ts,dly Synchronization Duty Cycle Dsync From SYNC falling edge to GDRV falling edge CURRENT SENSE AMPLIFIER Low−Frequency Gain Acsa Bandwidth BWcsa Gain of Acsa − 3 dB ISNS Input Bias Current Isns,bias Out of ISNS pin Current Limit Threshold Voltage Vcl Voltage on ISNS pin Current Limit, Response Time tcl CL tripped until GDRV falling edge, VISNS = Vcl(typ) + 60 mV Overcurrent Protection, Threshold Voltage %Vocp Overcurrent Protection, Response Time tocp Percent of Vcl From overcurrent event, Until switching stops, VISNS = VOCP + 40 mV − 30 50 mA 180 200 220 mV − 80 125 ns 125 150 175 % − − 125 ns 0.9 1.25 1.6 mS VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER Transconductance gm,vea VEA Output Resistance Ro,vea VFB Input Bias Current Ivfb,bias Reference Voltage VEA Maximum Output Voltage VFB – Vref = ± 20 mV 2.0 − − MW − 0.5 2.0 mA Vref 1.176 1.200 1.224 V Vc,max 2.5 − − V Current out of VFB pin www.onsemi.com 4 NCV887200 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 4.8 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit − − 0.3 V VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER VEA Minimum Output Voltage Vc,min VEA Sourcing Current Isrc,vea VEA output current, Vc = 2.0 V 80 100 − mA VEA Sinking Current Isnk,vea VEA output current, Vc = 0.7 V 80 100 − mA GATE DRIVER Sourcing Current Isrc VDRV ≥ 6 V, VDRV − VGDRV = 2 V 400 575 − mA Sinking Current Isink VGDRV ≥ 2 V 250 375 − mA VIN − VDRV, IvDRV = 25 mA − 0.3 0.6 V VIN − VDRV = 1 V 35 45 − mA Driving Voltage Dropout Driving Voltage Source Current Vdrv,do Idrv Backdrive Diode Voltage Drop Vd,bd VDRV − VIN, Id,bd = 5 mA − − 0.7 V Driving Voltage VDRV IVDRV = 0.1 − 25 mA 8.0 8.4 8.8 V Undervoltage Lock−Out, Threshold Voltage Vuvlo VIN falling VIN rising 4.6 − 4.75 5.23 4.90 5.45 V Undervoltage Lock−Out, Hysteresis Vuvlo,hys VIN rising 350 500 − mV Startup blanking period %tscp,dly From start of soft−start, Percent of tss 100 120 150 % Hiccup−mode period %thcp,dly From shutdown to start of soft−start, Percent of tss 70 85 100 % VFB as percent of Vref 60 67 75 % tscp From VFB < Vscp to stop switching − 35 100 ns Thermal shutdown threshold Tsd TJ rising 160 170 180 °C Thermal shutdown hysteresis Tsd,hys TJ falling 10 15 20 °C Thermal shutdown delay tsd,dly From TJ > Tsd to stop switching − − 100 ns UVLO SHORT CIRCUIT PROTECTION Short circuit threshold voltage Short circuit delay %Vscp THERMAL SHUTDOWN www.onsemi.com 5 NCV887200 TYPICAL PERFORMANCE CHARACTERISTICS 7 5.5 Iq,on, QUIESCENTCURRENT (mA) Iq,sleep, SLEEP CURRENT (mA) TJ = 25°C 6 5 4 3 2 1 0 5.0 4.5 4.0 TJ = 25°C, VIN = 13.2 V 3.5 0 10 20 30 VIN, INPUT VOLTAGE (V) 40 0 Figure 2. Sleep Current vs. Input Voltage 3.46 Iq,on, QUIESCENTCURRENT (mA) Iq,sleep, SLEEP CURRENT (mA) VIN = 13.2 V 5 4 3 2 1 0 50 100 150 3.42 3.40 3.38 3.36 3.34 TJ, JUNCTION TEMPERATURE (°C) 10 60 110 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Sleep Current vs. Temperature Figure 5. Quiescent Current vs. Temperature NORMALIZED CURRENT LIMIT (25°C) ton,min MINIMUM ON TIME (ns) VIN = 13.2 V 3.44 F = 675 kHz S 3.32 −40 200 125 123 121 119 117 115 −40 1000 Figure 3. Quiescent Current vs. Switching Frequency 6 0 −50 200 400 600 800 fs, SWITCHING FREQUENCY (kHz) 10 60 110 TJ, JUNCTION TEMPERATURE (°C) 160 1.010 1.005 1.000 0.995 0.990 −40 Figure 6. Minimum On Time vs. Temperature 10 60 110 TJ, JUNCTION TEMPERATURE (°C) Figure 7. Normalized Current Limit vs. Temperature www.onsemi.com 6 160 160 NCV887200 TYPICAL PERFORMANCE CHARACTERISTICS 7 Vref, REFERENCE VOLTAGE (V) Ienable, PULLDOWN CURRENT (mA) 1.205 1.203 1.201 1.199 1.197 5 4 3 2 1 0 TJ, JUNCTION TEMPERATURE (°C) 2 3 4 Venable, VOLTAGE (V) Figure 8. Reference Voltage vs. Temperature Figure 9. Enable Pulldown Current vs. Voltage 10 60 110 160 0 1 8.0 Ienable, PULLDOWN CURRENT (mA) 1.195 −40 TJ = 25°C 6 7.5 7.0 6.5 6.0 5.5 5.0 −40 10 60 110 TJ, JUNCTION TEMPERATURE (°C) Figure 10. Enable Pulldown Current vs. Temperature www.onsemi.com 7 160 5 6 NCV887200 THEORY OF OPERATION VIN L VOUT Oscillator GDRV S Q Gate Drive PWM Comparator − R CO RL + + + Voltage Error ISNS − CSA VFB − + VEA NCV8872 Compensation Figure 11. Current Mode Control Schematic Current Mode Control If the voltage across the current sense resistor exceeds the over current threshold voltage the device enters over current hiccup mode. The device will remain off for the hiccup time and then go through the soft−start procedure. The NCV887200 incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on−time of the power switch. The oscillator is used as a fixed−frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and the error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse−by−pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows for a simpler compensation. The NCV8872 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. Short Circuit Protection If the short circuit enable bit is set (SCE = Y) the device will attempt to protect the power MOSFET from damage. When the output voltage falls below the short circuit trip voltage, after the initial short circuit blanking time, the device enters short circuit latch off. The device will remain off for the hiccup time and then go through the soft−start. EN/SYNC The Enable/Synchronization pin has three modes. When a dc logic high (CMOS/TTL compatible) voltage is applied to this pin the NCV887200 operates at the programmed frequency. When a dc logic low voltage is applied to this pin the NCV887200 enters a low quiescent current sleep mode. When a square wave of at least %fsync,min of the free running switching frequency is applied to this pin, the switcher operates at the same frequency as the square wave. If the signal is slower than this, it will be interpreted as enabling and disabling the part. The falling edge of the square wave corresponds to the start of the switching cycle. Current Limit The NCV887200 features two current limit protections, peak current mode and over current latch off. When the current sense amplifier detects a voltage above the peak current limit between ISNS and GND after the current limit leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. Set the current limit with a resistor from ISNS to GND, with R = VCL / Ilimit. UVLO Input Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VIN is too low to support the internal rails and power the controller. The IC will start up when enabled and VIN surpasses the UVLO threshold plus the UVLO hysteresis and will shut down when VIN drops below the UVLO threshold or the part is disabled. www.onsemi.com 8 NCV887200 Internal Soft−Start Both duty cycles will actually be higher due to power loss in the conversion. The exact duty cycles will depend on conduction and switching losses. If the maximum input voltage is higher than the output voltage, the minimum duty cycle will be negative. This is because a boost converter cannot have an output lower than the input. In situations where the input is higher than the output, the output will follow the input, minus the diode drop of the output diode and the converter will not attempt to switch. If the calculated Dmax is higher the Dmax of the NCV887200, the conversion will not be possible. It is important for a boost converter to have a restricted Dmax, because while the ideal conversion ration of a boost converter goes up to infinity as D approaches 1, a real converter’s conversion ratio starts to decrease as losses overtake the increased power transfer. If the converter is in this range it will not be able to regulate properly. If the following equation is not satisfied, the device will skip pulses at high VIN: To insure moderate inrush current and reduce output overshoot, the NCV887200 features a soft start which charges a capacitor with a fixed current to ramp up the reference voltage. This fixed current is based on the switching frequency, so that if the NCV887200 is synchronized to twice the default switching frequency the soft start will last half as long. VDRV An internal regulator provides the drive voltage for the gate driver. Bypass with a ceramic capacitor to ground to ensure fast turn on times. The capacitor should be between 0.1 mF and 1 mF, depending on switching speed and charge requirements of the external MOSFET. GDRV An RGND = 15 kW (typical) GDRV−GND resistor is strongly recommended. APPLICATION INFORMATION D min w t on(min) fs Design Methodology This section details an overview of the component selection process for the NCV8872 in continuous conduction mode boost. It is intended to assist with the design process but does not remove all engineering design work. Many of the equations make heavy use of the small ripple approximation. This process entails the following steps: 1. Define Operational Parameters 2. Select Current Sense Resistor 3. Select Output Inductor 4. Select Output Capacitors 5. Select Input Capacitors 6. Select Feedback Resistors 7. Select Compensator Components 8. Select MOSFET(s) 9. Select Diode 10. Determine Feedback Loop Compensation Network Where: fs: switching frequency [Hz] ton(min): minimum on time [s] 2. Select Current Sense Resistor Current sensing for peak current mode control and current limit relies on the MOSFET current signal, which is measured with a ground referenced amplifier. The easiest method of generating this signal is to use a current sense resistor from the source of the MOSFET to device ground. The sense resistor should be selected as follows: RS + Where: RS: sense resistor [W] VCL: current limit threshold voltage [V] ICL: desire current limit [A] 3. Select Output Inductor 1. Define Operational Parameters The output inductor controls the current ripple that occurs over a switching period. A high current ripple will result in excessive power loss and ripple current requirements. A low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. A good starting point for peak to peak ripple is around 20−40% of the inductor current at the maximum load at the worst case VIN, but operation should be verified empirically. The worst case VIN is half of VOUT, or whatever VIN is closest to half of VOUT. After choosing a peak current ripple value, calculate the inductor value as follows: Before beginning the design, define the operating parameters of the application. These include: VIN(min): minimum input voltage [V] VIN(max): maximum input voltage [V] VOUT: output voltage [V] IOUT(max): maximum output current [A] ICL: desired typical cycle-by-cycle current limit [A] From this the ideal minimum and maximum duty cycles can be calculated as follows: D min + 1 * D max + 1 * V CL I CL V IN(max) V OUT L+ V IN(min) V OUT www.onsemi.com 9 V IN(WC) D WC DI L,max f s NCV887200 8. Select MOSFET(s) Where: VIN(WC): VIN value as close as possible to half of VOUT [V] DWC: duty cycle at VIN(WC) DIL,max: maximum peak to peak ripple [A] The maximum average inductor current can be calculated as follows: I L,AVG + In order to ensure the gate drive voltage does not drop out the MOSFET(s) chosen must not violate the following inequality: Q g(total) v V OUTI OUT(max) Where: Qg(total): Total Gate Charge of MOSFET(s) [C] Idrv: Drive voltage current [A] fs: Switching Frequency [Hz] The maximum RMS Current can be calculated as follows: V IN(min)h The Peak Inductor current can be calculated as follows: I L,peak + I L,avg ) DI L,max 2 I Q(max) + I out Where: IL,peak: Peak inductor current value [A] The output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. The steady state output ripple associated with the output capacitors can be calculated as follows: DI OUT(max) fC OUT ) ǒ I OUT(max) 1*D ) V IN(min)D 2fL Ǔ V Q(max) + V OUT(max) 9. Select Diode The output diode rectifies the output current. The average current through diode will be equal to the output current: R ESR I D(avg) + I OUT(max) The capacitors need to survive an RMS ripple current as follows: I Cout(RMS) + I OUT Ǹ D WC D ) WC 12 DȀ WC ǒ DȀ WC L R OUT T SW Ǔ Additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: V D(max) + V OUT(max) 2 The maximum power dissipation in the diode can be calculated as follows: P D + V f (max) I OUT(max) The use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. Where: Pd: Power dissipation in the diode [W] Vf(max): Maximum forward voltage of the diode [V] 5. Select Input Capacitors The input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. I Cin(RMS) + 10. Determine Feedback Loop Compensation Network The purpose of a compensation network is to stabilize the dynamic response of the converter. By optimizing the compensation network, stable regulation response is achieved for input line and load transients. Compensator design involves the placement of poles and zeros in the closed loop transfer function. Losses from the boost inductor, MOSFET, current sensing and boost diode losses also influence the gain and compensation expressions. The OTA has an ESD protection structure (RESD ≈ 502 W, data not provided in the datasheet) located on the die between the OTA output and the IC package compensation pin (VC). The information from the OTA PWM feedback control signal (VCTRL) may differ from the IC-VC signal if R2 is of similar order of magnitude as RESD . The compensation and gain expressions which follow take influence from the OTA output impedance elements into account. Type-I compensation is not possible due to the presence of RESD . The Figures 12 and 13 compensation networks correspond to a Type-II network in series with RESD . The resulting control-output transfer function is an accurate V IN(min) 2 D WC Lf sV OUT2 Ǹ3 6. Select Feedback Resistors The feedback resistors form a resistor divider from the output of the converter to ground, with a tap to the feedback pin. During regulation, the divided voltage will equal Vref. The lower feedback resistor can be chosen, and the upper feedback resistor value is calculated as follows: R upper + R lower ǸD DȀ The maximum voltage across the MOSFET will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: 4. Select Output Capacitors V OUT(ripple) + I drv fs ǒV out * V refǓ V ref The total feedback resistance (Rupper + Rlower) should be in the range of 1 kW – 100 kW. 7. Select Compensator Components Current Mode control method employed by the NCV8872 allows the use of a simple, Type II compensation to optimize the dynamic response according to system requirements. www.onsemi.com 10 NCV887200 • The CCM Boost control-output transfer function mathematical model of the IC in a boost converter topology. The model does have limitations and a more accurate SPICE model should be considered for a more detailed analysis: • The attenuating effect of large value ceramic capacitors in parallel with output electrolytic capacitor ESR is not considered in the equations. L rL VIN includes operating efficiency as a correction factor to improve modeling accuracy under low input voltage and high output current operating conditions where operating losses becomes significant. Vd VOUT rCf COUT Rds(on) VC GDRV R2 RESD C2 C1 ISNS VCTRL OTA Ri R0 VFB GND R1 Rlow Figure 12. NCV887200 Boost Converter OTA and Compensation www.onsemi.com 11 ROUT NCV887200 Vd VIN VOUT 1:N rCf Lp COUT Rds(on) ROUT VC GDRV R2 RESD C2 ISNS C1 VCTRL OTA R0 Ri VREF VFB GND R1 Rlow Figure 13. NCV887200 Flyback Converter OTA and Compensation Necessary equations for describing the modulator gain (Vctrl-to-Vout gain) Hctrl_output (f) are described next. Boost continuous conduction mode (CCM) and discontinuous conduction mode (DCM) transfer function expressions are summarized in Table 1. Flyback CCM and DCM transfer function expressions are summarized in Table 2. The following equations may be used to select compensation components R2 , C1 , C2 for Figures 12 & 13 power supply. Required input design parameters for analysis are: Vd = Output diode Vf (V) VIN = Power supply input voltage (V) N = Ns /Np (Flyback transformer turns ratio) Ri = Current sense resistor (W) RDS(on) = MOSFET RDS(on) (W) (Rsw_eq = RDS(on) + Ri for the boost continuous conduction mode (CCM) expressions) COUT = Bulk output capacitor value (F) rCF = Bulk output capacitor ESR (W) ROUT = Equivalent resistance of output load (W) Pout = Output Power (W) L = Boost inductor value or flyback transformer primary side inductance (H) rL = Boost inductor ESR (W) Ts = 1/fs , where fs = clock frequency (Hz) R1 and Rlow = Feedback resistor divider values used to set the output voltage (W) VOUT = Device specific output voltage (defined by R1 and Rlow values) (V) R0 = OTA output resistance = 3 MW Sa = IC slope compensation (e.g. 34 mV/ms for NCV887200) gm = OTA transconductance = 1.2 mS D = Controller duty ratio D’ = 1 − D www.onsemi.com 12 NCV887200 Table 1. BOOST CCM AND DCM TRANSFER FUNCTION EXPRESSIONS CCM Duty Ratio (D) ȡ ȧ ȧ ȧ Ȣ -V OUT DCM ƪ 2R OUTV dV IN* R sw_eq)R OUT Ǹ ǒ ǒ V IN V OUT *2 V OUT 2 Ǔ ǒ VOUT/VIN DC Conversion Ratio (M) Ǹ2tLM(M * 1) L Where: t L + R OUTT s Ǔ 1 1 1*D 2 ǒ Ǹ 1) 1) 2D 2 tL Ǔ V IN * I Laveǒr L ) R sw_eqǓ Inductor On-slope (Sn ), V/s Ri L Where average inductor current: Compensation Ramp (mc ) (1 * D) L Low Frequency Modulator Pole (wp1 ) 2 V IN I Lave + P out L Sa 1) Sn Sn 1 1 r CFC OUT r CFC OUT ǒ r CFR OUT R OUT * r CF ) R OUT Ǔ * rL R OUT L M 2L Ts 2 ) mc R OUT LM 3 1 R CFC OUT C OUT High Frequency Modulator Pole (wp2 ) 2F SW p Sampling Double Pole (wn ) 2M * 1 @ M*1 ǒ Ǔ − 1 1*M 2 D − Ts Sampling Quality Coefficient (Qp ) Ri V INh Sa 1) Cout ESR Zero (wz1 ) 1 − p(m c(1 * D) * 0.5) Fm 1 ǒ R OUTT s 1 Sa 2M ) ) 2 Sn LM 2 Hd Control-Output Transfer Function (Hctrl_output (f)) ȣ ȧ ȧ ȧ Ȥ R OUTV IN 2)2R sw_eqV INV OUT*4V dR sw_eqV IN R OUT )R sw_eq 2V OUT 2 -4R sw_eqV OUT 2*4r LV dV IN*4r LV OUT 2 2R OUT V OUT 2 ) V dV IN Right-Half-Plane Zero (wz2 ) Ǔƫ 1 Ǔ S nm cT s hR OUT 2V OUT Ri D F mH d ǒ 2pf 1 )jw p1 Ǔǒ z2 1)j 2pf 2 2pf ) ǒj w Ǔ n w nQ p www.onsemi.com 13 M*1 2M * 1 ǒ1 ) j w2pfǓǒ1 * j w2pfǓ ǒ1 ) j w2pfǓǒ1 * j w2pfǓ z1 @ Ǔ F mH d z1 ǒ 2pf 1 )jw p1 Ǔǒ z2 2pf 1 ) jw p2 Ǔ NCV887200 Table 2. FLYBACK CCM AND DCM TRANSFER FUNCTION EXPRESSIONS CCM DCM Duty ratio (D) V OUT V OUT V OUT ) NV IN VOUT/VIN DC Conversion Ratio (M) Compensation Ramp (mc ) Ǹ2 @ tL V IN V IN Cout ESR Zero (wz1 ) Right-Half-Plane Zero (wz2 ) Ri Lp Sa 1) 1 r CFC OUT (1 * D) R OUT R OUT DL pN 2 N 2L @ p 1 M(M ) 1) Ǔ 2 R OUTC OUT R OUTC OUT ǒ Ǔ wp2 − 1 ǒ 2F SW V IN R iN ǒ1 ) j w2pfǓǒ1 * j w2pfǓ 1 1)M 2pf 1 ) jw p1 F mH d Ǔ Ǹ 1 2t L ǒ1 ) j w2pfǓǒ1 * j w2pfǓ z2 z1 ǒ 2 S nm cT s R OUT F mH d 1 D 1 Ǔ Sa t L 1 ) 2 S n ) 2M ) 1 Control-output Transfer Function (Hctrl_output (f)) Sn 1 ǒ Hd Ri r CFC OUT Sa DȀ 3 t L 1 ) 2 S n ) 1 ) D DȀ 2 T sR OUT Sa 1) Sn 2 Fm N 2L p N@D 1*D Lp Modulator Pole (wp1 ) Where: t L + N@D Inductor On-slope (Sn ), V/s Ǹ2t L NV IN z1 ǒ 2pf 1 )jw p1 Ǔǒ z2 2pf 1 ) jw p2 Ǔ component value adjustments may become necessary when R2 ≤ ~10·Resd as a result of approximations for determining components R2 , C1 , C2 . Once the desired cross-over frequency (fc ) gain adjustment and necessary phase boost are determined from the Hctrl_output (f) gain and phase plots, the Table 3 equations may be used. It should be noted that minor compensation www.onsemi.com 14 NCV887200 Table 3. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES Desired OTA Gain at Cross-over Frequency fc (G) desired_G fc_gain_db 20 10 ǒq Desired Phase Boost at Cross-over Frequency fc (boost) Ǔ 180° * 90° Ǔ p ǒ ( ) margin * arg H ctrl_output fc p 180° w p1e Select OTA Compensation Zero to Coincide with Modulator Pole at fp1 (fz ) 2p f zf c ) f c 2 tan(boost) Resulting OTA High Frequency Pole Placement (fp ) f c * f z tan(boost) Compensation Resistor R2 V OUT f p * f z 1.2g m f pG Ǹ 1) Ǹ 1) Compensation Capacitor C1 ǒǓ 2 fc fp ǒǓ fz fp 1 2pf zR 2 Compensation Capacitor C2 1 2pf pG OTA DC Gain (G0_OTA ) @ R lowg m R low ) R 1 R low R low ) R 1 ȳ R R C 1* 1*4 ȧ ȧ 2 R R C ǒR ) R Ǔ C ȴ Ȳ ǒ Ǔ ȳ R R C 1 R )R ȱ 1) 1*4 ȧ ȧ 2 R R C ǒR ) R Ǔ C ȴ Ȳ ǒ Ǔȱ ȳ R ǒR ) R ǓC 1 R )R )R 1 * 1 * 4 ȧ ȧ 2 R ǒR ) R ǓC ǒR ) R ) R Ǔ C ȴ Ȳ ǒ Ǔȱ ȳ R ǒR ) R ǓC 1 R )R )R 1) 1*4 ȧ ȧ 2 R ǒR ) R ǓC ǒR ) R ) R Ǔ C ȴ Ȳ ǒ1 ) j w Ǔ ǒ1 ) j w2pf Ǔ Low Frequency Zero (wz1e ) 1 ǒR2 ) ResdǓȱ @ gm @ R0 2 esd 2 High Frequency Zero (wz2e ) 2 0 2 High Frequency Pole (wp2e ) 2 0 0 2 OTA Transfer Function (GOTA (f)) 2 0 2 esd esd 2 esd 2 2 2 1 esd Ǹ Ǹ esd esd 2 esd 2 2 2 1 esd Ǹ esd 2 esd 2 Low Frequency Pole (wp1e ) Ǹ 2 2 0 0 2 2 0 esd 2 2 1 esd 0 esd 2 esd 2 2 1 2pf z2e z1e -G 0_OTA The open-loop-response in closed-loop form to verify the gain/phase margins may be obtained from the following expression. ǒ 2pf 1 ) jw p1e Ǔǒ 2pf 1 )jw p2e Ǔ device. Simply connect the voltage you would like to boost to the inductor and connect the stable voltage to the VIN pin of the device. In boost configuration, the output of the converter can be used to power the device. In some cases it may be desirable to connect 2 sources to VIN pin, which can be accomplished simply by connecting each of the sources through a diode to the VIN pin. T(f) + G OTA(f) H ctrl_output(f) Low Voltage Operation If the input voltage drops below the UVLO or MOSFET threshold voltage, another voltage may be used to power the www.onsemi.com 15 NCV887200 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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