ENA1979 D

Ordering number : ENA1979
LV5636VH
Bi-CMOS Integrated Circuit
DC/DC converter
for BS/CS antennas
http://onsemi.com
Overview
LV5636VH integrates 1ch DC/DC boost converter and 1ch LDO. It is suitable as the power supply for BS/CS antennas
of LCD/PDP TV and BD recorders that require automatic recovery without IC destruction and malfunction when the
output is short-circuited.
Functions
DC/DC boost converter
• Soft-start time: 2.6ms
• Pulse by pulse over-current limiter
LDO
• Over-current limiter (Fold back)
ALL
• Under-voltage lockout
• Power good
• Output voltage setting resistor
• Frequency 1MHz operation
• Short circuit protector (constant timer: 1.6ms)
• Thermal shut-down protector
• Power good delay function
• Output voltage switching function (BS/CS)
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
VCC maximum supply voltage
VCC max
-0.3 to 25
V
LDOIN maximum input voltage
VLDOIN max
-0.3 to 30
V
SW maximum voltage
VSW max
Allowable power dissipation
Pd max
-0.3 to 30
V
1.45
W
Operating temperature
Operating junction temperature
Topr
-30 to 85
°C
Tjopr
-30 to 125
Storage temperature
°C
Tstg
-40 to 150
°C
*1
*1: When mounted on the specified printed circuit board (32.0mm ×38.0mm × 1.6mm), glass epoxy, double sides board
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
August, 2013
2111 SY 20110909-S00003 No.A1979-1/8
LV5636VH
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
VCC supply voltage
VCC
8 to 23
V
LDOIN input voltage
VLDOIN
8 to 28
V
SW voltage
VSW
-0.3 to 28
V
EN voltage
VEN
0 to 23
V
Electrical Characteristics at Ta = 25°C, VCC = 12V, VEN=VCTL=2V
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
ALL
Supply current
ICC
Switching is turned off
IOFF
EN=0V, LDOIN=0V
2.1
4.0
mA
10
µA
Reference voltage
VREF
LDO output voltage
LDOOUT1
CTL=High
(-2%)
15.9
(2%)
V
LDOOUT2
CTL=Low
(-2%)
11.7
(2%)
V
DCDC output voltage
1.26
V
DCDCOUT1
CTL=High
(-2%)
16.5
(2%)
V
DCDCOUT2
CTL=Low
(-2%)
12.3
(2%)
V
Enable voltage
VEN
Disable voltage
VDIS
EN input current
IEN
PGOOD threshold
VPG
2.0
V
VEN=2.0V
Power-good output is “good” when LDO is
0.4
V
10
µA
85
%
1.0
mA
85% or higher of the setting value.
PGOOD sink current
PGOOD leak current
IPG
Where power-good output is “no good” and
IPGLK
VPGOOD=0.5V.
Where power-good output is “good” and
10
µA
5.76
µA
VPGOOD=2V
PGDLY source current
IPGDLY
PGDLY threshold
VPGDLY
3.84
4.8
CTL high voltage
VCTLH
15V output setting
CTL low voltage
VCTLL
11V output setting
0.4
V
CTL input current
ICTL
VCTL=2V
20
µA
1.26
V
2.0
V
UVLO on voltage
VUVLO
7.0
V
Thermal shutdown temperature
TTSD
*2
155
°C
TSD hysteresis
THYS
*2
30
°C
DC/DC boost converter
FB output voltage “Low”
FB low
IN=2.0V, IFB=-20µA (sink)
FB output voltage “High”
HB high
IN=2.0V, IFB=20µA (source)
0.2
Soft-start time
TSS
Oscillator frequency
fOSC
1
MHz
Max ON duty
D max
85
%
SW ON resistance
RON
0.7
Ω
SW peak current
IPK
1.8
A
SCP timer
tSCP
1.6
ms
1.8
V
V
2.6
ms
LDO
Maximum output current
IO max
800
mA
Line regulation
RLN
16.5V ‹ LDOIN ‹ 21.5V
450
620
20
mV
Load regulation
RLD
10mA ‹ IO ‹ 300mA
50
mV
Dropout voltage
VDROP
IO=400mA
Short current
ISHORT
LDOOUT=GND
0.35
0.5
V
100
mA
*2: Design guarantee value.
No.A1979-2/8
LV5636VH
Package Dimensions
unit : mm (typ)
3313
6.5
1.3
7
0.22
0.15
0.65
1.5
0.1 (1.3)
1.5max
(2.35)
Allowable power dissipation, Pd max -- W
6.4
0.5
1
Pd max -- Ta
2.0
8
4.4
14
mm
mm3
Specified circuit board:32mm
glass epoxy board(both sides)
1.5
1.45
1.0
0.58
0.5
0
--30
0
30
60
90
120
Ambient temperature, Ta -- C
SANYO : HSSOP14(225mil)
Specified board (32mm×38mm×1.6mm, glass epoxy, double side board)
No.A1979-3/8
LV5636VH
Block diagram and Application circuit
VCC=12V
SW
12
C1
DC/DC
Boost
Converter
L1
VCC
VREG
OSC
C4
DC/DC OUT=16.5V/12.3V
14
P by P
D1
C2
VREF
DC/DCOUT
(LDOIN)
C5
IN
R1
5
-
+
+
-
+
LDOIN
2
C6
Soft
Start
R2
FB
6
PGOOD
SCP
8
R3
PGOOD
UVLO
ILimit
TSD
PGDLY
-
9
LDOOUT
+
C7
LDOOUT=15.9V/11.7V
1
EN
C3
IO=400mA
11
LDO
CTL
10
CTL=H: 15V setting
CTL=L: 11V setting
15V/11V
Control
SGND
PGND
7
Start and stop
Output waveform during start and stop is shown below.
Soft start
2.6ms
DC/DC boost output
LDO output
16.5V
15.9V
12V(=VCC)
4.0ms
0V
EN
No.A1979-4/8
LV5636VH
Pin arrangement
Fin
PGND
PGND
Fin
1
LDOOUT
SW 14
2
LDOIN
NC 13
3
NC
VCC 12
4
NC
EN 11
5
IN
CTL 10
6
FB
7
SGND
PGDLY 9
PGOOD 8
Top view
Pin function
Pin No.
Pin name
Function
1
LDOOUT
LDO output
2
LDOIN
LDO input
7
SGND
Signal ground
Equivalent circuit
2 LDOIN
1
LDOOUT
7 SGND
5
IN
DC/DC error amplifier input
LDOIN
IN
5
SGND 7
6
FB
DC/DC error amplifier output
FB 6
SGND 7
8
PGOOD
Power good output
8 PGOOD
7 SGND
Continued on next page.
No.A1979-5/8
LV5636VH
Continued from preceding page.
Pin No.
9
Pin name
PGDLY
Function
Equivalent circuit
PGDLY capacitor connection pin for delay time
setting
9 PGDLY
7 SGND
10
CTL
15V, 11V output voltage switching
VREG
CTL 10
SGND 7
11
EN
Enable
12
VCC
Power supply
VCC 12
EN 11
SGND 7
14
SW
DC/DC open drain output
Fin
PGND
Power ground
VREG
14 SW
Fin PGND
No.A1979-6/8
LV5636VH
Function overview
(1) UVLO (Under Voltage Lockout)
UVLO stops outputs of both DC/DC and to LDO to prevent malfunction when VCC decreases. UVLO operates when
VCC falls below the UVLO voltage. This function is a non-latch-type, and recovers these outputs automatically when
VCC exceeds the UVLO voltage.
(2) Power good
Power good notifies that the output voltage of LDO is within the range of the setting voltage. The output is judged to be
“power good” when both outputs are 85% or higher compared to the setting voltages. If the output voltage falls below
85%, PGOOD output becomes H→L (No Good). At “Good”→”No Good”, delay time can be set. It explains this at (3).
When EN=L (OFF), PGOOD output is H.
[ Power good circuit diagram]
Power supply (6V or less)
LDO
feed back
voltage
P.Good
Comp.
-
PGOOD
Pin
+
PGDLY
VREF*85%
Power good delay block
(At
(Example)
Good
No Good
H output
L output
Good
No GoodP.Good
,
Comp. output is delayed)
(3) Power good delay
If the output voltage of LDO falls below 85%, charge at 4.8µA constant starts to PGDLY capacitor for delay time
setting. When PGDLY voltage exceeds the threshold voltage (=VREF), PGOOD voltage reaches to the threshold
voltage, PGDLY capacitor using the following formula because delay time (tPGDLY) depends on capacitance.
CPGDLY = (IPGDLY × tPGDLY) / VREF
[PGDLY circuit diagram]
EN
LDO
output
PGDLY
Comp.
PGDLY
Pin
tPGDLY
PGOOD
CPGDLY
for delay
time setting
VREF
Discharge Tr.
(When P.Good Comp. is No
Good, discharge Tr. is OFF)
85%
PGDLY
voltage
Threshold
voltage(VREF)
PGOOD
output
Time
PGDLY capacitor is discharged.
When EN=L (OFF),
PGOOD output is H.
PGOOD output becomes H L(No Good)
PS No.A1979-7/8
LV5636VH
(4) Pulse-by-Pulse over current protection (P by P)
The P by P stops switch-on operation of a certain cycle by force when the current of power MOSFET reaches the
maximum output peak current.
[P by P circuit diagram]
Error
Amp.
PWM
Comp.
Power
Logic
Triangular
wave
P by P
Comp.
SW pin
The current of power_Tr. is constantly monitored.
If the peak current > 1.8A,
switching_on operation during
the cycle stops compulsorily
(5) Short circuit protector (SCP)
When output voltage of DC/DC decreases due to short-circuit; for example, SCP latches off the outputs of DC/DC and
LDO by timer.
When output voltage of DC/DC decreases and FB that is the error amplifier output turns to H, the internal counter starts,
latch-off occurs after 1.6ms.
To restart the output after latch-off, you need to input EN signal again.
(6) Output voltage switching function
Where CTL=High, 15V output setting is selected.
Where CTL=Low, 11V output setting is selected.
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PS No.A1979-8/8
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