NCP51145 DDR 1.8 Amp Source / Sink VTT Termination Regulator The NCP51145 is a linear regulator designed to supply a regulated VTT termination voltage for DDR−II, DDR−III, LPDDR−III and DDR−IV memory applications. The regulator is capable of actively sourcing and sinking ±1.8 A peak currents while regulating an output voltage to within ±20 mV. The output termination voltage is regulated to track VDDQ / 2 by two external voltage divider resistors connected to the PVCC, GND, and VREF pins. The NCP51145 incorporates a high−speed differential amplifier to provide ultra−fast response to line and load transients. Other features include source/sink current limiting, soft−start and on−chip thermal shutdown protection. www.onsemi.com MARKING DIAGRAMS 8 SOIC−8 EP D SUFFIX CASE 751BU 8 1 Features • • • • • • • • • • • • 1 For DDR VTT Applications, Source/Sink Currents: Supports DDR−II to ±1.8 A, DDR−III to ±1.5 A Supports LPDDR−III and DDR−IV to ±1.2 A Stable Using Ceramic−Only (Very Low ESR) Capacitors Integrated Power MOSFETs High Accuracy VTT Output at Full−Load Fast Transient Response Built−in Soft−Start Shutdown for Standby or Suspend Mode Integrated Thermal and Current−Limit Protection VTT Remote Sense Available in the DFN8 2x2mm Package These Devices are Pb−Free and are RoHS Compliant XXMG G 1 51145 XX M A Y WW G = Specific Device Code = Specific Device Code = Date Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS PVCC DDR−II / DR−III / DDR−IV SDRAM Termination Voltage Motherboard, Notebook, and VGA Card Memory Termination Set Top Box, Digital TV, Printers Low Power DDR−3LP 1 DFN8 MN SUFFIX CASE 506AA 1 Typical Applications • • • • 51145 AYWWG G GND VREF VTT 1 8 PVCC VCC NC NC VTT NC VTTS NC VCC VREF GND NC SOIC−8 EP DFN8 2x2, 0.5P (Top Views) 8 ORDERING INFORMATION Package Shipping† NCP51145PDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP51145MNTAG DFN−8 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2015 June, 2015 − Rev. 2 1 Publication Order Number: NCP51145/D NCP51145 NCP51145 SO8−EP Package PVCC = 1.0 to 5.5 V* 1 PVCC VCC C2 C3 R2 100k GND VREF R1 100k 2.2 2 3 Enable 5V R4 6 VTT VTT = 0.6 to 2.5 V* 4 C1 C4 R3 EP C1 = 1 to 100 nF Ceramic C2 = 10 mF Ceramic C3 = 1 mF C4 = 10 mF Ceramic R3 = Optional VTT Discharge Resistor N−Ch MOSFET = Optional Enable / Disable *For DDR2: PVCC = 1.8 V, VTT = 0.9 V DDR3: PVCC = 1.5 V, VTT = 0.75 V DDR4: PVCC = 1.2 V, VTT = 0.60 V Figure 1. Application Diagram PIN FUNCTION DESCRIPTION Pin No. SO8−EP Pin No. DFN8 Pin Name 1 1 PVCC Input voltage which supplies current to the output pin. CIN ^ ½ S COUT 2 4 GND Common Ground 3 5 VREF Buffered reference voltage input equal to ½ of VDDQ and active low shutdown pin. An external resistor divider dividing down the PVCC voltage creates the regulated output voltage. Pulling the pin to ground (0.15 V maximum) turns the device off. 4 2 VTT Regulator output voltage capable of sourcing and sinking current while regulating the output rail. COUT = 10 mF Ceramic, or greater 5, 7, 8 3, 7 NC True No Connect 6 8 VCC The VCC pin is a 5 V input pin that provides internal bias to the controller. PVCC should always be kept lower or equal to VCC. − 6 VTTS VTT Sense EP EP EPAD Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance. Description www.onsemi.com 2 NCP51145 ABSOLUTE MAXIMUM RATINGS Rating Input Supply Voltage Range (Vcc w PVCC) (Note 1) Output Voltage Range Reference Input Range Symbol Value Unit PVCC, VCC −0.3 to 6 V VTT −0.3 to 6 V VREF −0.3 to 6 V Maximum Junction Temperature TJ(max) 150 °C Storage Temperature Range TSTG −65 to 150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2 kV ESD Capability, Machine Model (Note 2) ESDMM 200 V TSLD 260 °C Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D THERMAL CHARACTERISTICS Rating Symbol Value RqJA RYJL 82 TBD Unit °C/W Thermal Characteristics, SO8−EP (Note 4) Thermal Resistance, Junction−to−Air (Note 5) Thermal Reference, Junction−to−Lead2 (Note 5) 4. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area. 5. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. OPERATING RANGES (Note 6) Rating Input Voltage Bias Supply Voltage Ambient Temperature Symbol Min Max Unit PVCC 1.0 5.5 V VCC 4.75 5.25 V TA −40 85 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. www.onsemi.com 3 NCP51145 ELECTRICAL CHARACTERISTICS PVCC = 1.8 V / 1.5 V; VCC = 5 V; VREF = 0.9 V / 0.75 V; CTT = 10 mF (Ceramic), TA = +25°C, unless otherwise specified. Parameter Test Conditions Symbol Min Typ Max Unit Iout = 0 A VOS −16 − +16 mV Regload −4 − +4 mV Iout = 0 A IBIAS − 1 2.5 mA VREF < 0.2 V (Shutdown), RLOAD = 180W ISTB − 2 90 mA REGULATOR OUTPUT Output Offset Voltage Iout = ±1.8 A, PVCC = 1.8 V, VREF = 0.9 V Load Regulation Iout = ±1.5 A, PVCC = 1.5 V, VREF = 0.75 V Iout = ±1.2 A, PVCC = 1.35 V, VREF = 0.675 V Iout = ±1.2 A, PVCC = 1.2 V, VREF = 0.6 V INPUT AND STANDBY CURRENTS Bias Supply Current Standby Current CURRENT LIMIT PROTECTION Current Limit PVCC = 1.8 V, VREF = 0.9 V PVCC = 1.5 V, VREF = 0.75 V ILIM 2 − 3.5 1.5 − 3.5 A SHUTDOWN THRESHOLDS Enable VIH 0.45 − − Shutdown VIL − − 0.15 Thermal Shutdown Temperature VCC = 5 V TSD − 125 − °C Thermal Shutdown Hysteresis VCC = 5 V TSH − 35 − °C Shutdown Threshold Voltage V THERMAL SHUTDOWN Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 NCP51145 PACKAGE DIMENSIONS SOIC8−NB EP CASE 751BU ISSUE B D A 8 NOTE 5 F 2X 0.10 C D 5 NOTE 6 A1 E E1 NOTE 4 L2 L 2X 4 TIPS 0.20 C 4 1 NOTE 5 8X B TOP VIEW b 0.25 M C A-B D 2X 0.10 C A-B NOTE 4 D 0.10 C DETAIL A 8X 0.10 C A SEATING PLANE C DETAIL A h B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSION E DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 7. TAB CONTOUR MAY VARY MINIMALLY TO INCLUDE TOOLING FEATURES. DIM A A1 b b1 c c1 D E E1 e F G h L L2 B e C SIDE VIEW END VIEW SEATING PLANE ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ b NOTE 7 b1 F G c c1 SECTION B−B BOTTOM VIEW RECOMMENDED SOLDERING FOOTPRINT 3.30 3.10 8X 1.52 7.00 1 8X 0.60 1.27 PITCH DIMENSION: MILLIMETERS www.onsemi.com 5 MILLIMETERS MIN MAX 1.35 1.75 −−− 0.10 0.31 0.51 0.28 0.48 0.17 0.25 0.17 0.23 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 1.55 3.07 1.55 3.07 0.25 0.50 0.40 1.27 0.25 BSC NCP51145 PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA ISSUE E D 0.10 C 0.10 C 2X 0.10 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 ÇÇ ÇÇ PIN ONE REFERENCE 2X A B DETAIL A E OPTIONAL CONSTRUCTIONS ÉÉ ÉÉ EXPOSED Cu TOP VIEW A DETAIL B DIM A A1 A3 b D D2 E E2 e K L L1 MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION 0.08 C (A3) NOTE 4 A1 C SIDE VIEW SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 8X D2 1 8X 1.30 L PACKAGE OUTLINE 4 E2 K 8 5 8X e/2 e 0.90 b 2.30 1 0.10 C A B 0.05 C 0.50 8X 0.30 NOTE 3 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 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