NCP51510, NCV51510 3 Amp VTT Termination Source / Sink Regulator for DDR, DDR-2, DDR-3, DDR-4 The NCP51510 is a source/sink Double Data Rate (DDR) termination regulator specifically designed for low input voltage and low−noise systems where space is a key consideration. The NCP51510 maintains a fast transient response and only requires a minimum VTT load capacitance of 10 mF for output stability. The NCP51510 supports remote sensing and all power requirements for DDR VTT bus termination. The NCP51510 can also be used in low−power chipsets and graphics processor cores that require dynamically adjustable output voltages. The NCP51510 is available in the thermally−efficient DFN10 Exposed Pad package, and is rated both Green and Pb−Free. www.onsemi.com DFN10 CASE 485C MARKING DIAGRAM 51510 ALYWG G Features • • • • • • • • • • • • • • Generate DDR Memory Termination Voltage (VTT) For DDR, DDR−2, DDR−3 and DDR−4 Source / Sink Currents Supports Loads Up to ±3 A (Typ), Output is Over−Current Protected Integrated MOSFETs with Thermal Shutdown Protection Fast Load−Transient Response PGOOD Output Pin to Monitor Status of VTT Output Regulation SS Input Pin for Suspend Shutdown mode VRI Input Reference for Flexible Voltage Tracking VTTS Input for Remote Sensing (Kelvin Connection) Built−in Soft−Start, Under Voltage Lockout Small, Low−Profile 10−pin, 3 x 3 mm DFN Package NCV51510MWTAG − Wettable Flank Option for Enhanced Optical Inspection NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable* This is a Pb−Free Device 51510 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS VRO 1 10 PVCC VCC 2 9 VTT AGND 3 VRI 4 7 SS PGOOD 5 6 VTTS GND 8 PGND Applications • • • • • • • • (Top View) DDR Memory Termination Desktop PC’s, Notebooks, and Workstations Servers and Networking equipment Telecom/Datacom, GSM Base Station Graphics Processor Core Supplies Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers Supplies Power for Chipset/RAM as Low as 0.5 V Active Source/Sink Bus Termination © Semiconductor Components Industries, LLC, 2015 April, 2015 − Rev. 2 ORDERING INFORMATION Device Package Shipping† DFN10 (Pb−Free) 3000 / Tape & Reel NCP51510MNTAG NCV51510MNTAG* NCV51510MWTAG* †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: NCP51510/D NCP51510, NCV51510 PIN FUNCTION DESCRIPTION Pin Number Pin Name 1 VRO OUTPUT − Buffered Output of VRI Reference Input pin. Pin Function 2 VCC INPUT − Regulator Analog Power Input pin. Connect to the system supply voltage. Bypass VCC to AGND with a 1 mF or greater ceramic capacitor. 3 AGND 4 VRI 5 PGOOD 6 VTTS 7 SS 8 PGND 9 VTT 10 PVCC − THERMAL PAD Analog Ground INPUT − External Reference Input for VTT Output (see Figure 1 for typical application) OUTPUT − VTT “Power Good” pin (open drain output) INPUT − Remote Sense Input for VTT. The VTTS pin provides accurate remote feedback sensing of the VTT output. INPUT − Suspend Shutdown Control Input. CMOS compatible. Logic HIGH = enable, logic LOW = shutdown. Connect to VDDQ for normal operation. Power Ground. Internally connected to Low−side MOSFET OUTPUT − Regulated Power Output pin INPUT − Regulator Power Input pin. Internally connected to High−side MOSFET Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value PVCC to PGND (Note 1) − −0.3 to 4.3 VCC to AGND (Note 1) VCC −0.3 to 4.3 VRI, VRO, SS, PGOOD to AGND (Note 1) − −0.3 to (VCC + 0.3) VTT to PGND (Note 1) − −0.3 to (PVCC + 0.3) VTTS to AGND (Note 1) VTTS −0.3 to (PVCC + 0.3) PGND −0.3 to +0.3 Storage Temperature Tstg −65 to 150 Operating Junction Temperature Range TJ −40 to 125 PGND to AGND Unit V °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V VTT Output Continuous RMS Current 100 sec − ±1.6 1 sec ±2.5 A Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78. DISSIPATION RATINGS Package 10−Pin DFN TA =705C Power Rate Derating Factor Above TA = 705C 1951 mW 24.4 mW / °C www.onsemi.com 2 NCP51510, NCV51510 RECOMMENED OPERATING CONDITIONS Rating Symbol Value VTT, VTTS 0.5 to 1.5 PVCC Input Voltage Range (Power) PVCC 1.1 to 3.6 VCC Input Voltage Range (Analog) VCC 2.7 to 3.6 SS, PGOOD 0 to VCC TA −40 to +125 VTT Output Voltage Range Logic Voltage Range Operating Ambient Temperature Range Unit V °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS PVCC = 1.8 V; VCC = 3.3 V; VRI = VTTS = 1.25 V; SS = VCC; (circuit of Figure 1, −40°C ≤ (TJ = TA) ≤ 125°C; unless otherwise noted. Typical values are at TA = +25°C Conditions Symbol Min PVCC > (VTT + VDROPOUT) VTT VTT Load Regulation −1 A ≤ ITT ≤ +1 A DVLOAD VTT Line−Regulation 1.4 V ≤ PVCC ≤ 3.3 V, IOUT = ±100 mA DVLINE Parameter Typ Max Unit 0.5 1.5 V −4 +4 mV OUTPUT VTT Output Voltage Range Feedback−Voltage Error VRI to VTTS, ITT = ±200 mA TA = −40°C to 125°C VTTS 1 −17 +17 VTT Current Slew Rate COUT = 100 mF, ITT = 0.1 A to 2 A ITT di/dt 3 A/ms VTT Output Power−Supply Rejection Ratio 10 Hz < f < 10 kHz, ITT = 200 mA, COUT = 100 mF PSRR 80 dB High−side (source) (ITT = +100 mA) RDS(on) 140 250 140 250 VTT Output MOSFET RDS(on) Low−side (sink) (ITT = −100 mA) VTT Output−to−VTTS Input Discharge MOSFET RDS(on) mW Internal Feedback Resistance RFB 12 kW SS = 0 V RDIS 8 W No Load IPVCC 0.4 10 VRI > 0.45 V, No Load ICC 0.7 1.3 SS = 0 V IPVCC SD 0.1 10 SS = 0V, VRI = 0 V ICC SD 50 100 350 600 SUPPLY CURRENT Quiescent PVCC Current Quiescent VCC Current Shutdown PVCC Current Shutdown VCC Current SS = 0V, VRI > 0.45 V mA mA REFERENCE VRI Input Voltage Range VRI Input−Bias current VRO Output Voltage VRO Load Regulation VRI 0.5 1.5 V TA = +25°C IRI −1 +1 mA VCC = 3.3 V, IRO = 0 VRO VRI −10 VRI +10 mV IRO = ±5 mA DVRO −20 SS Logic HI (VTT Output Enabled) VIH 2.0 SS Logic LOW (VTT Suspended) VIL SS = VCC or 0 V, TA = +25°C ISS −1 TA = −40°C to +125°C ITT LIMIT 1.8 VRI +20 SUSPEND SHUTDOWN SS − Suspend Shutdown Logic Input Threshold SS − Logic Input Current V 0.8 +1 mA 4.2 A FAULT CONDITION − CURRENT LIMIT Current−Limit Threshold Soft−start Current−limit time TSS www.onsemi.com 3 3 200 ms NCP51510, NCV51510 ELECTRICAL CHARACTERISTICS PVCC = 1.8 V; VCC = 3.3 V; VRI = VTTS = 1.25 V; SS = VCC; (circuit of Figure 1, −40°C ≤ (TJ = TA) ≤ 125°C; unless otherwise noted. Typical values are at TA = +25°C (continued) Parameter Conditions Symbol Min Typ Max Unit Wake−up, rising edge VCC UVLO 2.50 2.70 2.90 V Hysteresis Voltage − 100 Wake−up, rising edge PVCC 0.9 FAULT CONDITION − UNDER−VOLTAGE LOCKOUT VCC UVLO Threshold PVCC UVLO Threshold mV 1.1 V UVLO mV Hysteresis Voltage − 55 VRI, rising edge VRI UVLO 350 Hysteresis Voltage − 50 Thermal Shutdown, rising edge TSD 165 Hysteresis Temperature TSH 15 With respect to feedback threshold, hysteresis = 12 mV − −200 −150 −100 − 100 150 200 ISINK = 4 mA (PGOOD MOSFET = On) − Start−up rising edge, VTTS within ±100 mV of the feedback threshold − 1 2 3.5 ms VTTS forced 25 mV beyond PGOOD trip threshold TPGOOD 5 10 35 ms VTTS = VRI (PGOOD Hi−impedance), PGOOD = VCC + 0.3 V, TA = +25°C IPGOOD 1 mA VRI UVLO Voltage 450 FAULT CONDITION − THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Shutdown Hysteresis °C FAULT CONDITION − POWER GOOD PGOOD Lower trip threshold PGOOD Upper trip threshold PGOOD Output Low Voltage PGOOD start−up delay PGOOD Propagation Delay PGOOD Leakage Current mV 300 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 NCP51510, NCV51510 General* The NCP51510 is a source/sink tracking termination regulator specifically designed for low input voltage and low external component count systems where space is a key application parameter. The NCP51510 integrates a high−performance, low−dropout (LDO) linear regulator that is capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with minimum effect of trace resistance, a remote sensing input (VTTS) should be connected to the positive terminal of the output capacitors as a separate trace from the high current path of the VTT output. surge currents at startup, with full current available after the 200 ms Soft−Start circuitry has timed out. When the SS input is driven low, the VTT output is discharged to PGND through an internal 8 W MOSFET. The VRO output remains on when the SS input is driven low. The NCP51510 provides an open−drain PGOOD “Power Good” output that goes high when the VTTS Sense input is within ±150 mV of the VRI Reference Input. The PGOOD output de−asserts within 10 ms after the VTTS Sense input exceeds the size of the PGOOD window. During initial VTT startup, PGOOD asserts high 2 ms after the VTTS Sense input enters PGOOD window. Because the PGOOD output is open−drain, an external pull−up resistor is required (100 kW*) between PGOOD and a stable active supply voltage rail. Generation of Internal Voltage Reference Thermal Shutdown with Hysteresis The VTT output voltage is regulated to (and tracks with) the voltage on the VRI Reference input. When the VRI input is configured for standard DDR termination applications, the VRI Reference input can be set by an external equivalent ratio voltage divider connected to the memory supply bus (VDDQ). The NCP51510 supports VTT voltages from 0.5 V to 1.5 V. If the NCP51510 is to operate in elevated temperatures for long durations, care should be taken to ensure that the maximum operating junction temperature is not exceeded. To guarantee safe operation, the NCP51510 provides on−chip thermal shutdown protection. When the chip junction temperature exceeds 165°C*, the part will shutdown. When the junction temperature falls back, to 150°C*, the device resumes normal operation. If the junction temperature exceeds the thermal shutdown threshold, the VTT output is shut off, discharged by the 8 W internal discharge MOSFET. Generation of Internal Voltage Reference (cont) When the VRO output is configured for DDR termination applications, it provides a separate VTT output reference voltage for the memory application. The VRO Reference Output pin is a buffered version of the VRI Reference Input, and is capable of sourcing and sinking a load of ±5 mA. The VRO output becomes active when the VRI input > 0.45 V and the VCC power rail is above the UVLO threshold. The VRO Reference Output is independent of the SS pin (Suspend Shutdown) state. Output Capacitor Output stability is guaranteed for VTT output capacitance COUT from 10 mF to 220 mF. The ESR of COUT between 2 mW and 50 mW is required to maintain stability. Use the formula below to calculate the application’s transient response: DI TT(pp) Fault Detection and Shutdown Function When the SS “Suspend Shutdown” input pin is driven high, the NCP51510 regulator begins normal operation, with the Soft Start circuit gradually increasing output current during the first 200 ms in order to reduce the input ESR + DV TT(pp) Where: DITT(pp) is the maximum peak−to−peak load current delta and DVTT(pp) is the allowable peak−to−peak voltage tolerance. *Typical values are used with the application description text. Please refer to the Electrical Specifications Table for a more detailed list of MIN, MAX and TYPICAL values. www.onsemi.com 5 NCP51510, NCV51510 Figure 1. Standard Application Schematic for NCP51510 www.onsemi.com 6 NCP51510, NCV51510 PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE C D PIN 1 REFERENCE EDGE OF PACKAGE A B L1 ÇÇÇ ÇÇÇ ÇÇÇ E DETAIL A Bottom View (Optional) 0.15 C 2X EXPOSED Cu TOP VIEW MOLD CMPD 0.15 C 2X (A3) DETAIL B 0.10 C A1 ÉÉÉ ÉÉÉ A 10X SIDE VIEW A1 D2 1 DIM A A1 A3 b D D2 E E2 e K L L1 C DETAIL A e L A3 DETAIL B Side View (Optional) SEATING PLANE 0.08 C 10X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. 7. FOR DEVICE OPN CONTAINING W OPTION, DETAIL B ALTERNATE CONSTRUCTION IS NOT APPLICABLE. SOLDERING FOOTPRINT* 5 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.40 2.60 3.00 BSC 1.70 1.90 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 2.6016 E2 10X K 10 10X 0.10 C A B 0.05 C 6 1.8508 2.1746 b 3.3048 BOTTOM VIEW NOTE 3 10X 0.5651 10X 0.5000 PITCH 0.3008 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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