NCL30030 D

NCL30030
Combination Power Factor
Correction and
Quasi-Resonant Flyback
Controllers for LED Lighting
Common General Features
• Wide VCC Range from 9 V to 30 V with Built−in Overvoltage
Protection
• High−Voltage Startup Circuit
• Integrated High−Voltage Brown−Out Detector
• Fault Input for Severe Fault Conditions, NTC Compatible (Latch and
Auto−Recovery Options)
• Critical Conduction Mode with a Multiplier
• Accurate Overvoltage Protection
• Optional Bi−Level Line−Dependent Output Voltage
•
•
•
•
1
MULT
PControl
PONOFF
QCT
Fault
QFB
16
PFB
GND
PCS/PZCD
PDRV
QDRV
QCS
VCC
QZCD
NCL30030 = Specific Device Code
x
= A or B
y
= 1, 2 or 3
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
Auto−Recovery options)
Adjustable Overpower Protection
Winding and Output Diode Short−Circuit Protection
4 ms Soft−Start Timer
These are Pb−Free Devices
Typical Applications
•
•
•
•
•
•
QR Flyback Controller Features
• Valley Switching Operation with Valley−Lockout for
Noise−Free Operation
• Frequency Foldback with Minimum Frequency Clamp
for Highest Performance in Standby Mode
March, 2015 − Rev. 1
BO/HV
• Minimum Frequency Clamp Eliminates Audible Noise
• Timer−Based Overload Protection (Latched or
(2:1 / 1.77:1 Versions)
Fast Line / Load Transient Compensation
Boost Diode Short−Circuit Protection
Feed−Forward for Improved Operation across Line and
Load
Adjustable PFC Disable Threshold Based on Output
Power
© Semiconductor Components Industries, LLC, 2015
MARKING DIAGRAM
See detailed ordering and shipping information on page 31 of
this data sheet.
PFC Controller Features
•
SOIC−16 NB MISSING PIN 2
CASE 751DT
ORDERING INFORMATION
• 0.5 A / 0.8 A Source / Sink Gate Drivers
• Internal Temperature Shutdown
•
•
•
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NCL30030xy
AWLYWWG
This combination IC integrates power factor correction (PFC) and
quasi−resonant flyback functionality necessary to implement a
compact and highly efficient LED driver for high performance LED
lighting applications.
The PFC stage utilizes a proprietary multiplier architecture to
achieve low harmonic distortion and near−unity power factor while
operating in a Critical Conduction Mode (CrM). The circuit
incorporates all the features necessary for building a robust and
compact PFC stage while minimizing the number of external
components.
The quasi−resonant current−mode flyback stage features a
proprietary valley−lockout circuitry, ensuring stable valley switching.
This system works down to the 4th valley and toggles to a frequency
foldback mode with a minimum frequency clamp beyond the 4th
valley to eliminate audible noise. Skip mode operation allows
excellent efficiency in light load conditions while consuming very low
standby power consumption.
1
High Power LED Drivers
Commercial LED ballasts
LED Signage Power Supplies
Adapters
Open Frame Power Supplies
LED Electronic Control Gear
Publication Order Number:
NCL30030/D
PCS/PZCD
PDRV
PFB
BO/HV
GND
MULT PCS/PZCD
PDRV
PControl
QDRV
PONOFF
QCT
QCS
VCC
Fault
QFB
QZCD
NCL30030
U1
QCS
VCC
PCS/PZCD
PDRV
VZCD
VCC
VZCD
(Aux)
QCS
NCL30030
Figure 1. NCL30030 Typical Application Circuit
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2
NCL30030
PUVP
16
Central
KPOVP(xL)
OVP
Detection
Brownout
Low/High Line
POVP
1
Detection, and
Logic
Reset
Logic
VCCOVP
VCC_OK
VCC(reset)
VCC_OK
IPControl(boost)
I start1/2
VCC
VCC
10
Management
CCC
V DD
KLOW(HYS)
KLOW
BO/HV
Startups
VCC_OK
QR_EN
PFC
DPOVP(xL)
High Voltage
Brownout
VBO_BUF
Latch
Auto−recovery
VCC(reset)
VPFB(disable)
−
PFB
Low/High Line
VPFB(HYS)
+
QR_EN
Soft−start
VQILIM1
IEA
VQFB
+
VPREF(xL)
−
QZCD
In Regulation
Soft−start
I PONOFF
VPCONTROL(MAX)
PControl
VCONTROL
4
PUVP
VPCONTROL(MIN)
+
VPONHYS
POVP
PUVP
PSKIP
PILIM1
PILIM2
Disable PFC
PSKIP
QDRV
Q
Dominant
Reset
Latch
Q
S
R
Q
Dominant
Reset
Latch
Q
S
VPCONTROL
VPOFF
QRDRV
R
ton1x
In Regulation
−
Low/High Line
+
DVPSKIP
−
Low/High Line
VBO_BUF
PONOFF
5
tPdisable
Disable PFC
PFCDRV
12
Soft−start
t Q(toutx)
VQZCD
QZCD
Valley
Multiplier
ZCD
9
Detect
VQZCD(hys)
t delay(QSKIP)
3
QSkip
VQZCD(th)
+
MULT
−
Minimum
VQFB
Setpoint
QRDRV
Oscillator
PILIM1
CT
VCO
Frequency
LEB1
I QCT
+
VPILIM1
VCO
QRDRV
tPFC(offx)
Timer
PILIM2
PFCDRV
ZCD
IQFB
QSkip
PZCD
I PCS/PZCD
Detect
+
−
t onQR(MAX)
Valley
Valley
QSkip
Select
VCO
Logic
VPZCD
PCS/PZCD
LEB2
PDRV
PFCDRV
TSD
QOVLD
nQILIM2
S
S
S
OVP
OTP
S
S
S
VCCOVP
+
−
OVP
Brownout
VCC(reset)
GND
Latch
QILIM1
Fault
LEB1
Auto−recovery
Logic
t QOVLD
R
R
VQZCD
+
VQILIM1
VFault(OVP)
Temperature
TSD
OTP
nQILIM2
LEB2
Counter
VFault(OTP_in)
−
Figure 2. NCL30030 Functional Block Diagram
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3
IQCS
QCS
QILIM2
+
7
/KQFB
15
QOVLD
IOTP
VQFB
VQZCD
+
−
Fault
QFB
PILIM2
VPILIM2
13
RQFB
8
+
QRDRV
14
QCT
6
−
VQILIM2
11
NCL30030
Table 1. PIN FUNCTION DESCRIPTION
Pin Out
Name
1
BO/HV
2
Function
Performs input brown−out detection and line voltage range detection.
Removed for creepage distance.
3
MULT
This is the output of the multiplication of the BO and Control signals. A capacitor should be put on this
pin for filtering. Suggested values from 1 nF − 20 nF.
4
PControl
Output of the PFC transconductance error amplifier. A compensation network is connected between
this pin and ground to set the loop bandwidth.
5
PONOFF
A resistor between this pin and ground sets the PFC turn off threshold. The voltage on this pin is
compared to an internal voltage signal proportional to the output power. The PFC disabled threshold
is determined by the resistor on this pin and the internal pull–up current source, IPONOFF.
6
QCT
An external capacitor sets the frequency in VCO mode for the QR flyback controller.
7
Fault
The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds.
A precise pull up current source allows direct interface with an NTC thermistor. Fault detection triggers a latch or auto−recovery depending on device option.
8
QFB
Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
9
QZCD
10
VCC
Supply input.
11
QCS
Input to the cycle−by−cycle current limit comparator for the QR Flyback section.
12
QDRV
QR flyback controller switch driver.
13
PDRV
PFC controller switch driver.
14
PCS/PZCD
15
GND
Ground reference.
16
PFB
PFC feedback input from external resistor divider used to sense the PFC bulk voltage. This pin voltage is compared to an internal reference. There are three different reference voltage combinations
depending on ac mains voltage and version of the part.
Input to the demagnetization detection comparator for the QR Flyback controller. Also used to set the
overpower compensation.
Input to the cycle−by−cycle current limit comparator for the PFC section. Also used to perform the
demagnetization detection for the PFC controller.
Table 2. NCL30030 DEVICE OPTIONS
Flyback Overload Protection
Fault OTP
PFC Reference Voltage
(High Line / Low Line)
NCL30030B1DR2G
Auto−Recovery
Auto−Recovery
3.55 / 2 V
NCL30030B2DR2G
Auto−Recovery
Auto−Recovery
4/2V
NCL30030B3DR2G
Auto−Recovery
Auto−Recovery
4/4V
NCL30030A1DR2G*
Latch
Latch
3.55 / 2 V
NCL30030A2DR2G*
Latch
Latch
4/2V
NCL30030A3DR2G*
Latch
Latch
4/4V
Device
*Please contact local sales representative for availability
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4
NCL30030
Table 3. MAXIMUM RATINGS (Notes 1 through 6)
Rating
Pin
Symbol
Value
Unit
High Voltage Brownout Detector Input Voltage
1
VBO/HV
−0.3 to 700
V
High Voltage Brownout Detector Input Current
1
IBO/HV
20
mA
PFC Low Voltage Feedback Input Voltage
16
VPFB
−0.3 to 9
V
PFC Low Voltage Feedback Input Current
16
IPFB
0.5
mA
PFC Zero Current Detection and Current Sense Input Voltage (Note 1)
14
VPCS/PZCD
−0.3 to VPCS/PZCD(MAX)
V
PFC Zero Current Detection and Current Sense Input Current
14
IPCS/PZCD
−2/+5
mA
PFC Control Input Voltage
4
VPControl
−0.3 to 5
V
PFC Control Input Current
4
IPControl
10
mA
Supply Input Voltage
10
VCC(MAX)
−0.3 to 30
V
Supply Input Current
10
ICC(MAX)
30
mA
Supply Input Voltage Slew Rate
10
dVCC/dt
1
V/ms
Fault Input Voltage
7
VFault
−0.3 to (VCC + 1.25)
V
Fault Input Current
7
IFault
10
mA
PFC Multiplier pin
3
VMULT
−0.3 to 10
V
PFC Multiplier pin
3
IMULT
3
mA
QR Flyback Zero Current Detection Input Voltage
9
VQZCD
−0.9 to (VCC + 1.25)
V
QR Flyback Zero Current Detection Input Current
9
IQZCD
−2/+5
mA
QR Feedback Input Voltage
6
VQCT
−0.3 to 10
V
QR Feedback Input Current
6
IQCT
10
mA
QR Flyback Current Sense Input Voltage
11
VQCS
−0.3 to 10
V
QR Flyback Current Sense Input Current
11
IQCS
10
mA
QR Flyback Feedback Input Voltage
8
VQFB
−0.3 to 10
V
QR Flyback Feedback Input Current
8
IQFB
10
mA
PFC Driver Maximum Voltage (Note 2)
13
VPDRV
−0.3 to VPDRV(high2)
V
PFC Driver Maximum Current
13
IPDRV(SRC)
IPDRV(SNK)
500
800
mA
Flyback Driver Maximum Voltage (Note 2)
12
VQDRV
−0.3 to VQDRV(high2)
V
Flyback Driver Maximum Current
12
IQDRV(SRC)
IQDRV(SNK)
500
800
mA
PFC ON/OFF Threshold Adjust Input Voltage
5
VPONOFF
−0.3 to 10
V
PFC ON/OFF Threshold Adjust Input Current
5
IPONOFF
10
mA
Operating Junction Temperature
N/A
TJ
−40 to 125
°C
Storage Temperature Range
N/A
TSTG
–60 to 150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
1. VPCS/PZCD(MAX) is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks
a current equal to (VPCS/PZCD − 5 V)/(2 kW). A VPSC/PZCD of 7 V generates a sink current of approximately 1 mA.
2. Maximum driver voltage is limited by the driver clamp voltage, VXDRV(high2), when VCC exceeds the driver clamp voltage. Otherwise,
the maximum driver voltage is VCC.
3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond
those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied.
Functional operation should be restricted to the Recommended Operating Conditions.
4. This device contains Latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +100/−100 mA.
5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
6. Pin 1 is rated to the maximum voltage of the part, or 700 V.
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5
NCL30030
Table 3. MAXIMUM RATINGS (Notes 1 through 6)
Rating
Power Dissipation (TA = 75°C, 1 Oz Cu, 0.155 Sq Inch Printed Circuit Copper
Clad) Plastic Package SOIC−16NB
Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit Copper Clad)
Plastic Package SOIC−16NB
ESD Capability (Note 6)
Human Body Model per JEDEC Standard JESD22−A114F.
Machine Model per JEDEC Standard JESD22−A115−A.
Charge Device Model per JEDEC Standard JESD22−C101E.
Symbol
Value
Unit
PD
550
mW
RqJA
°C/W
145
V
HBM
MM
CDM
3000
200
750
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
1. VPCS/PZCD(MAX) is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks
a current equal to (VPCS/PZCD − 5 V)/(2 kW). A VPSC/PZCD of 7 V generates a sink current of approximately 1 mA.
2. Maximum driver voltage is limited by the driver clamp voltage, VXDRV(high2), when VCC exceeds the driver clamp voltage. Otherwise,
the maximum driver voltage is VCC.
3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond
those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied.
Functional operation should be restricted to the Recommended Operating Conditions.
4. This device contains Latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +100/−100 mA.
5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
6. Pin 1 is rated to the maximum voltage of the part, or 700 V.
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NCL30030
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V,
VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF,
CQDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Pin
Symbol
Min
Typ
Max
Unit
VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
VCC(inhibit)
16
8.2
7.7
4.5
0.3
17
8.8
–
5.5
0.7
18
9.4
–
7.5
0.95
10
tUVLO(blank)
3
–
25
ms
Istart1A
0.20
0.50
0.65
mA
Istart2A
2.5
−
5
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Operating Hysteresis
Internal Latch / Logic Reset Level
Transition from Istart1 to Istart2
10
VCC increasing
VCC decreasing
VCC(on) − VCC(off)
VCC decreasing
VCC increasing, IHV/HV = 650 mA
Blanking Duration After VCC(off)
Startup Current in Inhibit Mode
V
VCC = 0 V
10
VCC = VCC(on) – 0.5 V,
VBO/HV = 100 V
10
Istart2A = 1 mA, VCC = VCC(on) – 0.5 V
1
VBO/HV(MIN)
–
–
40
V
VCC Overvoltage Protection Threshold
10
VCC(OVP)
27
28
29
V
VCC Overvoltage Protection Delay
10
tdelay(VCC_OVP)
20.0
30.0
40.0
Supply Current
Before Startup, Fault or Latch
Flyback in Skip, PFC Disabled
Flyback in Skip, PFC in Skip
Flyback Enabled, QDRV Low, PFC
Disabled
Flyback Enabled, QDRV Low, PFC in
Skip
PFC and Flyback switching at 70 kHz
PFC and Flyback switching at 70 kHz
10
Startup Current
Operating Mode
Minimum Startup Voltage
mA
ms
mA
VCC = VCC(on) – 0.5 V
VQFB = 0.35 V
VQFB = 0.35 V, VPControl < VPSKIP
VQZCD = 1 V
ICC2
ICC3a
ICC3b
ICC4
−
−
−
−
0.15
0.3
0.5
0.85
0.28
0.43
1.03
1.38
VQZCD = 1 V, VPControl < VPSKIP
ICC5
−
1.1
1.83
CQDRV = CPDRV = open
ICC6
ICC7
−
−
1.5
2.8
4.03
5.23
BROWN−OUT DETECTION
System Startup Threshold
VBO/HV increasing
1
VBO(start)
102
111
120
V
System Shutdown Threshold
VBO/HV decreasing
1
VBO(stop)
86
101
116
V
Brown−out Hysteresis
VBO/HV increasing
1
VBO(hys)
4
−
16
V
Brown−out Detection Blanking Time
VBO/HV decreasing, duration below
VBO(stop) for a Brown−out fault
1
tBO(stop)
43
54
65
ms
Brown−out Drive Disable Threshold
VBO/HV decreasing, threshold to
disable drive
1
VBO(DRV_disable)
20
30
40
V
Line Level Detection Threshold
VBO/HV increasing
1
Vlineselect
216
240
264
V
High to Low Line Mode Selector Timer
VBO/HV decreasing
1
thigh to low line
43
54
65
ms
Low to High Line Mode Selector Timer
VBO/HV increasing
1
tlow to high line
200
350
450
ms
VBO/HV = 500 V
1
IBO/HV(off)
–
–
42
mA
13
tPFC(off1)
tPFC(off2)
100
700
200
1000
300
1300
ms
Fixed Cycle by Cycle Current Sense
Threshold
14
VPILIM1
1.35
1.5
1.65
V
Cycle by Cycle Leading Edge Blanking
Duration
14
tPCS(LEB1)
250
325
400
ns
Cycle by Cycle Current Sense
Propagation Delay
14
tPCS(delay1)
−
100
400
ns
Abnormal Overcurrent Fault Threshold
14
VPILIM2
1.8
2
2.2
V
Abnormal Overcurrent Fault Leading
Edge Blanking Duration
14
tPCS(LEB2)
100
175
250
ns
Abnormal Overcurrent Fault
Propagation Delay
14
tPCS(delay2)
−
100
200
ns
Brownout Pin Off State Leakage
Current
PFC MAXIMUM OFF TIME TIMER
Maximum Off Time
VPCS/PZCD > VPILIM2
PFC CURRENT SENSE
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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7
NCL30030
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V,
VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF,
CQDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Pin
Symbol
Min
Typ
Max
Unit
Multipler Cycle by Cycle Current Sense
Offset
BO = 180, PFB = 1.5 V
14
VPILIM_MULT
−12
−
10
mV
Multiplier Cycle by Cycle Current Sense
Propagation Delay
BO = 180 V, PFB = 1.5 V
14
tPCS(delay_mult)
10
100
200
ns
VPCS/PZCD = 2.5 V
14
IPCS/PZCD
0.7
1.0
1.3
mA
VBO/HV > VBO(lineselect)
16
VPREF(HL)
3.47
3.92
1.95
3.92
3.55
4.00
2
4
3.62
4.08
2.05
4.08
V
PFC CURRENT SENSE
Pull−up Current Source
PFC REGULATION BLOCK
PFC Reference Voltage
See Table 2 for Options
VBO/HV < VBO(lineselect)
Error Amplifier Current
Source
Sink
Source
Sink
VPREF(LL)
mA
PFC Enabled
VPFB = 0.96 x VPREF(HL)
VPFB = 1.04 x VPREF(HL)
VPFB = 0.96 x VPREF(LL)
VPFB = 1.04 x VPREF(LL)
4
IEA(SRCHL)
IEA(SNKHL)
IEA(SRCLL)
IEA(SNKLL)
16
16
10
10
32
32
20
20
48
48
30
30
Open Loop Error Amplifier
Transconductance
VPFB = VPREF(LL) +/− 4 %
VPFB = VPREF(HL) +/− 4 %
4
gm
gm_HL
100
100
200
200
300
300
mS
Maximum Control Voltage
VPFB * KLOW(PFCxL),
CPControl = 10 nF
4
VPControl(MAX)
–
4.5
–
V
VPFB * KPOVP(xL), CPControl = 10 nF
4
VPControl(MIN)
–
0.6
–
V
V
Minimum Control Voltage (Lower
clamp)
VPControl(MAX) − VPControl(MIN)
4
DVPControl
3.7
3.9
4.1
Ratio between the Vout Low Detect
Threshold and the Regulation Level
VPFB decreasing, VBOOST / VPREF(HL)
VPFB decreasing, VBOOST / VPREF(LL)
16
KLOW(PFCHL)
KLOW(PFCLL)
0.940
0.940
0.945
0.945
0.950
0.950
Ratio between the Vout Low Exit
Threshold and the Regulation Level
VPFB increasing
16
KLOW(HYSHL)
KLOW(HYSLL)
0.950
0.950
0.960
0.960
0.965
0.965
4
IPControl(boost)
190
240
290
mA
VPControl increasing
4
IIn_Regulation
−6.5
–
0
mA
IPControl = 5 mA
4
RPControl
4
25
50
W
VPControl decreasing, measured from
VPControl(MIN)
4
DVPSKIP
5
25
50
mV
VPControl increasing
4
VPSKIP(HYS)
25
50
75
mV
Apply 1 V step from VPControl(MIN)
4
tdelay(PSKIP)
–
50
60
ms
VPFB increasing
KPOVP(LL) = VPFB/VPREF(LL)
KPOVP(HL) = VPFB/VPREF(HL)
16
KPOVP(LL)
KPOVP(HL)
1.06
1.05
1.08
1.06
1.10
1.08
VPSOVP(LL) = soft overvoltage level
DPOVP(LL) = KPOVP*VPREF(LL) −
VPSOVP(LL)
DPOVP(HL) = KPOVP*VPREF(HL) −
VPSOVP(HL)
16
DPOVP(LL)
20
–
55
DPOVP(HL)
20
–
55
PFC Feedback Pin Disable Threshold
VPFB decreasing
16
VPFB(disable)
0.225
0.30
0.35
V
PFC Feedback Pin Enable Threshold
VPFB increasing
16
VPFB(enable)
0.275
0.35
0.40
V
PFC Feedback Pin Hysteresis
VPFB increasing
16
VPFB(HYS)
25
50
−
mV
16
tdelay(PFB)
20
30
40
ms
ton1a
ton1b
12.5
4.25
15
5.00
17.5
5.75
EA Output Control Voltage Range
Source Current During Vout Low Detect
PFC In Regulation Threshold
Resistance of Internal Pull Down Switch
PFC SKIP MODE
Delta Between Skip Level and Lower
Clamp PControl Voltages
PFC Skip Hysteresis
Delay Exiting Skip Mode
PFC FAULT PROTECTION
Ratio between the Hard Overvoltage
Protection Threshold and Regulation
Level
Soft Overvoltage Protection Threshold
PFC Feedback Disable Delay
mV
PFC ON TIME CONTROL
PFC Maximum On
VPControl = VPControl(MAX)
VBO/HV = 163 V
VBO/HV = 325 V
ms
13
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
8
NCL30030
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V,
VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF,
CQDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Pin
Symbol
Min
Typ
Max
Unit
Voltage to Current Conversion Ratio
VQFB = 3 V, Low Line
VQFB = 3 V, High Line
5
Iratio1(QFB/PON)
Iratio2(QFB/PON)
13
13
15
15
17
17
mA
PFC Disable Threshold
VPONOFF decreasing
5
VPOFF
1.9
2.0
2.1
V
PFC Enable Hysteresis
VQFB = increasing
5
VPONHYS
0.135
0.160
0.185
V
tdemag/T = 70%,
RPONOFF = 191 kW, CPONOFF = 1 nF
VQFB = 1.8 V (decreasing)
VQFB = 3 V (decreasing)
5
Disable Timer
PFC DISABLE
PONOFF Operating Mode Voltage
V
VPONOFF1
VPONOFF2
1.08
1.8
1.20
2.0
1.32
2.2
5
tPdisable
450
500
550
ms
5
tPenable(filter)
50
100
150
ms
PONOFF Increasing
5
tPenable
200
–
500
ms
Multiplier maximum BO=180V
PControl = open, BO = 180 V
3
MULT_max_180
0.85
1
1.15
V
Multiplier maximum BO = 360V
PControl = open, BO = 360 V
3
MULT_max_360
0.425
0.5
0.575
V
Multiplier output
PControl = 2.5 V, BO = 180 V
3
VmultLL
0.425
0.5
0.575
V
Multiplier output
PControl = 2.5 V, BO = 360 V
3
VmultHL
0.2125
0.25
0.2875
V
Multiplier linearity with respect to BO at
low line.
(VMULT180/180V)/(VMULT120/120V)
PControl = 2.5 V, BO = 180 V and
BO = 120 V
3
Mult_linearityLL
0.98
1
1.02
Multiplier linearity with respect to BO at
high line.
(VMULT360/360V)/VMULT300/300V)
PControl = 2.5 V, BO = 360 V and BO
= 300 V
3
Mult_linearityHL
0.99
1
1.01
Rise Time (10−90%)
VPDRV from 10% to 90% of VCC
13
tPDRV(rise)
–
40
80
ns
Fall Time (90−10%)
90% to 10% of VPDRV
13
tPDRV(fall)
–
20
40
ns
RPDRV(SRC)
RPDRV(SNK)
−
−
13
7
−
−
IPDRV(SRC)
IPDRV(SNK)
–
–
500
800
–
–
PFC Disable Timer
PFC Enable Filter Delay
PFC Enable Timer
PFC MULTIPLIER
PFC GATE DRIVE
Driver Resistance
Source
Sink
Current Capability
Source
Sink
W
13
13
VPDRV = 2 V
VPDRV = 10 V
mA
High State Voltage
VCC = VCC(off) + 0.2 V, RPDRV = 10 kW
VCC = 26 V, RPDRV = 10 kW
13
VPDRV(high1)
VPDRV(high2)
8
10
–
12
–
14
V
Low State Voltage
VFault = 4 V
13
VPDRV(low)
–
–
0.25
V
Zero Current Detection Threshold
VPCS/PZCD rising
VPCS/PZCD falling
14
VPZCD(rising)
VPZCD(falling)
675
200
750
250
825
300
mV
Hysteresis on Voltage Threshold
VPZCD(rising) – VPZCD(falling)
14
VPZCD(HYS)
375
500
625
mV
Propagation Delay
Measure from VPCS/PZCD =
VPZCD(falling) to PDRV rising
14
tPZCD
50
100
170
ns
VPCS/PZCD(MAX)
VPCS/PZCD(MIN)
6.5
−0.9
7
−0.7
7.5
0
PFC ZERO CURRENT DETECTION
Input Voltage Excursion
Upper Clamp
Negative Clamp
Minimum detectable ZCD Pulse Width
ZCD blanking time
14
IPCS/PZCD = 1 mA
IPCS/PZCD = −2 mA
V
Between VPZCD(rising) and
VPZCD(falling) to PDRV
14
tSYNC
–
70
200
ns
Measured DRV off to DRV on
14
TPzcd_blank
450
700
1000
ns
VQDRV from 10 to 90%
12
tQDRV(rise)
–
40
80
ns
QR FLYBACK GATE DRIVE
Rise Time (10−90%)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
9
NCL30030
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V,
VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF,
CQDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Pin
Symbol
Min
Typ
Max
Unit
90 to 10% of VQDRV
12
tQDRV(fall)
–
20
40
ns
RQDRV(SRC)
RQDRV(SNK)
−
−
13
7
−
−
IQDRV(SRC)
IQDRV(SNK)
–
–
500
800
–
–
QR FLYBACK GATE DRIVE
Fall Time (90−10%)
Driver Resistance
Source
Sink
W
12
Current Capability
Source
Sink
12
VQDRV = 2 V
VQDRV = 10 V
mA
High State Voltage
VCC = VCC(off) + 0.2 V, RQDRV = 10 kW
VCC = 26 V, RQDRV = 10 kW
12
VQDRV(high1)
VQDRV(high2)
8
10
–
12
–
14
V
Low State Voltage
VFault = 4 V
12
VQDRV(low)
–
–
0.25
V
Internal Pull−Up Current Source
8
IQFB
46.75
50
53.25
mA
Feedback Input Open Voltage
8
VQFB(open)
4.5
5.0
5.5
V
VQFB to Internal Current Setpoint
Division Ratio
8
KQFB
3.8
4.0
4.2
8
RQFB
340
400
460
VH2D
VH3D
VH4D
VHVCOD
VHVCOI
VH4I
VH3I
VH2I
1.316
1.128
0.846
0.752
1.316
1.504
1.692
1.880
1.400
1.200
0.900
0.800
1.400
1.600
1.800
2.000
1.484
1.272
0.954
0.848
1.484
1.696
1.908
2.120
QR FLYBACK FEEDBACK
QFB Pull Up Resistor
VQFB = 0.4 V
Valley Thresholds
Transition from 1st to 2nd valley
Transition from 2nd to 3rd valley
Transition from 3rd to 4th valley
Transition from 4th valley to VCO
Transition from VCO to 4th valley
Transition from 4th to 3rd valley
Transition from 3rd to 2nd valley
Transition from 2nd to 1st valley
VQFB decreasing
VQFB decreasing
VQFB decreasing
VQFB decreasing
VQFB increasing
VQFB increasing
VQFB increasing
VQFB increasing
Skip Threshold
VQFB decreasing
8
VQSKIP
0.35
0.40
0.45
V
Skip Hysteresis
VQFB increasing
8
VQSKIP(HYS)
25
50
75
mV
Apply 1 V step from VQSKIP
8
tdelay(QSKIP)
–
–
10
ms
12
tonQR(MAX)
26
32
38
ms
VQFB = 0.5 V
6
VQCT(peak)
3.815
4.000
4.185
V
VQCT = 0 V
6
IQCT
18
20
22
mA
6
VQCT(min)
–
–
90
mV
6
fVCO(MIN)
23.5
27
30.5
kHz
VQZCD decreasing
9
VQZCD(th)
35
55
90
mV
VQZCD increasing
9
VQZCD(HYS)
15
35
55
mV
VQZCD step from 4.0 V to −0.3 V
9
tDEM
–
150
250
ns
VQZCD(MAX)
VQZCD(MIN)
12.4
−0.9
12.7
−0.7
13.5
0
9
tZCD(blank)
2
3
4
ms
During soft−start
After soft−start
12
tQ(tout1)
tQ(tout2)
80
5.1
100
6
120
6.9
ms
VQCS increasing
VQCS increasing, VQZCD = 1 V
11
VQILIM1a
VQILIM1b
0.760
0.760
0.800
0.800
0.840
0.840
V
Delay Exiting Skip Mode to 1st QDRV
Pulse
8
kW
Maximum On Time
V
QR FLYBACK TIMING CAPACITOR
QCT Operating Voltage Range
On Time Control Source Current
Minimum voltage on QCT Input
Minimum Operating Frequency in VCO
Mode
VQCT = VQCT(peak) + 100 mV
QR FLYBACK DEMAGNETIZATION INPUT
QZCD threshold voltage
QZCD hysteresis
Demagnetization Propagation Delay
Input Voltage Excursion
Upper Clamp
Negative Clamp
9
IQZCD = 5.0 mA
IQZCD = −2.0 mA
Blanking Delay After Turn−Off
Timeout After Last Demagnetization
Detection
V
QR FLYBACK CURRENT SENSE
Current Sense Voltage Threshold
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
10
NCL30030
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V,
VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF,
CQDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Pin
Symbol
Min
Typ
Max
Unit
Minimum on time minus tdelay(ILIM_QR)
11
tQCS(LEB1)
220
275
350
ns
11
tQCS(delay1)
–
125
175
ns
QR FLYBACK CURRENT SENSE
Cycle by Cycle Leading Edge Blanking
Duration
Cycle by Cycle Current Sense
Propagation Delay
Immediate Fault Protection Threshold
11
VQILIM2
1.125
1.200
1.275
V
Abnormal Overcurrent Fault Leading
Edge Blanking Duration
VQCS increasing, VQFB = 4 V
11
tQCS(LEB2)
90
120
150
ns
Abnormal Overcurrent Fault
Propagation Delay
11
tQCS(delay2)
–
125
175
ns
Number of Consecutive Abnormal
Overcurrent Detections to Enter Fault
Mode
11
nQILIM2
–
4
–
VQFB = 0.4 V, VQCS increasing
11
Ipeak(VCO)
11
12.5
14
%
VQCS Increasing, VQFB = 4 V
11
VOPP(MAX)
28
31.25
33
%
Minimum Peak Current Level in VCO
Mode
Set point decrease for VQZCD =
−250 mV
Overpower Protection Delay
11
tQOPP(delay)
–
125
175
ns
VQCS = 1.5 V
11
IQCS
0.7
1.0
1.3
mA
Measured from 1st QDRV pulse to
VQCS = VQILIM1
11
tSSTART
2.8
4.0
5.0
ms
VQCS = VQILIM1
11
tQOVLD
60
80
100
ms
VFault increasing
7
VFault(OVP)
2.79
3.00
3.21
V
tdelay(Fault_OVP)
tdelay(Fault_OTP)
22.5
22.5
30.0
30.0
37.5
37.5
Pull−up Current Source
QR FLYBACK FAULT PROTECTION
Soft−Start Period
Flyback Overload Fault Timer
COMMON FAULT PROTECTION
Overvoltage Protection (OVP)
Threshold
Delay Before Fault Confirmation
Used for OVP Detection
Used for OTP Detection
ms
7
VFault increasing
VFault decreasing
Overtemperature Protection (OTP)
Threshold (Note 7)
VFault decreasing
7
VFault(OTP_in)
0.38
0.40
0.42
V
Overtemperature Protection (OTP)
Exiting Threshold (Note 7)
VFault increasing, B version
7
VFault(OTP_out)
0.874
0.920
0.966
V
VFault = VFault(OTP_in) + 0.2 V
7
IFault(OTP)
42.5
45.5
48.5
mA
VFault = open
7
VFault(clamp)
1.5
1.75
2.0
V
7
RFault(clamp)
1.32
1.55
1.82
kW
OTP Pull−up Current Source (Note 7)
Fault Input Clamp Voltage
Fault Input Clamp Series Resistor
7. NTC with R110 = 8.8 kW (TTC03-474)]
THERMAL PROTECTION
Thermal Shutdown
Temperature increasing
N/A
TSHDN
−
150
−
°C
Thermal Shutdown Hysteresis
Temperature decreasing
N/A
TSHDN(HYS)
−
40
−
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
11
NCL30030
DETAILED OPERATING DESCRIPTION
INTRODUCTION
must be considered to correctly size CCC. The increase in
current consumption due to external gate charge is
calculated using Equation 1.
The NCL30030 is a combination critical mode (CrM)
power factor correction (PFC) and quasi−resonant (QR)
flyback controller optimized for high performance LED
driver applications.
I CC(gatecharge) + f @ Q G
(eq. 1)
where f is the operating frequency and QG is the gate charge
of the external MOSFETs.
HIGH VOLTAGE STARTUP CIRCUIT
The NCL30030 integrates a high voltage startup circuit
accessible by the BO/HV pin. The BO/HV input is also used
for monitoring the ac line voltage and detecting brown−out
faults. The startup circuit is rated at a maximum voltage of
700 V to support higher voltages used in commercial
lighting such as 277 and 347 VAC.
A startup regulator consists of a constant current source
that supplies current from the ac input terminals (Vin) to the
supply capacitor on the VCC pin (CCC). The startup circuit
current (Istart2A) is typically 3.75 mA. Istart2A is disabled if
the VCC pin is below VCC(inhibit). In this condition the
startup current is reduced to Istart1A, typically 0.5 mA. The
internal high voltage startup circuit eliminates the need for
external startup components. In addition, the startup
regulator helps increase the system efficiency as it uses
negligible power in the normal operation mode.
Once CCC is charged to the startup threshold, VCC(on),
typically 17 V, the startup regulator is disabled and the
controller is enabled. The startup regulator will remain
disabled until VCC falls below the minimum operating
voltage threshold, VCC(off), typically 8.8 V. Once reached,
the PFC and flyback controllers are disabled reducing the
bias current consumption of the IC. The startup circuit is
then are then enabled allowing VCC to charge back up.
A dedicated comparator monitors VCC when the QR stage
is enabled and latches off the controller if VCC exceeds
VCC(OVP), typically 28 V.
The controller is disabled once a fault is detected. The
controller will restart the next time VCC reaches VCC(on) and
all non−latching faults have been removed.
The supply capacitor provides power to the controller
during power up. The capacitor must be sized such that a
VCC voltage greater than VCC(off) is maintained while the
auxiliary supply voltage is building up. Otherwise, VCC will
collapse and the controller will turn off. The operating IC
bias current, ICC4, and gate charge load at the drive outputs
LINE VOLTAGE SENSE
The BO/HV pin provides access to the brown−out and line
voltage detectors. The brown−out detector detects mains
interruptions and the line voltage detector determines the
presence of either 120 V or 230 V ac mains. Depending on
the detected input voltage range device parameters are
internally adjusted to optimize the system performance.
This pin can connect after the rectifier bridge to achieve
full wave rectification as shown in Figure 3. A diode is used
to prevent the pin from going below ground. A low value
resistor in series with the BO/HV pin can be used for
protection. A low value resistor is needed to reduce the
voltage offset while sensing the line voltage.
AC
Input
EMI
Filter
BO/HV
NCL30030
Figure 3. Brown−out and Line Voltage Detectors
Configuration
The flyback stage is enabled once VBO/HV is above the
brown−out threshold, VBO(start), typically 111 V, and VCC
reaches VCC(on). The high voltage startup is immediately
enabled when the voltage on VBO/HV crosses over the
brown−out start threshold, VBO(start), to ensure that device is
enabled quickly upon exiting a brown−out state. Figure 4
shows typical power up waveforms.
www.onsemi.com
12
NCL30030
Figure 4. Startup Timing Diagram
www.onsemi.com
13
NCL30030
reduced by a factor of 3, resulting in a maximum output
power independent of input voltage.
The default power−up mode of the controller is low line.
The controller switches to “high line” mode if VBO/HV
exceeds the line select threshold for longer than the low to
high line timer, t(low to high line), typically 300 ms, as long as
it was not previously in high line mode. If the controller has
switched from “high line” to “low line” mode, the low to
high line timer, t(low to high line), is inhibited until VBO/HV
falls below VBO(stop). This prevents the controller from
toggling back to “high line” until at least one VBO(stop)
transition has occurred. The timer and logic is included to
prevent unwanted noise from toggling the operating line
level.
In “high line” mode the high to low line timer, t(high to low
line), (typically 54 ms) is enabled once VBO/HV falls below
VBO(lineselect). It is reset once VBO/HV exceeds
VBO(lineselect). The controller switches back to “low line”
mode if the high to low line timer expires.
A timer is enabled once VBO/HV drops below its stop
threshold, VBO(stop), typically 101 V. If the timer, tBO,
expires the device will begin monitoring the voltage on
VBO/HV and disable the PFC and flyback stages when that
voltage is below the Brown−out Drive Disable threshold,
VBO(DRV_disable), typically 30 V. This ensures that device
switching is stopped in a low energy state which minimizes
inductive voltage kick from the EMI components and ac
mains. The timer, tBO, typically 54 ms, is set long enough to
ignore a single cycle drop−out.
LINE VOLTAGE DETECTOR
The input voltage range is detected based on the peak
voltage measured at the BO/HV pin. Discrete values are
selected for the PFC stage gain (feedforward) depending on
the input voltage range. The controller compares VBO/HV to
an internal line select threshold, VBO(lineselect), typically
240 V. Once VBO/HV exceeds VBO(lineselect), the PFC stage
operates in “high line” (Commercial US − 277 Vac) or
“230 Vac” mode. In high line mode the maximum on time is
Figure 5. Line Detector Waveforms
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14
NCL30030
FAULT INPUT
the upper threshold, the external pull−up current has to be
higher than the pull−down capability of the clamp (set by
RFault(clamp) at VFault(clamp)). The upper fault threshold is
intended to be used for an overvoltage fault using a Zener
diode and a resistor in series from the auxiliary winding
voltage, VAUX. The controller goes into a triple hiccup once
VFault exceeds VFault(OVP).
The Fault input signal is filtered to prevent noise from
triggering the fault detectors. Upper and lower fault detector
blanking delays, tdelay(Fault_OVP) and tdelay(Fault_OTP) are
both typically 30 ms. A fault is detected if the fault condition
is asserted for a period longer than the blanking delay.
A bypass capacitor is usually connected between the Fault
and GND pins and it will take some time for VFault to reach
its steady state value once IFault(OTP) is enabled. Therefore,
a lower fault (i.e. overtemperature) is ignored during
soft−start. In Option B, IFault(OTP) remains enabled while
the lower fault is present independent of VCC in order to
provide temperature hysteresis. The upper OVP fault
detection is enabled and remains active as long as the QR
flyback is enabled.
Once the controller is latched, it is reset if a brown−out
condition is detected or if VCC is cycled down to its reset
level, VCC(reset). In the typical application these conditions
occur only if the ac voltage is removed from the system.
Prior to reaching VCC(reset), Vfault(clamp) is set at 0 V.
The NCL30030 includes a dedicated fault input
accessible via the Fault pin. The controller will enter triple
hiccup mode when the pin is pulled above the upper fault
threshold, VFault(OVP), typically 3.0 V. The controller is
disabled if the Fault pin voltage, VFault, is pulled below the
lower fault threshold, VFault(OTP_in), typically 0.4 V. The
lower threshold is normally used for detecting an
overtemperature fault. The controller operates normally
while the Fault pin voltage is maintained within the upper
and lower fault thresholds. Figure 6 shows the architecture
of the Fault input.
The lower fault threshold is intended to be used to detect
an overtemperature fault using an NTC thermistor. A pull up
current source IFault(OTP), (typically 45.5 mA) generates a
voltage drop across the thermistor. The resistance of the
NTC thermistor decreases at higher temperatures resulting
in a lower voltage across the thermistor. The controller
detects a fault once the thermistor voltage drops below
VFault(OTP_in). Part option A latches off the controller after
an overtemperature fault is detected. For part option B the
controller is re−enabled once the fault is removed such that
VFault increases above VFault(OTP_out) and VCC reaches
VCC(on). Figure 7 shows typical waveforms related to the
latch option where as Figure 8 shows waveforms of the
auto−recovery option.
An active clamp prevents the Fault pin voltage from
reaching the upper latch threshold if the pin is open. To reach
VAUX
+
−
VDD
Blanking
tdelay(Fault_OTP)
VFault(OVP)
S
Q
Triple Hiccup
R
IFault(OTP)
Fault
Vfault(OTP)
NTC
Thermistor
RFault(clamp)
VFault(clamp)
−
+
Blanking
tdelay(Fault_OTP)
Soft−start
end
Hysteresis
Control
Figure 6. Fault Detection Schematic
www.onsemi.com
15
S
Q
Latch
R
Option
Auto−restart
Control
Auto−restart
NCL30030
Figure 7. Latch−off Function Timing Diagram
Figure 8. OTP Auto−Recovery Timing Diagram
QR FLYBACK VALLEY LOCKOUT
reduce switching losses and electromagnetic interference
(EMI).
The operating frequency of a traditional QR flyback
controller is inversely proportional to the system load. That
is, a load reduction increases the operating frequency. This
traditionally requires a maximum frequency clamp to limit
the operating frequency. This causes the controller to
become unstable and jump (or hesitate) between two valleys
generating audible noise. The NCL30030 incorporates a
patent pending valley lockout circuitry to eliminate valley
jumping. Once a valley is selected, the controller stays
locked in this valley until the output power changes
significantly. Like a traditional QR flyback controller, the
frequency increases when the load decreases. Once a higher
valley is selected the frequency decreases very rapidly. It
The NCL30030 integrates a quasi−resonant (QR) flyback
controller. The power switch turn−off of the QR converter
is determined by the peak current set by the feedback loop.
The switch turn−on is determined by the transformer
demagnetization. The demagnetization is detected by
monitoring the transformer auxiliary winding voltage.
Turning on the power switch once the transformer is
demagnetized or reset reduces switching losses. Once the
transformer is demagnetized, the drain voltage starts ringing
at a frequency determined by the transformer magnetizing
inductance and the drain lump capacitance eventually
settling at the input voltage. A QR controller takes
advantage of the drain voltage ringing and turns on the
power switch at the drain voltage minimum or “valley” to
www.onsemi.com
16
NCL30030
or increases, the valley comparators toggle one after another
to select the proper valley. The activation of an “n” valley
comparator blanks the “n−1” or “n+1” valley comparator
output depending if VQFB decreases or increases,
respectively.
A valley is detected once VQZCD falls below the QR
flyback demagnetization threshold, VQZCD(th), typically
55 mV. The controller will switch once the valley is detected
or increment the valley counter depending on QFB voltage.
will continue to increase if the load is further reduced. This
technique extends QR operation over a wider output power
range while maintaining good efficiency and limiting the
maximum operating frequency. Figure 9 shows a qualitative
frequency vs output power relationship.
Figure 10 shows the internal arrangement of the valley
detection circuitry. An internal counter increments each
time a valley is detected. The operating valley (1st, 2nd, 3rd
or 4th) is determined by the QFB voltage. As VQFB decreases
Figure 9. Valley Lockout Frequency vs Output Power Relationship
VDD
IQFB
RQFB
QFB
VDD
Minimum
Frequency
Oscillator
CT
Setpoint
IQCT
QR Logic
QCT
demag
QZCD
ROPPU
QDRV(internal)
Timeout
QZCD Comparator
+
−
VQZCD(th)
RQCZD
LAUX
QDRV(internal)
Blanking
(tblank)
Figure 10. Valley Detection Circuitry
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17
Overcurrent
QCT
Discharge
S
Q
Dominant
Reset
Latch
Q
R
QDRV(internal)
NCL30030
VQFB falls below VHVCOD. In VCO mode the peak current
is set to VQILIM1*KIpeak(VCO) as shown in Figure 12. The
operating frequency in VCO mode is adjusted to deliver to
required output power.
A hysteresis between valleys provides noise immunity
and helps stabilize the valley selection in case of small
perturbations on VQFB.
Figure 11 shows the operating valley versus VQFB. Once
a valley is asserted by the valley selection circuitry, the
controller is locked in this valley until VQFB decreases or
increases such that VQFB reaches the next valley threshold.
A decrease in output power causes the controller to switch
from “n” to “n+1” valley until reaching the 4th valley.
A further reduction of output power causes the controller
to enter the voltage control oscillator (VCO) mode once
Valley
VCO
4th
3rd
2nd
1st
VHVCOD
VH4D
V H3D
V H2D
V HVCOI
V QFB
V H4I
V H3I
V H2I
V QILIM1*KQFB
Figure 11. Selected Operating Valley versus VQFB
Peak current
Setpoint
Skip
VCO
Mode
QR Mode
VQILIM1
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1st Valley
2nd
3rd
Fault
4th
Ipeak(VCO)*VQILIM1
VQFB(TH)
VQSKIP VHVCOD
VH4D
VH3D
VH2D
VQILIM1*KQFB
VQFB
Figure 12. Operating Valley versus VQFB
Figures 13 through 16 show drain voltage, VQFB and
VQCT simulation waveforms for a reduction in output
power. The transitions between 2nd to 3rd, 3rd to 4th and 4th
valley to VCO mode are observed without any instabilities
or valley jumping.
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18
NCL30030
Plot1
vdrain in volts
700
Zoom 1
Zoom 2
Zoom 3
500
Vdrain
300
1
100
Plot2
feedback in volts
−100
2.00
1.60
1.20
800m
VQFB
400m
2
VQCT
Plot3
vct in volts
7.00
5.00
3.00
1.00
−1.00
3.64m
4.91m
6.18m
time in seconds
7.45m
8.72m
Figure 13. Operating Mode Transitions Between 2nd to 3rd, 3rd to 4th and 4th Valley to VCO Mode
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19
NCL30030
2 feedback
3 vct
1 vdrain
Vdrain
500
Plot1
vdrain in volts
Plot1
vdrain in volts
1 vdrain
700
1
300
100
VQFB
2.05
2
1.95
1.85
1.75
6.00
Vdrain
500
300
1
100
1.38
2
1.34
1.30
1.26
VQFB
1.22
4.00
Plot3
vct in volts
Plot3
vct in volts
3 vct
−100
2.15
Plot2
feedback in volts
Plot2
feedback in volts
−100
2 feedback
700
VQCT
4.00
2.00
0
−2.00
VQCT
3.00
2.00
1.00
0
3.70m
3.78m
3.86m
time in seconds
3.94m
4.02m
5.90m
Figure 14. Zoom 1: 2nd to 3rd Valley
Transition
1 vdrain
2 feedback
6.00m
time in seconds
6.05m
6.11m
Figure 15. Zoom 2: 3rd to 4th Valley
Transition
3 vct
Vdrain
700
Plot1
vdrain in volts
5.95m
500
300
1
100
Plot2
feedback in volts
−100
1.12
1.02
2
919m
819m
VQFB
719m
Plot3
vct in volts
8.00
VQCT
6.00
4.00
2.00
0
7.10m
7.21m
7.32m
time in seconds
7.43m
7.55m
4th
Figure 16. Zoom 3:
Valley to VCO Mode
Transition
VCO MODE
capacitor is charged with a constant current source, IQCT,
typically 20 mA.
The capacitor voltage, VQCT, is compared to an internal
voltage level, Vf(QFB), inversely proportional to VQFB The
relationship between and Vf(QFB) and VQFB is given by
Equation 2).
The controller enters VCO mode once VQFB falls below
VHVCOD and remains in VCO until VQFB exceeds VHVCOI.
In VCO mode the peak current is set to VQILIM1*Ipeak(VCO)
and the operating frequency is linearly dependent on VQFB.
The product of VQILIM1*Ipeak(VCO) is typically 12.5%. A
minimum frequency clamp, fVCO(MIN), typically 27 kHz,
prevents operation in the audible range. Further reduction in
output power causes the controller to enter skip operation.
The minimum frequency clamp is only enabled when
operating in VCO mode.
The VCO mode operating frequency is set by the timing
capacitor connected between the QCT and GND pins. This
V f(QFB) + 5 * 2 @ V QFB
(eq. 2)
A drive pulse is generated once VQCT exceeds Vf(QFB)
followed by the immediate discharge of the timing capacitor.
The timing capacitor is also discharged once the minimum
frequency clamp is reached. Figure 17 shows simulation
waveforms of Vf(QFB), VQDRV and output current while
operating in VCO mode.
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20
800m
600m
IOUT
400m
200m
Plot2
v(fbint:x1), vct in volts
Plot1
iout in amperes
NCL30030
1
0
7.00
5.00
3
2
VQCT
3.00
Vf(QFB)
1.00
−1.00
Plot3
drv in volts
30.0
20.0
VQDRV
10.0
0
−10.0
7.57m
7.78m
7.99m
time in seconds
8.20m
8.40m
Figure 17. VCO Mode Operating Waveforms
FLYBACK TIMEOUT
During startup, the voltage offset added by the overpower
compensation diode, DOPP, prevents the QZCD Comparator
from accurately detecting the valleys. In this condition, the
steady state timeout period will be shorter than the inductor
demagnetization period causing continuous current mode
(CCM) operation. CCM operation lasts for a few cycles until
the voltage on the QZCD pin is high enough to detect the
valleys. A longer timeout period, tQ(tout1), (typically 100 ms)
is set during soft−start to limit CCM operation. Figures 19
and 20 show the timeout period generator related
waveforms.
In case of extremely damped oscillations, the QZCD
comparator may be unable to detect the valleys. In this
condition, drive pulses will stop waiting for the next valley
or ZCD event. The NCL30030 ensures continued operation
by incorporating a maximum timeout period after the last
demagnetization detection. The timeout signal is a substitute
for the ZCD signal for the valley counter. Figure 18 shows
the timeout period generator circuit schematic. The steady
state timeout period, tQ(tout2), is set at 6 ms to limit the
frequency step.
QZCD Comparator
QZCD
demag
DOPP
ROPPU
+
V
− QZCD(th)
QR Logic
RQCZD
LAUX
QDRV(internal)
QDRV(internal)
Blanking
tZCD(blank)
Soft−start
Complete
Minimum
Frequency
Oscillator
Timeout
Steady
State
Timeout
(tout2) R
Soft−Start
Timeout
(tout1)
R
Figure 18. Timeout Period Generator Circuit Schematic
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21
NCL30030
3
4
high
The 3rd valley is
validated
VQZCD
VQZCD(th)
14
2nd, 3rd
low
high
The 2nd valley is detected
by the QZCD Comparator
12
The 3rd valley is not detected
by the QZCD Comparator
low
high
15
QZCD
Comparator
Output
Timeout
low
16
Timeout adds a pulse to account for
the missing 3rd valley
high
Clk
low
17
Figure 19. Timeout Operation With a Missing 3rd Valley
VQZCD
VQZCD(th)
3
4
high
The 4th valley is
validated
18
3rd, 4th
low
14
high
QZCD
Comparator
15 Output
low
high
Timeout
16
low
Timeout adds 2 pulses to account
for the missing 3rd and 4th valleys
high
Clk
low
17
Figure 20. Timeout Operation With Missing 3rd and 4th Valleys
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22
NCL30030
QR FLYBACK CURRENT SENSE AND OVERLOAD
The Maximum Peak Current Comparator compares the
current sense signal to a reference voltage to limit the
maximum peak current of the system. The maximum peak
current reference voltage, VQILIM1, is typically 0.8 V. The
maximum peak current setpoint is reduced by the overpower
compensation circuitry. An overload condition causes the
output of the Maximum Peak Current Comparator to
transition high and enable the overload timer. Figure 21
shows the implementation of the current sensing circuitry.
The power switch on time is modulated by comparing a
ramp proportional to the switch current to VQFB/KQFB using
the PWM Comparator. The switch current is sensed across
a current sense resistor, RSENSE, and the resulting voltage is
applied to the QCS pin. The current signal is blanked by a
leading edge blanking (LEB) circuit. The blanking period
eliminates the leading edge spike and high frequency noise
during the switch turn−on event. The LEB period,
tQCS(LEB1), is typically 275 ns. The drive pulse terminates
once the current sense signal exceeds VQFB/KQFB.
VDD
VQFB
IQFB RQFB
Skip
QFB
+
−
VQSKIP
Ipeak(VCO) =
KQCS(VCO)
VQZCD
PWM
Comparator
/KQFB
+
Peak Current
Comparator
LEB
tQCS(LEB1)
Short−Circuit
Comparator
nQILIM2
+
Disable QDRV
VQZCD
VQILIM1
VDD
LEB
IQCS
+
−
Overload Timer
tQOVLD
Count Down
Count Up
QCS
tQCS(LEB2)
Counter
+
VQILIM2
−
Figure 21. Current Sensing Circuitry Schematic
The overload timer integrates the duration of the overload
fault. That is, the timer count increases while the fault is
present and reduces its count once it is removed. The
overload timer duration, tQOVLD, is typically 80 ms. If both
the PWM and Maximum Peak Current Comparators toggle
at the same time, the PWM Comparator takes precedence
and the overload timer counts down. The controller can latch
(option A) or allow for auto−recovery (option B) once the
overload timer expires. Auto−recovery requires a VCC triple
hiccup before the controller restarts. Figures 22 and 23
show operating waveforms for latched and auto−recovery
overload conditions.
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23
NCL30030
Figure 22. Latched Overload Operation
Figure 23. Auto−Recovery Overload Operation
The NCL30030 protects against this fault by adding an
additional comparator, Fault Overcurrent Comparator. The
current sense signal is blanked with a shorter LEB duration,
tQCS(LEB2), typically 120 ns, before applying it to the Fault
Overcurrent Comparator. The voltage threshold of the
comparator, VQILIM2, typically 1.2 V, is set 50% higher than
VQILIM1, to avoid interference with normal operation. Four
A severe overload fault like a secondary side winding
short−circuit causes the switch current to increase very
rapidly during the on−time. The current sense signal
significantly exceeds VQILIM1. But, because the current
sense signal is blanked by the LEB circuit during the switch
turn on, the system current can get extremely high causing
system damage.
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24
NCL30030
overtemperature) is blanked. Soft−start ends once VSSTART
exceeds the peak current sense signal threshold.
consecutive faults detected by the Fault Overcurrent
Comparator causes the controller to enter triple−hiccup
auto−recovery mode. The count to 4 provides noise
immunity during surge testing. The counter is reset each
time a QDRV pulse occurs without activating the Fault
Overcurrent Comparator. A 1 mA (typically) pull−up current
source, IQCS, pulls up the QCS pin to disable the controller
if the pin is left open.
QR FLYBACK OVERPOWER COMPENSATION
The input voltage of the QR flyback stage varies with the
line voltage and operating mode of the PFC converter. At
low line the PFC bulk voltage is 220 V and at high line it will
be 390 V or 440 V, depending on the version of the part.
Additionally, the PFC can be disabled at which point the
PFC bulk voltage is set by the rectified peak line voltage.
An integrated overpower circuit provides a relative
constant output power across PFC bulk voltage, Vbulk. It
also reduces the variation on VQFB during the PFC stage
enable or disable transitions. Figure 24 shows the circuit
schematic for the overpower detector.
QR FLYBACK SOFT−START
Soft−start is achieved by ramping up an internal reference,
VSSTART, and comparing it to current sense signal. VSSTART
ramps up from 0 V once the controller powers up. The
soft−start duration, tSSTART, is typically 4 ms.
During soft−start the timeout duration is extended and the
lower latch or OTP Comparator signal (typically for
QZCD
DOPP
RQCZD
LAUX
ROPPU
QZCD Comparator
+
−
ROPPL
QFB
VQZCD(th)
Peak Current
Comparator
+
/4
+
−
VQILIM1
Disable
QDRV
+
KQCS(VCO) +
−
QCS
Other Faults
PWM
Comparator
LEB
tQCS(LEB1)
Figure 24. Overpower Compensation Circuit Schematic
The voltage is scaled down using ROPPU and ROPPL. The
negative voltage applied to the pin is referred to as VOPP.
The internal current setpoint is the sum of VOPP and peak
current sense threshold, VQILIM1. VOPP is also subtracted
from VQFB to compensate for the PWM Comparator delay
and improve the PFC on/off accuracy.
The current setpoint is calculated using Equation 3. For
example, a VOPP of −0.15 V results in a current setpoint of
0.65 V.
The auxiliary winding voltage during the power switch on
time is a reflection of the input voltage scaled by the primary
to auxiliary winding turns ratio, NP,AUX, as shown in
Figure 25.
Current setpoint + V QILIM1 ) V OPP
(eq. 3)
To ensure optimal zero−crossing detection, a diode is
needed to bypass ROPPU during the off−time. Equation 4 is
used to calculate ROPPU and ROPPL.
R QZCD ) R OPPU
R OPPL
Figure 25. Auxiliary Winding Voltage Waveform
+*
N P,AUX @ V bulk * V OPP
(eq. 4)
V OPP
ROPPU is selected once a value is chosen for ROPPL.
ROPPL is selected large enough such that enough voltage is
available for the zero crossing detection during the off−time.
Overpower compensation is achieved by scaling down the
on−time reflected voltage and applying it to the QZCD pin.
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25
NCL30030
at the end of each switch cycle. Figure 26 shows the PFC
inductor current while operating in CrM. High power factor
and low harmonic distortion is achieved by shaping the input
current, Iin(t), such that it is sinusoidal and in phase with the
ac line voltage, Vin(t).
It is recommended to have at least 8 V applied on the QZCD
pin for good detection. The maximum voltage is internally
clamped to VCC. The off−time voltage on the QZCD is given
by Equation 5.
V QZCD + *
R OPPL
R OZCD ) R OPPL
@ ǒV AUX * V FǓ
(eq. 5)
Where VAUX is the voltage across the auxiliary winding and
VF is the DOPP forward voltage drop.
The ratio between RQZCD and ROPPL is given by
Equation 6. It is obtained combining Equations 4 and 5.
R OZCD
R OPPL
+
V AUX * V F * V QZCD
V QZCD
(eq. 6)
A design example is shown below:
System Parameters:
VAUX = 18 V
VF = 0.6 V
NP,AUX = 0.18
Figure 26. Inductor Current in CrM
To achieve unity power factor and low harmonic
distortion the NCL30030 uses a peak current mode control
architecture where the cycle−by−cycle current limit is set by
a multiplier circuit. A block diagram of the control
architecture is shown in Figure 27. The control works by
generating a DC current proportional to the instantaneous
AC line voltage and multiplying that current with the error
voltage generated from the feedback error amplifier.
The multiplication factor is determined by the output of a
comparator which measures the error voltage against a high
frequency ramping signal. As the error voltage approaches
its maximum value, the multiplication factor approaches 1.
The output of the comparator toggles a switch to modulate
the DC current from the current generator. The modulated
current then feeds a resistor to set the peak current limit and
hence control the duty cycle for every switching period. An
external capacitor on the MULT pin is used to filter ripple
caused by the modulation.
This control architecture is effectively a dual loop control
method where the current generator shapes the peak current
setpoint such that it follows the AC input while the error
voltage adjusts the peak current to ensure that bulk voltage
regulation is maintained.
The ratio between RQZCD and ROPPL is calculated using
Equation 6 for a minimum VQZCD of 8 V.
R OZCD
R OPPL
+
18 * 0.6 * 8
[ 1.2
8
RQZCD is arbitrarily set to 1 kW. ROPPL is also set to 1 kW
because the ratio between the resistors is close to 1.
The NCL30030 maximum overpower compensation or
peak current setpoint reduction is 31.25% for a VOPP of
−250 mV. We will use this value for the following example:
Substituting values in Equation 4 and solving for ROPPU
we obtain,
R QZCD ) R OPPU
R OPPL
+*
0.18 @ 370 * (−0.25)
(−0.25)
+ 271
R OPPU + 271 @ R OPPL * R QZCD
R OPPU + 271 @ 1k * 1k + 270k
POWER FACTOR CORRECTION
The PFC stage operates in critical conduction mode
(CrM). In CrM the PFC inductor current, IL(t), reaches zero
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26
NCL30030
BO/HV
Low/High Line
Vbulk
IMULT
Ramp
Signal
Error
Amplier
R1
PFB
MULT
PWM
Comparator
PCS/PZCD
Multiplier
Comparator
+
−
R2
VPREF
PControl
Reset PDRV
LEB1
Figure 27. Multiplier Block Diagram
has a typical gm of 200 mS. The PControl pin provides access
to the amplifier output for compensation. The compensation
network is ground referenced allowing the PFC feedback
signal to detect undervoltage and overvoltage conditions as
shown in Figure 28.
The compensation network on the PControl pin is selected
to filter the bulk voltage ripple such that a constant control
voltage is maintained across the ac line cycle. A capacitor
between the PControl pin and ground sets a pole. A pole at
or below 20 Hz is enough to filter the ripple voltage for a 50
and 60 Hz system. The low frequency pole, fp, of the system
is calculated using Equation 7.
PFC FEEDBACK
The PFC feedback circuitry is shown in Figure 28. A
resistor divider consisting of R1 and R2 scales down the PFC
output voltage, Vbulk, to generate a PFC feedback signal.
The feedback signal is applied to the inverting input of a
transconductance error amplifier which regulates Vbulk by
comparing the PFC feedback signal to an internal reference
voltage, VPREF. The reference is connected to the
non−inverting input of the error amplifier and is trimmed
during manufacturing to achieve an accuracy of ±2% across
temperature.
PFC OVP
Circuitry
Vbulk
fp +
POVP
PFC UVP
Comparator
R1
PFB
+
−
VPFB(disable)
Error
Amplier
VBOHV
PWM
Comparator
Multiplier
PDRV Reset
+
−
VPREF
VPCS
PFC TRANSIENT RESPONSE
VDD
PControl
The PFC bandwidth is set low enough to achieve good
power factor. However, a low bandwidth system is slow and
fast load transients can result in large output voltage
excursions. The NCL30030 incorporates dedicated circuitry
to help maintain regulation of the output voltage
independent of load transients.
An undervoltage detector monitors the ratio between
VPFB and VPREF(xL). Once the ratio between VPFB and
VPREF(xL) exceeds KLOW(PFCxL), typically 5.5%, a pull−up
current source on the PControl pin, IPControl(boost), is enabled
to speed up the charge of the compensation network. This
results in an increased on−time and thus output power.
IPControl(boost) is typically 240 mA. The boost current source
VPControl(MAX)
VPControl(MIN)
(eq. 7)
where, CPControl is the capacitor on the PControl pin to
ground.
The output of the error amplifier is held low when the PFC
is disabled by means of an internal pull−down transistor. The
pull down transistor is disabled once the PFC stage is
enabled. An internal voltage clamp is then enabled to
quickly raise VPControl to its minimum voltage,
VPControl(min), typically 0.6 V.
PUVP
R2
gm
2pC PControl
Disable PFC
PUVP
Figure 28. PFC Regulation Circuit Schematic
PFC ERROR AMPLIFIER
A transconductance amplifier has a voltage−to−current
gain, gm. That is, the amplifier’s output current is controlled
by the differential input voltage. The NCL30030 amplifier
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27
NCL30030
VPFB
exceeds
the
hard−OVP
level,
VPOVP
(VPREF(xL)*KPOVP(xL)). Soft−OVP reduces the on−time
proportional to the delta between VPFB and the hard−OVP
level. Soft−OVP is enabled once the delta, DPOVP(xL),
between VPFB and the hard−OVP level is between 20 and 55
mV. Figure 29 shows a block diagram of the boost and
Soft−OVP circuits.
During power up, VPControl exceeds the regulation level
due to the system’s inherently low bandwidth. This causes
the bulk voltage to rapidly increase and exceed its
regulation. The on time starts to decrease when soft−OVP is
activated. Once the bulk voltage decreases to its regulation
level the PFC on time is no longer controlled by the
soft−OVP circuitry.
is disabled once the ratio between VPFB and VPREF(xL) drops
below KLOW(PFCxL), typically 4%.
The boost current source becomes active as soon as the
PFC is enabled. Coupled with the lower control clamp, the
boost current source assists in rapidly bringing VPControl to
its set point to allow the bulk voltage to quickly reach
regulation. Achieving regulation is detected by monitoring
the error amplifier output current. The error amplifier output
current drops to zero once the PFC output voltage reaches
the target regulation level.
The maximum PFC output voltage is limited by the
overvoltage protection circuitry. The NCL30030
incorporates both soft and hard overvoltage protection. The
hard overvoltage protection function immediately
terminates and prevents further PFC drive pulses when
PDRV
Low/High Line
On−Time
Comparator
RAMP
Generator
Fixed
Reference
R
Q
Dominant
Reset
Latch
Q
S
PCS/PZCD
LEB1
MULT
PWM
Comparator
V DD
PControl
PDRV
VBOHV
VPOVP
VPControl(MAX)
VPControl(MIN)
MULTIPLIER
VDD
A
Soft OVP
Comparator
Boost
Comparator
+
−
Error
Amplier
PFB
IPControl(boost)
V * KLOW
+
VPREF
−
Regulation
Detector
Regulation OK
Figure 29. Boost and Soft−OVP Circuit Schematics
PFC CURRENT SENSE AND ZERO CURRENT
DETECTION
single input terminal. Figure 30 shows the circuit schematic
of the current sense and ZCD detectors.
The NCL30030 uses a novel architecture combining the
PFC current sense and zero current detectors (ZCD) in a
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28
NCL30030
tPFC(off) Timer
PDRV
PILIM2
Reset
S
Q
R
Q
+
PFC Boost
Diode
PFC Inductor
V
− PZCD(rising)
PFC Switch
tPZCD_Blank
PDRV
RPsense
To PDRV Set
PDRV
D
RPCS
RPZCD
Q
CLK
+
PCS/PZCD
PDRV
V
− PZCD(falling)
Q
Current Limit
Comparator
LEB1
tPCS(LEB1)
VPILIM1
R
+
−
LEB2
tPCS(LEB2)
VPILIM2
PDRV
Short Circuit
Comparator PDRV
PILIM1
PILIM2
+
−
Figure 30. PFC Current Sense and ZCD Detectors Schematic
PFC CURRENT SENSE
comparator, VPILIM2, typically 2 V, is set 33% higher than
VPILIM1, to avoid interference with normal operation.
Whenever a fault is detected by the Short Circuit
Comparator, the watchdog timer increases to 1 ms allowing
the system time to recover from the excessive over current.
The next PFC drive pulse is then initiated when the
watchdog timer expires.
The PFC Switch current is sensed across a sense resistor,
RPsense, and the resulting voltage ramp is applied to the
PCS/PZCD pin. The current signal is blanked by a leading
edge blanking (LEB) circuit. The blanking period eliminates
the leading edge spike and high frequency noise during the
switch turn−on event. The LEB period, tPCS(LEB1), is
typically 325 ns. The Current Limit Comparator disables the
PFC driver once the current sense signal exceeds the PFC
current sense reference, VPILIM1, typically 1.5 V.
A severe overload fault like a PFC boost diode short
circuit causes the switch current to increase very rapidly
during the on−time. The current sense signal significantly
exceeds VPILIM1. But, because the current sense signal is
blanked by the LEB circuit during the switch turn on, the
system current can get extremely high causing system
damage.
The NCL30030 protects against this fault by adding an
additional comparator, PFC Short Circuit Comparator. The
current sense signal is blanked with a shorter LEB duration,
tPCS(LEB2), typically 175 ns, before applying it to the PFC
Short Circuit Comparator. The voltage threshold of the
PFC ZERO CURRENT DETECTION
The off−time in a CrM PFC topology varies with the
instantaneous line voltage and is adjusted every switching
cycle to allow the inductor current to reach zero before the
next switching cycle begins. The inductor is demagnetized
once its current reaches zero. Once the inductor is
demagnetized the drain voltage of the PFC switch begins to
drop. The inductor demagnetization is detected by sensing
the voltage across the inductor using an auxiliary winding.
This winding is commonly known as a zero crossing
detector (ZCD) winding. This winding provides a scaled
version of the inductor voltage. Figure 31 shows the ZCD
winding arrangement.
www.onsemi.com
29
NCL30030
PFC Inductor
PFC Switch
Rectied
ac line
voltage
During startup there are no ZCD transitions to set the PFC
PWM Latch and generate a PDRV pulse. A watchdog timer,
tPFC(off1), starts the drive pulses in the absence of ZCD
transitions. Its duration is typically 200 ms. The timer is also
useful if the line voltage transitions from low line to high line
and while operating at light load because the amplitude of
the ZCD signal may be too small to cross the ZCD arming
threshold. The watchdog timer is reset at the beginning of a
PFC drive pulse. It is disabled during a PFC hard
overvoltage and feedback input short circuit condition.
PFC
output
voltage
PDRV
RPsense
RPCS
RPZCD
PCS/PZCD
PFC ENABLE & DISABLE
Figure 31. ZCD Winding Implementation
In some applications it is desired to disable the PFC at
lighter loads to increase the overall system efficiency. The
NCL30030 integrates a novel architecture that allows the
user to program the PFC disable threshold based on the
percentage of QR output power. The PFC enable circuitry is
inactive until the QR flyback soft start period has ended. A
voltage to current (V−I) converter generates a current
proportional to VQFB. This current is pulse width modulated
by the demagnetization time of the flyback controller to
generate a current, IPONOFF, proportional to the output
power. An external resistor, RPONOFF, between the
PONOFF and GND pins is used to scale the output power
signal. A capacitor, CPONOFF, in parallel with RPONOFF is
required to average the signal on this pin. A good
compromise between voltage ripple and speed is achieved
by setting the time constant of CPONOFF and RPONOFF to
160 ms.
The PONOFF pin voltage, VPONOFF, is compared to an
internal reference, VPOFF (typically 2 V) to disable the PFC
stage. In high power SSL applications it is often desired to
control the PFC disable point from the secondary side. An
optocoupler can be used as a logic disable to ground the
PONOFF pin when the PFC needs to be disabled.
Once VPONOFF decreases below VPOFF, the PFC disable
timer, tPdisable, is enabled. The PFC disable timer is typically
500 ms. The PFC stage is disabled once the timer expires.
The PFC stage is enabled once VPONOFF exceeds VPOFF by
VPONHYS for a period longer than the PFC enable filter,
tPenable(filter), typically 100 ms. A shorter delay for the PFC
enable threshold is used to reduce the bulk capacitor
requirements during a step load response. Figure 33 shows
the block diagram of the PFC disable circuit.
The ZCD voltage, VZCD, is positive while the PFC Switch
is off and current flows through the PFC inductor. VZCD
drops to and rings around zero volts once the inductor is
demagnetized. The next switching cycle begins once a
negative transition is detected on the PCS/PZCD pin. A
positive transition (corresponding to the PFC switch turn
off) arms the ZCD detector to prevent false triggering. The
arming of the ZCD detector, VPZCD(rising), is typically
0.75 V. The trigger threshold, VPZCD(falling), is typically
0.25 V. The NCL30030 also incorporates a blanking period,
TPZCD_Blank which prevents detection of a ZCD event for
700 ns after the PFC switch turn off.
The PCS/PZCD pin is internally clamped to 5 V with a
Zener diode and a 2 kW resistor. A resistor in series with the
PCS/PZCD pin is required to limit the current into pin. The
Zener diode also prevents the voltage from going below
ground. Figure 32 shows typical ZCD waveforms.
Figure 32. ZCD Winding Waveforms
www.onsemi.com
30
NCL30030
QFB
V to I
Converter
Demag
Time
Calculator
PFC Disable
Timer
Enable
t Pdisable
Reset
QZCD
QDRV
IPONOFF
PONOFF
CPONOFF
+
Release
PControl
S
Q
Dominant
Reset
Latch
Q
R
Disable PFC
PFC Enable
Timer
tPenable
Filter Delay
tPenable(filter)
VPOFF
−
RPONOFF
−
+
PONOFF
Comparator
Soft−Start Complete
Hysteresis Control
Figure 33. PFC On/Off Control Circuitry
PFC SKIP
AUTO−RECOVERY
The PFC stage incorporates skip cycle operation at light
loads to reduce input power. Skip operation disables the PFC
stage if the PControl voltage decreases below the skip
threshold. The skip threshold voltage is typically 25 mV
(DVPSKIP) above the PControl minimum voltage clamp,
VPControl(MIN). The PFC stage is enabled once VPControl
increases above the skip threshold by the skip hysteresis,
VPSKIP(HYS). PFC skip is disabled during any initial PFC
startup and when the PFC is in a UVP. Skip operation will
become active after the PFC has reached regulation.
The controller is disabled and enters “triple−hiccup”
mode if VCC drops below VCC(off). The controller will also
enter “triple−hiccup” mode if an overload fault is detected
on the non−latching version. A hiccup consists of VCC
falling down to VCC(off) and charging up to VCC(on). The
controller needs to complete 3 hiccups before restarting.
TEMPERATURE SHUTDOWN
An internal thermal shutdown circuit monitors the
junction temperature of the IC. The controller is disabled if
the junction temperature exceeds the thermal shutdown
threshold, TSHDN, typically 150°C. A continuous VCC
hiccup is initiated after a thermal shutdown fault is detected.
The controller restarts at the next VCC(on) once the IC
temperature drops below below TSHDN by the thermal
shutdown hysteresis, TSHDN(HYS), typically 40°C.
The thermal shutdown fault is also cleared if VCC drops
below VCC(reset), a brown−out fault is detected or if the line
voltage is removed. A new power up sequences commences
at the next VCC(on) once all the faults are removed.
PFC AND FLYBACK DRIVERS
The NCL30030 maximum supply voltage, VCC(MAX), is
30 V. Typical high voltage MOSFETs have a maximum gate
voltage rating of 20 V. Both the PFC and flyback drivers
incorporate an active voltage clamp to limit the gate voltage
on the external MOSFETs. The PFC and flyback voltage
clamps, VPDRV(high2) and VQDRV(high2), are typically 12 V
with a maximum limit of 14 V.
ORDERING INFORMATION
Device
Package
Shipping†
SOIC16 NB LESS PIN 2
(Pb−Free)
2500 / Tape & Reel
NCL30030B1DR2G
NCL30030B2DR2G
NCL30030B3DR2G
NCL30030A1DR2G*
NCL30030A2DR2G*
NCL30030A3DR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Please contact local sales representative for availability
www.onsemi.com
31
NCL30030
PACKAGE DIMENSIONS
SOIC−16 NB MISSING PIN 2
CASE 751DT
ISSUE O
NOTE 5
D
A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS
NOTE 6
OR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE.
DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
A1
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
C SEATING
MILLIMETERS
PLANE
DIM MIN
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.35
0.49
c
0.17
0.25
D
9.80
10.00
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
1.27
0.203 BSC
L2
2X
9
0.10 C D
F
E
0.20 C
2X 4 TIPS
E1
1
NOTE 4
L2
8
B
15X b
NOTE 5
0.25
TOP VIEW
L
DETAIL A
M
C A-B D
2X
0.10 C A-B
0.10 C
DETAIL A
D
0.10 C
e
A
SEATING
PLANE
C
SIDE VIEW
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
15X
1.52
16
9
7.00
8
1
1.27
PITCH
15X
0.60
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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32
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
NCL30030/D