ENA2350 D

Ordering number : EN*A2350
STK581U3C2D-E
Advance Information
http://onsemi.com
Inverter IPM
for 3-phase Motor Drive
Overview
This “Inverter IPM” is highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase
outputs in a single SIP module (Single-In line Package). Output stage uses IGBT/FRD technology and implements
Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal
Boost diodes are provided for high side gate boost drive.
Function
 Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit
 All control input and status output are at low voltage levels directly compatible with microcontrollers
 Built-in cross conduction prevention
 Externally accessible embedded thermistor for substrate temperature measurement
 The level of the over-current protection current is adjustable with the external resistor, “RSD”
Certification
 UL1557 (File Number : E339285).
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Supply voltage
Collector-emitter voltage
Symbol
VCC
VCE
Conditions
Ratings
Unit
P to N, surge < 500V *1
450
P to U,V,W or U,V,W to N
600
V
V
P, N, U,V,W terminal current
±30
A
Output current
Io
P, N, U,V,W terminal current at Tc = 100C
±15
A
Output peak current
Iop
P, N, U,V,W terminal current for a Pulse width of 1ms.
±45
A
Pre-driver voltage
VD1,2,3,4
VB1 to U, VB2 to V, VB3 to W, VDD to VSS *2
20
V
Input signal voltage
VIN
VFAULT
HIN1, 2, 3, LIN1, 2, 3
0.3 to VDD
V
FAULT terminal voltage
FAULT terminal
0.3 to VDD
V
Maximum power dissipation
Pd
IGBT per channel
49
W
Junction temperature
Tj
IGBT,FRD
150
C
Storage temperature
Tstg
40 to +125
C
Operating case temperature
Tc
Tightening torque
Withstand voltage
Vis
40 to +100
C
Case mounting screws *3
1.17
Nm
50Hz sine wave AC 1 minute *4
2000
VRMS
H-IC case temperature
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : Surge voltage developed by the switching operation due to the wiring inductance between “P” and “N” terminal.
*2 : Terminal voltage : VD1=VB1-U, VD2=VB2-V, VD3=VB3-W, VD4=VDDVSS
*3 : Flatness of the heat-sink should be 0.15mm and below.
*4 : Test conditions : AC2500V, 1 second.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
Semiconductor Components Industries, LLC, 2014
July, 2014 Ver.140702YK
70314HK No.A2350-1/15
STK581U3C2D-E
Electrical Characteristics at Tc  25C, VD1, VD2, VD3, VD4 = 15V
Parameter
Symbol
Conditions
Test
circuit
min
typ
max
-
-
0.1
-
-
0.1
Unit
Power output section
Collector-emitter cut-off
current
Bootstrap diode reverse
current
Collector to emitter
saturation voltage
ICE
VCE = 600V
IR(BD)
VR(BD)
VCE(SAT)
Fig.1
Ic = 30A
Tj = 25C
Upper side
-
1.8
2.7
Lower side *1
-
2.1
3.0
Ic = 15A
Tj = 100C
Upper side
-
1.5
-
Fig.2
Lower side *1
-
1.7
-
IF = 30A
Tj = 25C
Upper side
-
2.0
2.9
-
2.3
3.2
IF = 15A
Tj = 100C
Upper side
-
1.5
-
-
1.7
-
Lower side *1
Fig.3
mA
mA
V
Diode forward voltage
VF
Junction to case
thermal resistance
θj-c(T)
IGBT
-
-
2.5
θj-c(D)
FRD
-
-
3
-
0.08
0.4
-
1.6
4
2.5
-
-
V
-
-
0.8
V
0.5
0.8
-
V
-
100
143
A
-
-
2
A
-
2
-
mA
18
-
80
ms
10.5
11.1
11.7
V
10.3
10.9
11.5
V
0.14
0.2
-
V
Lower side *1
V
C/W
Control (Pre-driver) section
VD1, 2, 3 = 15V
Pre-driver power dissipation
ID
High level Input voltage
Vin H
Low level Input voltage
Vin L
Input threshold voltage
hysteresis*1
Logic 1 input leakage current
Vinth(hys)
IIN+
Logic 0 input leakage current
IIN
VIN = +3.3V
VIN = 0V
FAULT terminal input electric
current
FAULT clear time
IoSD
FAULT : ON / VFAULT = 0.1V
FLTCLR
VCCUV+
VSUV+
VCCUV
VSUV
VCCUVH
VSUVH
Fault output latch time.
ISD
PW = 100μs, RSD = 0Ω
ISO
Io = 10A
VCC and VS undervoltage
positive going threshold.
VCC and VS undervoltage
negative going threshold.
VCC and VS undervoltage
hysteresis
Over current protection level
Output level for current monitor
VD4 = 15V
Fig.4
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS
Fig.5
mA
38.5
-
48.2
A
0.32
0.34
0.36
V
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : The lower side’s VCE(SAT) and VF include a loss by the shunt resistance
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2350-2/15
STK581U3C2D-E
Electrical Characteristics at Tc  25C, VD1, VD2, VD3, VD4 = 15V, VCC=300V, L=3.5mH
Parameter
Symbol
Conditions
Test
circuit
min
typ
max
Unit
0.3
0.6
1.3
-
0.9
1.6
-
800
-
J
-
550
-
J
-
1350
-
J
-
530
-
J
-
450
-
J
-
980
-
J
-
39
-
J
-
75
-
Ns
Switching Character
Switching time
tON
tOFF
Turn-on switching loss
Eon
Turn-off switching loss
Eoff
Total switching loss
Etot
Io = 30A
Io = 30A
Turn-on switching loss
Eon
Turn-off switching loss
Eoff
Total switching loss
Etot
Diode reverse recovery energy
Erec
Diode reverse recovery time
trr
Reverse bias safe operating
area
Short circuit safe operating area
RBSOA
Io = 45A, VCE = 450V
SCSOA
VCE = 400V, Tc = 100C
dv/dt
Between U, V, W to N
Allowable offset voltage slew
rate
Io = 15A, Tc = 100C
IF = 15A, P = 400V, Tc = 100C
Fig.6
s
Full square
4
50
-
s
50
V/ns
Reference voltage is “VSS” terminal voltage unless otherwise specified.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Notes :
1. When the internal protection circuit operates, a Fault signal is turned ON (When the Fault terminal is low level, Fault
signal is ON state : output form is open DRAIN) but the Fault signal does not latch.After protection operation ends,it
returns automatically within about 18ms to 80ms and resumes operation beginning condition. So, after Fault signal
detection, set all input signals to OFF (Low) at once.However, the operation of pre-drive power supply low voltage
protection (UVLO : with hysteresis about 0.2V) is as follows.
Upper side :
The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch
will continue till the input signal will turn ‘low’.
Lower side :
The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input
signal voltage.
2. When assembling the IPM on the heat sink with M3 type screw, tightening torque range is 0.79 Nm to 1.17 Nm.
3. The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to
an operating malfunction.
No.A2350-3/15
STK581U3C2D-E
Module Pin-Out Description
Pin
Name
Description
1
VB1
High Side Floating Supply Voltage 1
2
U, VS1
Output 1 - High Side Floating Supply Offset Voltage
3

Without Pin
4
VB2
High Side Floating Supply voltage 2
5
V,VS2
Output 2 - High Side Floating Supply Offset Voltage
6

Without Pin
7
VB3
High Side Floating Supply voltage 1
8
W,VS3
Output 1 - High Side Floating Supply Offset Voltage
9

Without Pin
10
P
Positive Bus Input Voltage
11

Without Pin
12
N
Positive Bus Input Voltage
13

Without Pin
14
HIN1
Logic Input High Side Gate Driver - Phase U
15
HIN2
Logic Input High Side Gate Driver - Phase V
16
HIN3
Logic Input High Side Gate Driver - Phase W
17
LIN1
Logic Input Low Side Gate Driver - Phase U
18
LIN2
Logic Input Low Side Gate Driver - Phase V
19
LIN3
Logic Input Low Side Gate Driver - Phase W
20
ISO
Current monitor output
21
VDD
+15V Main Supply
22
VSS
Negative Main Supply
No.A2350-4/15
STK581U3C2D-E
Equivalent Block Diagram
VB1(1)
U, VS1(2)
VB2(4)
V, VS2(5)
VB3(7)
W,VS3(8)
BD
BD
BD
U.V.
U.V.
U.V.
P(13)
Shunt Resistor
N(12)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1(13)
HIN2(14)
HIN3(15)
Logic
Logic
Logic
LIN1(16)
LIN2(17)
LIN3(18)
FAULT(19)
ISO(20)
(Protection)
VDD(21)
VSS(22)
Shut down
Thermistor
Latch time About 30ms
(Automatic reset)
VDD-Under Voltage
No.A2350-5/15
STK581U3C2D-E
Test Circuit
(The tested phase : U+ shows the upper side of the U phase and U shows the lower side of the U phase.)
■ ICE / IR(BD)
U+
V+
W+
U
V
W
M
10
10
10
2
5
8
N
2
5
8
12
12
12
U(BD)
V(BD)
W(BD)
M
1
4
7
N
22
22
22
Fig. 1
■ VCE(SAT) (Test by pulse)
M
U+
V+
W+
U
V
W
10
10
10
2
6
8
N
2
5
8
12
12
12
m
13
14
15
16
17
18
Fig. 2
■ VF (Test by pulse)
U+
V+
W+
U
V
W
M
10
10
10
2
5
8
N
2
5
8
12
12
12
Fig. 3
■ ID
VD1
VD2
VD3
VD4
M
1
4
7
21
N
2
5
8
22
Fig. 4
No.A2350-6/15
STK581U3C2D-E
■ ISD
Input signal
(0 to 5V)
Io
ISD
100μs
Fig. 5
■ Switching time (The circuit is a representative example of the lower side U phase.)
Input signal
(0 to 5V)
90%
Io
10%
tON
tOFF
Fig. 6
No.A2350-7/15
STK581U3C2D-E
Logic Timing Chart
VBS undervoltage protection reset signal
ON
HIN1,2,3
OFF
LIN1,2,3
*2
VDD
VDD undervoltage protection reset voltage
*3
VBS undervoltage protection reset voltage
VB1,2,3
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
-terminal
(BUS line)
Current
FAULT terminal
Voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(18ms to 80ms)
Fig. 7
Notes
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be
added externally.
*2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. When VDD rises the operation will
resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The
outputs return to normal operation immediately after the upper side gate voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 18 to
80ms after the over current condition is removed.
No.A2350-8/15
STK581U3C2D-E
Logic level table
P
INPUT
Ho
HIN1,2,3
(13,14,15)
LIN1,2,3
(16,17,18)
IC
Driver
U,V,W
(2,5,8)
OUTPUT
HIN
LIN
OCP
Ho
Lo
U, V, W
FAULT
H
L
OFF
H
L
P
OFF
L
H
OFF
L
H
N
OFF
L
L
OFF
L
L
High
Impedance
OFF
H
H
OFF
L
L
High
Impedance
OFF
X
X
ON
L
L
High
Impedance
ON
Lo
N
Fig. 8
Sample Application Circuit
Fig. 9
No.A2350-9/15
STK581U3C2D-E
Recommended Operating Conditions at Tc = 25C
Item
Symbol
Conditions
min
typ
max
Unit
V
Supply voltage
VCC
P to N
0
280
450
Pre-driver
supply voltage
VD1, 2, 3
VB1 to U, VB2 to V, VB3 to W
12.5
15
17.5
VD4
VDD to VSS *1
13.5
15
16.5
VIN(ON)
VIN(OFF)
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3
3.0
-
5.0
0
-
0.3
1
-
20
kHz
2
-
-
s
1
-
-
s
0.79
-
1.17
Nm
ON-state input voltage
OFF-state input voltage
PWM frequency
fPWM
Dead time
DT
Turn-off to turn-on
Allowable input pulse width
PWIN
ON and OFF
Tightening torque
‘M4’ type screw
V
V
*1 Pre-drive power supply (VD4=15±1.5V) must have the capacity of Io=20mA(DC), 0.5A(Peak).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Usage Precautions
1. This IPM includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is
generated; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47μF,
however this value needs to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a
resistor (about 20Ω) in series between each 3-phase upper side power supply terminals (VB1, 2, 3) and each bootstrap
capacitor.
When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply.
2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of
surge voltages. Recommended value of “CS” is in the range of 0.1 to 10μF.
3. “ISO” (pin20) is terminal for current monitor. When the pull-down resistor is used, please select it more than 5.6kΩ
4. “FAULT” (pin19) is open DRAIN output terminal (Active Low). Pull up resistor is recommended more than 5.6kΩ.
5. Inside the IPM, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and
TH terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should
be used. The temperature monitor example application is as follows, please refer the Fig.10, and Fig.11 below.
6. Pull down resistor of 33kΩ is provided internally at the signal input terminals. An external resistor of 2.2k to 3.3kΩ should be
added to reduce the influence of external wiring noise.
7. The over-current protection feature is not intended to protect in exceptional fault condition. An external fuse is recommended
for safety.
8. When input pulse width is less than 1.0μs, an output may not react to the pulse. (Both ON signal and OFF signal)
This data shows the example of the application circuit, does not guarantee a design as the mass production set.
No.A2350-10/15
STK581U3C2D-E
The characteristic of thermistor
Parameter
Symbol
Condition
Min
Typ.
Max
Unit
Resistance
R25
Tc = 25C
99
100
101
kΩ
Resistance
R100
Tc = 100C
B-Constant (25 to 50 C)
Temperature Range
B
5.12
5.38
5.66
kΩ
4165
4250
4335
K
40
-
+125
C
Fig. 10
Condition
Pull-up resistor = 39k
Pull-up voltage of TH = 5V
Fig. 11
No.A2350-11/15
STK581U3C2D-E
The characteristic of PWM switching frequency
Maximum sinusoidal phase current as function of switching frequency (VBUS=300V, Tc=100C)
Fig.12
Switching waveform
IGBT Turn-on. Typical turn-on waveform @Tc=100C, VBUS=400V
X (200ns/div)
VCE (100V/div)
Turn on
Io (10A/div)
Fig. 13
IGBT Turn-off. Typical turn-off waveform @Tc=100C, VBUS=400V
X (200ns/div)
Io (10A/div)
Turn off
VCE (100V/div)
Fig. 14
No.A2350-12/15
STK581U3C2D-E
CB capacitor value calculation for bootstrap circuit
Calculate condition
Item
Upper side power supply.
Total gate charge of output power IGBT at 15V.
Symbol
Value
Unit
VBS
15
V
Qg
266
nC
Upper side power supply low voltage protection.
UVLO
12
V
Upper side power dissipation.
IDmax
400
μA
Tonmax
-
s
ON time required for CB voltage to fall from 15V to UVLO
Capacitance calculation formula
CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Tonmax) of the upper
side is calculated as follows:
VBS * CB – Qg – IDmax * Tonmax = UVLO * CB
CB = (Qg + IDmax * Tonmax) / (VBS – UVLO)
The relationship between Tonmax and CB becomes as follows. CB is recommended to be approximately 3 times the value
calculated above. The recommended value of CB is in the range of 1 to 47μF, however, the value needs to be verified prior to
production.
Tonmax-CB characteristic
Fig 15
No.A2350-13/15
STK581U3C2D-E
Package Dimensions
unit : mm
SIP22 70x31.1
CASE 127BU
ISSUE O
Missing pin : 3, 6, 9, 11
70
4.6
6
2.5
(16)
31.1
2 R 2.3
22
2.54
0.75
0.5
1
0.5
8C F 00
21 x 2.54 = 53.34
12.5
3.5 ±0.4
2 2
58
78
No.A2350-14/15
STK581U3C2D-E
ORDERING INFORMATION
Device
STK581U3C2D-E
Package
SIP22 70x31.1
(Pb-Free)
Shipping (Qty / Packing)
7 / Tube
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PS No.A2350-15/15
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