ENA2228 D

Ordering number : EN*A2228A
STK5F1U3E2D-E
Advance Information
Thick-Film Hybrid IC
http://onsemi.com
Inverter Power IPM
for 3-phase Motor Drive
Overview
This “Inverter Power IPM” is highly integrated device containing all High Voltage (HV) control from HV-DC to
3-phase outputs in a single DIP module (Dual-In line Package). Output stage uses IGBT/FRD technology and
implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag.
Internal Boost diodes are provided for high side gate boost drive.
Function
 Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit
 All control input and status output are at low voltage levels directly compatible with microcontrollers
 Cross conduction prevention
 Externally accessible embedded thermistor for substrate temperature measurement
 The level of the over-current protection current is adjustable with the external resistor, “RSD”
Certification
 UL1557 (File Number: E339285)
Specifications
Absolute Maximum Ratings at Tc = 25C
Ratings
Unit
Supply voltage
Parameter
Symbol
VCC
P to N, surge < 500V *1
450
V
Collector-emitter voltage
VCE
P to U, V, W or U, V, W to N
P, N, U, V, W terminal current
600
±50
±25
±76
V
Output current
Io
Output peak current
Iop
Pre-driver supply voltage
Input signal voltage
FAULT terminal voltage
Maximum loss
VD1, 2, 3, 4
VIN
VFAULT
Pd
Junction temperature
Tj
Storage temperature
Tstg
Operating temperature
Tightening torque
Withstand voltage
Tc
MT
Vis
Remarks
P, N, U, V, W terminal current, Tc=100C
P, N, U, V, W terminal current, PW=1ms
VB1 to VS1, VB2 to VS2, VB3 to VS3, VDD to VSS *2
A
A
20
V
HIN1, 2, 3, LIN1, 2, 3
0.3 to VDD
V
FAULT terminal
IGBT per channel
0.3 to VDD
67.5
V
W
IGBT,FRD
IPM case
A screw part at use M4 type screw *3
50Hz sine wave AC 1 minute *4
150
C
40 to +125
C
20 to +100
1.17
2000
C
Nm
VRMS
Reference voltage is N terminal = VSS terminal voltage unless otherwise specified.
*1: Surge voltage developed by the switching operation due to the wiring inductance between the P and N terminals.
*2: Terminal voltage: VD1=VB1VS1, VD2=VB2VS2, VD3=VB3VS3, VD4=VDDVSS.
*3: Flatness of the heat-sink should be 0.25mm and below.
*4: Test conditions: AC 2500V, 1 second.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
Semiconductor Components Industries, LLC, 2014
July, 2014 Ver.140520DS
71114HK/O0913HK No.A2228-1/15
STK5F1U3E2D-E
Electrical Characteristics at Tc  25C, VD1, VD2, VD3, VD4=15V
Parameter
Symbol
Conditions
Ratings
Test
circuit
Min.
Typ.
Max.
Unit
Power output section
Collector to emitter cut-off current
Bootstrap diode reverse current
Collector to emitter saturation
voltage
ICE
IR(BD)
VCE=600V
VR(BD)=600V
Ic=50A
VCE(sat)
Junction to case thermal resistance
VF
-
-
100
μA
-
-
100
μA
Upper side
-
1.7
2.6
Lower side
-
2.3
3.2
-
1.35
-
-
1.75
-
Ic=25A,
Upper side
Tj=100C
Lower side
IF=50A
Diode forward voltage
Fig.1
Fig.2
Upper side
-
1.8
2.7
Lower side
-
2.4
3.3
-
1.45
-
-
1.85
-
IF=25A,
Upper side
Tj=100C
Lower side
Fig.3
V
V
θj-c(T)
IGBT
-
-
1.5
-
C/W
θj-c(D)
FWD
-
-
1.8
-
C/W
-
0.05
0.4
-
1.0
4.0
Control (Pre-driver) section
Pre-drive power supply consumption
current
ID
VD1,2,3=15V
VD4=15V
Fig.4
mA
High level input voltage
Vin H
HIN1,HIN2,HIN3,
-
2.5
-
-
V
Low level input voltage
Vin L
LIN1,LIN2,LIN3 to VSS
-
-
-
0.8
V
Logic 1 input leakage current
IIN+
VIN=+3.3V
100
195
μA
Logic 0 input leakage current
IIN-
VIN=0V
1
μA
ISD
PW=100μs,RSD=0Ω
Protection section
Over-current protection electric
current
Vdd and VBx supply undervoltage
VddUV+
positive going input threshold
VBxUV+
Vdd and VBx supply undervoltage
VddUV-
negative going input threshold
VBxUV-
Fig.5
57
-
76
A
10.6
11.1
11.6
V
10.4
10.9
11.4
V
Vdd and VBx supply undervoltage
VddUVH
Ilockout hysteresis
VBxUVH
FAULT terminal input electric current
IOSD
VFAULT=0.1V
-
1
1.5
-
mA
FAULT clearance delay time
FLTCLR
From time fault condition clear
-
18
-
80
ms
Rt
Resistance between the TH(18)
and VSS(20) terminals
-
90
-
110
kΩ
-
0.7
1.5
μs
-
1.1
2.1
μs
Thermistor for substrate temperature
monitor
0.2
V
Switching character
Switching time
tON
tOFF
Io=50A, Inductive load
Turn-on switching loss
Eon
Turn-off switching loss
Eoff
-
1100
-
μJ
-
1220
-
μJ
Total switching loss
Etot
Turn-on switching loss
Eon
Io=25A, VCC=300V,
-
2320
-
μJ
-
620
-
Turn-off switching loss
Eoff
μJ
VD=15V, L=280μH,
-
790
-
μJ
Total switching loss
Etot
Tc=100C
Io=25A, VCC=300V,
Diode reverse recovery energy
Erec
-
1410
-
μJ
-
27
-
μJ
-
80
-
ns
Io=50A, VCC=300V,
VD=15V, L=280μH
Fig.6
VD=15V, L=280μH,
Diode reverse recovery time
Trr
Reverse bias safe operating area
RBSOA
Tc=100C
Io = 76A, VCE= 450V
Short circuit safe operating area
SCSOA
VCE = 400V, Tc=100C
Electric current output signal level
ISO
Io=50A
Full square
4
-
0.427
μs
0.45
0.474
V
Reference voltage is N terminal = VSS terminal voltage unless otherwise specified.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2228-2/15
STK5F1U3E2D-E
Notes
1. When the internal protection circuit operates, a Fault signal is turned ON (When the Fault terminal is low level,
Fault signal is ON state : output form is open DRAIN) but the Fault signal does not latch.After protection
operation ends,it returns automatically within about 18ms to 80ms and resumes operation beginning condition. So,
after Fault signal detection, set all input signals to OFF (Low) at once.However, the operation of pre-drive power
supply low voltage protection (UVLO:with hysteresis about 0.2V) is as follows.
Upper side:
The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch
will continue till the input signal will turn ‘low’.
Lower side:
The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input
signal voltage.
2. When assembling the IPM on the heat sink with M4 type screw, tightening torque range is 0.79 Nm to 1.17 Nm.
3. The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to
an operating malfunction.
Pin Assignment
Pin No.
Name
Description
Pin No.
Name
Description
1
VB1
High side floating supply voltage 1
44
P
Positive bus input voltage
2
VS1
High side floating supply offset voltage
43
P
Positive bus input voltage
3
-
Without pin
42
P
Positive bus input voltage
4
VB2
High side floating supply voltage 2
41
-
Without pin
5
VS2
High side floating supply offset voltage
40
N
Negative bus input voltage
6
-
Without pin
39
N
Negative bus input voltage
7
VB3
High side floating supply voltage 3
38
N
Negative bus input voltage
8
VS3
High side floating supply offset voltage
37
-
Without pin
9
-
Without pin
36
U
U-phase output
10
HIN1
Logic input high side driver-Phase1
35
U
U-phase output
11
HIN2
Logic input high side driver-Phase2
34
U
U-phase output
12
HIN3
Logic input high side driver-Phase3
33
-
Without pin
13
LIN1
Logic input low side driver-Phase1
32
V
V-phase output
14
LIN2
Logic input low side driver-Phase2
31
V
V-phase output
15
LIN3
Logic input low side driver-Phase3
30
V
V-phase output
16
FAULT
Fault out (open drain)
29
-
Without pin
17
ISO
Current monitor pin
28
W
W-phase output
18
TH
Thermistor out
27
W
W-phase output
19
VDD
+15V main supply
26
W
W-phase output
20
VSS
Negative main supply
25
-
Without pin
21
ISD
Over-current protection level setting pin
24
NC
-
22
NC
-
23
NC
-
No.A2228-3/15
STK5F1U3E2D-E
Block Diagram
NC(23,24)
U(34,35,36)
V(30,31,32)
W(26,27,28)
VB1(1)
VS1(2)
VB2(4)
VS2(5)
VB3(7)
VS3(8)
P
(42,43,44)
DB
DB DB
U.V.
U.V.
U.V.
RB
N
(38,39,40)
Shunt-Resistor
ISO(17)
Thermistor
TH(18)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1(10)
HIN2(11)
HIN3(12)
Logic
Logic
Logic
LIN1(13)
LIN2(14)
LIN3(15)
Shutdown
VDD(19)
Q
-
Detect
VSS(20)
S
+
Under voltage
Timer
R
Vref
Latch time about 18 to 80ms
ISD(21)
FAULT(16)
NC(22)
No.A2228-4/15
STK5F1U3E2D-E
Test Circuit
(The tested phase: U+ shows the upper side of the U phase and U- shows the lower side of the U phase.)
 ICE / IR(BD)
M
N
U+
42
34
V+
42
30
W+
42
26
M
N
U(BD)
1
20
V(BD)
4
20
W(BD)
7
20
U34
38
V30
38
W26
38
ICE
1
M
A
VD1=15V
2
4
VD2=15V
5
VCE
7
VD3=15V
8
19
VD4=15V
20
N
Fig.1
 VCE(SAT) (Test by pulse)
M
N
m
U+
42
34
10
V+
42
30
11
W+
42
26
12
U34
17
13
V30
19
14
W26
21
15
1
M
VD1=15V
2
4
VD2=15V
5
V
Ic
7
VD3=15V
VCE(SAT)
8
19
VD4=15V
5V
m
20
21
Fig.2
 VF (Test by pulse)
M
N
U+
42
34
V+
42
30
N
W+
42
26
U34
38
V30
38
W26
38
M
V
VF
IF
N
Fig.3
 ID
M
N
VD1
1
2
VD2
4
5
VD3
7
8
VD4
19
20
ID
A
M
VD*
N
Fig.4
No.A2228-5/15
STK5F1U3E2D-E
ISD
VD1=15V
Input signal
(0 to 5V)
VD2=15V
1
34
2
4
5
Io
7
ISD
Io
VD3=15V
8
19
VD4=15V
100μs
Input signal
13
20
38
21
Fig.5
Switching time (The circuit is a representative example of the lower side U phase.)
42
1
Input signal
(0 to 5V)
VD1=15V
2
4
VD2=15V
5
34
90%
Vcc
7
Io
VD3=15V
10%
tON
tOFF
CS
8
19
Io
VD4=15V
Input signal
13
20
38
21
Fig.6
 RB-SOA (The circuit is a representative example of the lower side U phase.)
Input signal
(0 to 5V)
42
1
VD1=15V
2
4
VD2=15V
Io
5
34
Vcc
7
VD3=15V
CS
8
19
Io
VD4=15V
Input signal
13
20
38
21
Fig.7
No.A2228-6/15
STK5F1U3E2D-E
Logic Timing Chart
VBS undervoltage protection reset signal
ON
HIN1,2,3
OFF
LIN1,2,3
*2
VDD
VDD undervoltage protection reset voltage
*3
VBS undervoltage protection reset voltage
VB1,2,3
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
ITRIP-terminal
(BUS line)
Current
FAULT terminal
Voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(18ms to 80ms)
Fig. 8
Notes
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be
added externally.
*2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. part. When VDD rises the operation
will resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The
outputs return to normal operation immediately after the upper side gat voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 18 to
80ms after the over current condition is removed.
No.A2228-7/15
STK5F1U3E2D-E
Logic level table
P(42,43,44)
FAULT*
Ho
HIN1,2,3
(10,11,12)
LIN1,2,3
(13,14,15)
IC
Driver
Lo
Fig.9
U,V,W
(34,35,36)
(30,31,32)
(26,27,28)
HIN1,2,3
LIN1,2,3
U,V,W
1
1
0
Vbus
1
0
1
0
1
0
0
Off
1
1
1
Off
0
X
X
Off
*With pulled-up registor
N(38,38,40)
No.A2228-8/15
STK5F1U3E2D-E
Application Circuit Example
CB
+
P 44
43
42
1 VB1
2 VS1
CB
+
4 VB2
5 VS2
N
CB
+5.0V
+
RFault
+
CI
-
U 36
35
34
10 HIN1
11 HIN2
Control
Circuit
V 32
31
30
12 HIN3
13 LIN1
W 28
27
26
14 LIN2
15 LIN3
16 FAULT
17 ISO
18 TH
NC
24
23
Rpd
CD
Missing pin
3, 6, 9, 25, 29, 33, 37, 41
CS
7 VB3
8 VS3
RTH
VDD=15V
40
39
38
Vcc
+
RSD
19 VDD
20 VSS1
21 ISD
22 NC
Fig.10
No.A2228-9/15
STK5F1U3E2D-E
Recommended Operating Conditions at Tc = 25C
Parameter
Supply voltage
Pre-driver supply voltage
Symbol
VCC
VD1, 2, 3
VD4
Input ON voltage
VIN(ON)
Input OFF voltage
VIN(OFF)
PWM frequency
Dead time
Allowable input pulse width
Tightening torque
Conditions
P to N
DT
MT
Typ
Max
0
280
450
Unit
V
VB1 to VS1, VB2 to VS2, VB3 to VS3
12.5
15
17.5
VDD to VSS *1
13.5
15
16.5
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3
3.0
-
VDD
0
-
0.8
1
-
20
kHz
fPWM
PWIN
Ratings
Min
V
V
Turn-off to turn-on (external)
2
-
-
μs
ON pulse width/OFF pulse width
1
-
-
μs
0.79
-
1.17
Nm
‘M4’ type screw
*1 Pre-driver power supply (VD4=15±1.5V) must have the capacity of Io=20mA (DC), 0.5A (Peak).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Usage Precautions
1. This IPM includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is generated;
each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47μF, however this
value needs to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a resistor (about
20Ω) in series between each 3-phase upper side power supply terminals (VB1,2,3) and each bootstrap capacitor.
When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply.
2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of
surge voltages. Recommended value of “CS” is in the range of 0.1 to 10μF.
3. “ISO” (pin17) is terminal for current monitor. When the pull-down resistor is used, please select it more than 5.6kΩ.
4. “FAULT” (pin16) is open DRAIN output terminal. (Active Low). Pull up resistor is recommended more than 5.6kΩ.
5.
Inside the IPM, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and TH
terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be
used. The temperature monitor example application is as follows, please refer the Fig.11, and Fig.12 below.
6. The pull down resistor of 33kΩ is provided internally at the signal input terminals. An external resistor of 2.2k to 3.3kΩ should
be added to reduce the influence of external wiring noise.
7. The over-current protection feature is not intended to protect in exceptional fault condition. An external fuse is recommended
for safety.
8. When “N” and “VSS” terminal are short-circuited on the outside, level that over-current protection (ISD) might be changed
from designed value as IPM. Please check it in your set (“N” terminal and “VSS” terminal are connected in IPM).
9. The over-current protection function operates normally when an external resistor RSD is connected between ISD and VSS
terminals. Be sure to connect this resistor. The level of the overcurrent protection can be changed according to the RSD value.
10. When input pulse width is less than 1.0μs, an output may not react to the pulse. (Both ON signal and OFF signal)
This data shows the example of the application circuit, does not guarantee a design as the mass production set.
No.A2228-10/15
STK5F1U3E2D-E
The characteristic of thermistor
Parameter
Resistance
Resistance
B-Constant(25-50C)
Temperature Range
Symbol
R25
R100
B
Condition
Tc=25C
Tc=100C
Min
97
4.93
4165
-40
Typ.
100
5.38
4250
Max
103
5.88
4335
+125
Unit
kΩ
kΩ
K
C
Fig.11 Variation of thermistor resistance with temperature
Condition
Pull-up resistor = 39kohm +/-1%
Pull-up voltage of TH = 5V +/-0.3V
Fig.12 Variation of temperature sense voltage with thermistor temperature
No.A2228-11/15
STK5F1U3E2D-E
Maximum Phase current
Motor Current vs. Frequency
(Sine wave oparation,Vcc=300V,cosθ=0.8,ON Duty=96%)
Phase Current : Io (A rms)
50
40
30
20
10
0
0
5
10
Switching Frequency : fc (KHz)
15
20
Fig.13 Maximum sinusoidal phase current as function of switching frequency
at Tc=100C, Vcc=300V
Switching waveform
Turn on
Fig. 14 IGBT Turn-on. Typical turn-on waveform at Tc=100C, VCC=300V, Ic=25A
Turn off
Fig. 15 IGBT Turn-off. Typical turn-off waveform Tc=100C, VCC=300V, Ic=25A
No.A2228-12/15
STK5F1U3E2D-E
CB capacitor value calculation for bootstrap circuit
Calculate condition
Item
Upper side power supply
Total gate charge of output power IGBT at 15V.
Upper side power supply low voltage protection.
Upper side power dissipation.
ON time required for CB voltage to fall from 15V to UVLO
Symbol
VBS
Qg
UVLO
IDmax
Ton-max
Value
15
0.47
12
400
-
Unit
V
μC
V
μA
s
Capacitance calculation formula
CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Ton-max) of the upper side is calculated as
follows:
VBS * CB – Qg – IDmax * Ton-max = UVLO * CB
CB = (Qg + IDmax * Ton-max) / (VD – UVLO)
Bootstrap Capacitance Cb (uF)
The relationship between Ton-max and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated above. The
recommended value of CB is in the range of 1 to 47μF, however, the value needs to be verified prior to production.
Cb vs ton max
100
10
1
0.1
0.01
0.1
1
10
100
1000
ton max (ms)
Fig.16 Ton-max vs CB characteristic
No.A2228-13/15
STK5F1U3E2D-E
Package Dimensions
unit : mm
HYBRID INTEGRATED MODULE
CASE MODAW
ISSUE O
4.6
6.0
44
(68.0)
63.4
0.75
1
2.54
23
76.0
21 x 2.54 = 53.34
22
+ 0.2
0.05
R 2.3
3.2
8.0
45.0
+ 0.2
0.5 0.05
10.8
49.7
No.A2228-14/15
STK5F1U3E2D-E
ORDERING INFORMATION
Device
STK5F1U3E2D-E
Package
610AC-DIP4-UL
(Pb-Free)
Shipping (Qty / Packing)
6 / Fan-Fold
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sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
PS No.A2228-15/15
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