LV8726TA D

LV8726TA
Stepper Motor Pre-Driver, PWM,
Constant-Current Control, Micro step
Overview
The LV8726 is a bipolar stepper motor driver with ultra-small micro step drive
capability. The device uses external dual H-bridges consisting of P and N
channel MOSFETs. The operation voltage range is from 9V to 55V, and it is
applicable to various industrial applications. Synchronous rectification control
is implemented for all H-bridges to minimize power dissipation during a
MOSFET switching.
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The device implements constant-current control using PWM. The step advance
sequencer covers from half step to 1/128 micro step, and is driven by a clock
input.
The configuration registers can be programmed through an SPI serial interface.
To enhance energy efficiency further, the device can be put into a power saving
standby mode.
48-pin TQFP with exposed pad
7 mm x 7 mm
MARKING DIAGRAM
Features
 H-bridge gate drivers
o For bipolar stepper motor
o Clockwise(CW) and Counter-clockwise(CCW) direction control
o Built-in step vector, selectable number of step resolutions from 2, 3, 4,
5, 6, 8, 10, 12, 16, 20, 32, 36, 50, 64, 100 and 128
o Constant-current control
o Synchronous rectification to reduce power dissipation
 Single clock input to advance the excitation step
 Low power 1μA(max) standby mode
 Separate power supplies for control logic (3.3-5V) and motor drivers ( 9V –
55V)
 SPI 8-bit 3-wire serial interface for system configuration
 Input pins for standby and active mode
 Built-in system protection features such as:
o Under-voltage
o Over-current
o Over-temperature
Typical Applications
 Textile machines
 Packing machines
 Large printers
 Engraving machines
 Industrial products
© Semiconductor Components Industries, LLC, 2015
October 2015- Rev. 0
XXXXXXXXXX
XXXXXXXXXX
AWLYYWWG
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Ordering Code:
LV8726TA-NH
Package
TQFP48 EP
(Pb-Free / Halogen Free)
Shipping (Qty / packing)
1000 / Tape & Reel
† For information on tape and reel specifications, including part
orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D.
http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
1
Publication Order Number:
LV8726TA/D
LV8726TA
BLOCK DIAGRAM
Figure 1. Block Diagram
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2
LV8726TA
APPLICATION CIRCUIT EXAMPLE
M
* Optional diodes and damping resistors for each gate are connected
to control turn OFF time of P-N channel MOSFETS, if needed.
48V
0Ω
100uF
TR1
TR3
SFT1342
0Ω
0Ω
SFT1342
0Ω
TR7
TR5
SFT1342
SFT1342
PGND
100Ω
TR4
TR2
SFT1446
100Ω
100Ω
SFT1446
SFT1446
SFT1446
0.1Ω
0.1Ω
100uF
GB4 37
GB3 38
NC 39
GU4 40
GU3 41
NC 42
NC 43
GB2 44
GB1 45
NC 46
GU2 47
PGND
1
NC
2
NC
3
OUT2
OUT4 34
4
OUT1
OUT3 33
5
RF1
RF2 32
6
NC
NC 31
7
VM
GND 30
8
VREG2
9
NC
NC 28
10 NC
NC 27
NC 35
0.1uF
VREG1 29
SGND
SCLK
SDATA
STB
STEP
RST
OE
FR
VREF
SDO
MO
14
15
16
17
18
19
20
21
22
23
47KΩ
12 NC
24 EMO
ST
NC 26
13
11 NC
PGND
NC 36
VCC 25
47KΩ
0.1uF
GU1 48
PGND
0.1uF
100Ω
TR8
TR6
1uF
Serial Input
Logic Input
Figure 2. Application Circuit Example
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3
5V
SGND
LV8726TA
37 GB4
38 GB3
39 NC
40 GU4
41 GU3
42 NC
43 NC
44 GB2
45 GB1
46 NC
47 GU2
48 GU1
PIN ASSIGNMENT
VM
7
30
GND
VREG2
8
29
VREG1
NC
9
28
NC
NC 10
27
NC
NC 11
26
NC
NC 12
25
24
NC
EMO
31
23
6
MO
NC
22
RF2
SDO
32
21
5
VREF
RF1
20
OUT3
FR
33
19
4
OE
OUT1
18
OUT4
RST
34
17
3
STEP
OUT2
16
NC
STB
35
15
2
SDATA
NC
14
NC
SCLK
36
13
1
ST
NC
Figure 3. Pin Assignment
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4
VCC
LV8726TA
PIN FUNCTION DISCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin Name
NC
NC
OUT2
OUT1
RF1
NC
VM
VREG2
NC
NC
NC
NC
ST
SCLK
SDATA
STB
STEP
RST
OE
FR
VREF
SDO
MO
EMO
VCC
NC
NC
NC
VREG1
GND
NC
RF2
OUT3
OUT4
NC
NC
GB4
GB3
NC
GU4
GU3
NC
NC
GB2
GB1
NC
GU2
GU1
Description
No connection
No connection
OUT2 voltage detection pin
OUT1 voltage detection pin
Channel 1 Output current detection pin
No connection
Motor power supply pin
Internal regulator capacitor connection pin for high side FET drive
No connection
No connection
No connection
No connection
Chip enable pin.
Serial data transfer clock input
Serial data input
Serial data latch pulse input
Step clock signal input pin
Reset signal input pin
Output enable signal input pin
Direction control signal input pin
Constant-current control reference voltage input pin.
STEP detection output pin
Position detecting monitor pin
Unusual condition warning output pins
Logic power supply pin
No connection
No connection
No connection
Internal regulator capacitor connection pin for low side FET drive
GND pin
No connection
Channel 2 Output current detection pin
OUT3 voltage detection pin
OUT4 voltage detection pin
No connection
No connection
Output terminal for low side gate drive 4
Output terminal for low side gate drive 3
No connection
Output terminal for high side gate drive 4
Output terminal for high side gate drive 3
No connection
No connection
Output terminal for low side gate drive 2
Output terminal for low side gate drive 1
No connection
Output terminal for high side gate drive 2
Output terminal for high side gate drive 1
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LV8726TA
PIN EQUIVALENT CIRCUITS
Pin No.
13
Pin Name
Equivalent Circuit
ST
GND
14
SCLK
15
SDATA
16
STB
17
STEP
18
RST
19
OE
20
FR
VCC
10kΩ
100kΩ
GND
21
VREF
VCC
500Ω
GND
Continued on next page.
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6
LV8726TA
Continued from preceding page.
Pin No.
Pin Name
SDO
23
MO
24
EMO
29
VREG1
200kΩ
22
Equivalent Circuit
VM
2kΩ
142kΩ
20kΩ
GND
8
VREG2
VM
100kΩ
102kΩ
2kΩ
GND
Continued on next page.
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7
LV8726TA
Continued from preceding page.
Pin No.
Pin Name
5
RF1
32
RF2
Equivalent Circuit
VCC
500Ω
GND
40
GU4
41
GU3
47
GU2
48
GU1
37
GB4
38
GB3
44
GB2
45
GB1
3
OUT2
4
OUT1
33
OUT3
34
OUT4
VM
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8
60KΩ
60KΩ
GND
LV8726TA
MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
Unit
Motor Supply Voltage (VM)
VM
60
V
Logic Supply Voltage (VCC)
VCC
6
V
Logic Input Voltage (ST, SCLK, SDATA, STB, STEP, RST, OE, FR)
VIN
6
V
IO
50
mA
Output current (GU1, GU2, GU3, GU4, GB1, GB2, GB3, GB4)
VREF
6
C
Pd
3.35
W
Storage Temperature
Tstg
55 to 150
ºC
Junction Temperature
TJ
150
ºC
Moisture Sensitivity Level (MSL) (Note 3)
MSL
3
-
Lead Temperature Soldering Pb-Free Versions (10sec or less) (Note 4)
TSLD
260
ºC
ESDHBM
±2000
V
Reference input voltage (VREF)
Allowable Power Dissipation (Note 2)
ESD Human Body Model: HBM (Note 5)
ESDCDM
ESD Charged Device Model: CDM (Note 6)
±500
V
1. Stresses exceeding those listed in the Absolute Maximum Rating table may damage the device. If any of these limits are exceeded,
device functionality should not be assumed, damage may occur and reliability may be affected.
2. Specified circuit board: 90mm 90mm 1.6mm, glass epoxy 2-layer board, with backside mounting. It has 1 oz copper traces on top and
bottom of the board.
3. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC standard: J-STD-020A
4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
http://www.onsemi.com/pub_link/Collateral/SOLDERRM-D.PDF
5. ESD Human Body Model is based on JEDEC standard: JESD22-A114
6. ESD Charge Device Model is based on JEDEC standard: JESD22-C101
THERMAL CHARACTERISTICS
Parameter
Symbol
Thermal Resistance, Junction-to-Ambient (Note 2)
RθJA
Thermal Resistance, Junction-to-Ambient (Note 7)
Thermal Resistance, Junction-to-Case (Top) (Note 2)
RΨJT
Thermal Resistance, Junction-to-Case (Top) (Note 7)
Unit
37.3
ºC/W
56.8
ºC/W
4.8
ºC/W
14.9
ºC/W
Specified circuit board: 90mm 90mm1.6mm, glass epoxy 2-layer board, without backside mounting. It has 1 oz copper traces on top
and bottom of the board.
Allowable power dissipation, Pdmax - W
7.
Value
4.00
3.50
3.35
3.00
2-layer circuit board
with backside mounting
2.50
2.00
2.20
2-layer circuit board
with no backside mounting
1.74
1.50
1.10
1.00
0.50
0.00
-20
0
20
40
60
80
Ambient temperature, Ta - C
Figure 4. Power Dissipation vs Ambient Temperature Characteristic
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9
100
LV8726TA
RECOMMENDED OPERATING RANGES (Note 8)
Parameter
Symbol
Ratings
Unit
Motor Supply Voltage Range (VM)
VM
9 to 55
V
Logic Supply Voltage Range (VCC)
VCC
2.7 to 5.5
V
Logic Input Voltage Range (ST, SCLK, SDATA, STB, STEP, RST, OE, FR)
VIN
0 to VCC
V
0 to 2.0
V
VREF Input Voltage Range (3.8V≤ VCC ≤5.5V)
VREF
VREF Input Voltage Range (2.7V≤ VCC ≤3.8V)
V
40 to 85
ºC
TA
Ambient Temperature
8.
0 to VCC – 1.8
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
TA=25ºC, VM = 48V, VCC=5V, VREF=1.5V unless otherwise noted. (Note 9)
Symbol
Parameter
Condition
Max
Unit
IMstn
ST=”L”, No load
1
μA
ICCstn
ST=”L”, No load
1
μA
IM
ST=”H”, OE=”L”,RST=”L”, No load
1.6
2.3
mA
ICC
ST=”H”, OE=”L”,RST=”L”, No load
1.7
2.3
mA
Thermal Shutdown Temperature
TSD
Guaranteed by design
180
210
˚C
Thermal hysteresis
∆TSD
Guaranteed by design
Standby Mode Current
Supply Current
Min
150
Typ
40
˚C
Under-voltage Monitor
VCC under-voltage threshold
VM under-voltage threshold
Vthvc
VCC falling
2.3
2.45
V
Vrevc
VCC rising
2.5
2.7
V
Vthvm
VM falling
7.6
8.4
V
Vrevm
VM rising
7.85
8.7
V
Regulator
REG10 Output Voltage
VREG1
9.4
10
10.6
V
VM-10V Output Voltage
VREG2
37
38
39
V
20
32
Ω
25
40
Ω
20
32
Ω
25
40
Ω
4
8
12
μA
30
50
70
μA
2.0
5.5
V
0
0.8
V
MOSFET Drivers
High Side Output On Resistance
Low Side Output On Resistance
RonH1
RonH2
RonL1
RonL2
GU1,GU2,GU3,GU4-source
Io=-10mA
GU1,GU2,GU3,GU4-sink
Io=10mA
GB1,GB2,GB3,GB4-source side
Io=-10mA
GB1,GB2,GB3,GB4-sink side
Io=10mA
Logic Inputs
IINL
Logic Input Current
IINH
Logic Input Voltage
High
VINH
Low
VINL
ST,SCLK,SDATA,STB,STEP,RST,OE,FR
VIN=0.8V
ST,SCLK,SDATA,STB,STEP,RST,OE,FR
VIN=5V
ST,SCLK,SDATA,STB,STEP,RST,OE,FR
System Monitoring
Step signal OFF detection time
TSDO0
TSDO1
No rising edge in STEP pin
Register D[7]=’0’, D[1:0]=’01’
No rising edge in STEP pin
Register D[7]=’1’, D[1:0]=’01’
0.39
0.52
0.65
S
0.78
1.04
1.3
S
Continued on next page.
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10
LV8726TA
Continued from preceding page.
Parameter
Symbol
Condition
Min
Typ
Max
Unit
0
μA
PWM Current Control
VREF Pin Input Current
IREF
VREF=1.5V
0.5
VREF000 Register D[4:2]=’000’, D[1:0]=’01’
0.291
0.3
0.309
V
VREF001 Register D[4:2]=’001’, D[1:0]=’01’
0.261
0.27
0.279
V
VREF010 Register D[4:2]=’010’, D[1:0]=’01’
0.231
0.24
0.248
V
V
Current setting comparator threshold REF011 Register D[4:2]=’011’, D[1:0]=’01’
voltage
VREF100 Register D[4:2]=’100’, D[1:0]=’01’
0.201
0.21
0.218
V
0.172
0.18
0.188
V
VREF101 Register D[4:2]=’101’, D[1:0]=’01’
0.142
0.15
0.158
V
VREF110 Register D[4:2]=’110’, D[1:0]=’01’
0.112
0.12
0.128
V
VREF111 Register D[4:2]=’111’, D[1:0]=’01’
0.082
0.09
0.098
V
Fchop1
Register D[7:6]=’00’, D[1:0]=’10’
6
8
10
μs
Fchop2
Register D[7:6]=’01’, D[1:0]=’10’
12
16
20
μs
Fchop3
Register D[7:6]=’10’, D[1:0]=’10’
18
24
30
μs
Fchop4
Register D[7:6]=’11’, D[1:0]=’10’
24
32
40
μs
SDO pin saturation voltage
Vsatsdo
Isod=1mA
400
mV
MO pin saturation voltage
Vsatmo
Imo=1mA
400
mV
EMO pin saturation voltage
Vsatemo
Iemo=1mA
400
mV
PWM (Chopping) Period
Open Drain Outputs
Serial Data Interface (Note 10)
SCLK “H” Pulse Width
Tckh
0.125
μs
SCLK “L” Pulse Width
Tckl
0.125
μs
SCLK start setup time
Tsup1
STB=Low -> SCLK rising edge
0.125
μs
STB setup time
Tsup2
SCLK rising edge -> STB rising edge
0.125
μs
Serial Packet STB Interval
Tstbw
0.125
μs
SDATA setup time
Tds
0.125
μs
SDATA hold time
Tdh
0.125
μs
SCLK Frequency
Fclk
4
9.
MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10. See Figure 5 for the definition of the timing
Figure 5. Serial Interface (SPI) Timing Chart
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11
LV8726TA
TYPICAL CHARACTERISTICS
Standby mode current - VCC
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
ICCstn (uA)
IMstn (uA)
Standby mode current - VM
0.5
0
-0.1
0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-0.5
0
10
20
30
40
50
60
0
1
2
3
4
5
6
VCC (V)
VM (V)
Figure 6. Standby Mode Current
vs VM Voltage
Figure 7. Standby Mode Current
vs VCC Voltage
Current Consumption of VM
Logic Level Input Voltage (OE pin)
1.6
2
1.8
1.4
1.6
1.2
1.4
1.2
H-level (V)
IM (mA)
1
0.8
0.6
1
0.8
* Logic inputs are hysteresis type and
devide the thethreshold level at VCC rising 4V
0.6
0.4
0.4
0.2
0.2
0
2
2.5
3
3.5
0
0
10
20
30
40
50
4
4.5
5
5.5
6
VCC(V)
60
H-level
VM (V)
Figure 8. Current Consumption(IM)
vs VM Voltage
L-Level
Figure 9. Logic H/L-Level Input Voltage
(except ST pin) vs VCC Voltage
Input Threshold Voltage (ST pin against VCC)
Crrent Consumption of VCC
2
2.5
1.8
1.6
2
1.4
1.2
ICC (mA)
threshold voltage(V)
1.5
1
0.5
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
0
6
2
2.5
3
3.5
4
4.5
5
5.5
VCC(V)
VCC (V)
Figure 10. Current Consumption (ICC)
vs VCC Voltage
Figure 11. ST pin Input Threshold Voltage
vs VCC Voltage
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6
LV8726TA
TYPICAL CHARACTERISTICS (CONTINUED)
Logic pin input current (VM=48V VCC=6V)
STEP signal OFF detection time
VM=48V setting mode=1.04s
70
1.4
60
1.2
Step signal OFF detection time (s)
50
IIN (uA)
40
30
20
10
1
0.8
0.6
0.4
0.2
0
0
1
2
3
VIN (V)
4
5
6
0
ST
SCLK
SDATA
STB
STEP
RST
OE
FR
2
3
4
5
6
VCC (V)
Figure 13. STEP signal OFF detection time
vs VCC Voltage
Figure 12. Logic Input Current
vs Input Voltage
VCC Under Voltage Protection
Threshold Voltage
VM Under Voltage Protection
Threshold Voltage
12
9
8
10
7
6
8
VREG1 (V)
GB (V)
5
6
4
4
3
2
2
1
0
0
-1
-2
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
-2
3
7.5
7.6
7.7
7.8
7.9
8
VM (V)
VCC (V)
Figure 14. VCC Under-voltage Protection
Threshold Voltage vs VCC Voltage
Figure 15. VM Under-voltage Protection
Threshold Voltage vs VM Voltage
VREG1 load regulation
VM=48V VCC=5.0V
VREG2 load regulation
VM=48V VCC=5.0V
12
50
48
10
46
44
VREG2 (V)
VREG1 (V)
8
6
4
42
40
38
36
34
2
32
0
0
-20
-40
-60
-80
30
-100
0
Iload (mA)
10
20
30
40
50
60
Iload (mA)
Figure 16. VREG1 Output Voltage
vs VREG1 Load Current
Figure 17. VREG2 Output Voltage
vs VREG2 Load Current
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70
LV8726TA
TYPICAL CHARACTERISTICS (CONTINUED)
SDO pin Saturation Voltage
VM=48V VCC=5V
VREF input current
VM=48 VCC=5.0V
1.4
0
1.2
-5
Saturation voltage (V)
IREF (nA)
1
-10
-15
-20
0.8
0.6
0.4
0.2
0
0
-25
0
1
2
3
4
5
10
15
20
25
30
Load currrent (mA)
5
VREF (V)
Figure 18. VREF pin Input Current (IREF)
vs VREF Voltage
Figure 19. SDO pin Saturation Voltage
vs SDO Load current
MO pinl Saturation Voltage
VM=48V VCC=5V
EMO pin Saturation Voltage
VM=48V VCC=5V
1.4
1.2
1.2
1
Saturation voltage (V)
Saturation voltage (V)
1
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0
0
0
5
10
15
20
25
0
30
Chopping period
VM=48V VREF=1.5V setting mode=32us
45
40
35
30
25
20
15
10
5
0
3
4
10
15
20
25
30
Figure 21. EMO pin Saturation Voltage
vs EMO Load Current
Figure 20. MO pin Saturation Voltage
vs MO Load Current
2
5
Load current (mA)
Load current (mA)
Chopping period (us)
0.8
5
6
VCC (V)
Figure 22. PWM (Chopping) Period
vs VCC Voltage
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14
LV8726TA
FUNCTIONAL DESCRIPTION
Power Supply Input (VM, VCC)
Table 2: Operating Mode control by ST pin
The LV8726 has two power supply pins, VM and VCC.
VM is the motor power supply rail which is also
connected externally to the power MOSFETs. VCC
supplies power to internal circuits. It is highly
recommended to provide a decoupling capacitor of
100µF for each position close to the VM pin and VM
line of external MOSFETs on the application board.
Driver Pins (GUx, GBx and OUTx)
The pins GUx are the high side P-MOSFET gate driver
outputs, and GBx are the low side N-MOSFET gate
driver outputs. The pins OUTx are the voltage sense
inputs used for the over-current protection function to
measure the P-MOSFET voltage between drain and
source. The channel pairing is shown in the following
table.
ST
Operating mode
Internal regulator
L
Standby
Standby
H
Active
Active
Initialize Step Position Pin (RST)
While pin RST is set High, the home position is excited.
After RST is released (Low), the first rising edge of
STEP pulse advances the step. The position monitor
output (MO pin) indicates that the output state is in the
home position by outputting Low level.
RESET
RST
STEP
MO
Table 1: External MOSFETs Connection
Channel
1
2
P-MOS
gate
P-MOS
drain
N-MOS
gate
Motor coil
GU1
OUT1
GB1
1A
GU2
OUT2
GB2
1B
GU3
OUT3
GB3
2A
GU4
OUT4
GB4
2B
1ch output
0%
2ch output
Refer to the APPLICATION CIRCUIT EXAMPLE of
page 3.
Home position
Figure 23. Initialize Step Position (RST)
Internal Voltage Regulator for N-MOSFETs (VREG1)
This 10V regulator provides required biasing for low
side N-MOSFET gate drivers. The output of this
regulator is connected to pin VREG1. Do not use
VREG1 to drive any external load. It is recommended to
connect a 0.1µF decoupling capacitor between VREG1
pin and GND.
Output Enable Pin (OE)
While OE pin is High, the output power MOSFETs are
turned off. During the output disabled, the internal step
sequencer keeps operation, advancing the step position
based on the clock at STEP pin.
Internal Voltage Regulator for P-MOSFETs (VREG2)
This regulator provides required biasing for high side
P-MOSFET gate drivers at 10V below VM. The output
of this regulator is connected to pin VREG2. Do not use
VREG2 to drive any external load. It is recommended to
connect a 0.1µF decoupling capacitor between VREG2
and VM.
STEP
MO
1ch output
Standby Mode (ST)
When pin ST is pulled down to GND, the device enters
standby mode: all power MOSFETs are turned off, and,
all logic as well as the step counter are reset.
When ST pin is pulled to High, the device enters active
mode. The motor is excited at the home position. A
rising edge at the STEP pin will advance the motor
(which direction). Refer to Table 5 of page 16 for the
home position.
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15
Power save mod e
OE
0%
2ch output
Output is high-impeda nce
Figure 24. Example of Output Enable (OE)
LV8726TA
Summary of System Mode Control (ST, OE, RST)
The following table shows the summary of the system
mode control function with ST, OE and RST pins.
Table 3: System Mode Control
ST
OE
RST
Output
Step position
L
*
*
High
impedance
Home position
Rotational Direction Control Pin (FR)
FR controls the progression of the electrical angle of the
motor. When FR is Low, the direction is clockwise, and
when FR is High, direction is counter-clockwise.
Table 6: Direction Control by FR pin
H
H
H
High
impedance
H
H
L
High
impedance
Based on
STEP signal
H
L
H
Active
Home position
H
L
L
Active
Based on
STEP signal
FR
Operating mode
Low
Clockwise (CW)
High
Counter-clockwise (CCW)
Figure 25 shows an example of the direction change
with FR pin.
FR
CW mode
CCW mode
CW mode
STEP
Step Clock Signal Input Pin (STEP)
A rising edge of the step clock signal at STEP pin
advances the step position of the stepper motor by
advancing the electrical angle of the excitation current
for the motor coils. The number of steps for 90 degree of
an electrical cycle (i.e. resolution) is determined by the
register bits which are accessible through the serial
interface.
Excitation position
(1)
(2)
(3)
(4)
(5)
(6)
(5)
(4)
(3)
(4)
(5)
1ch output
2ch output
Table 4: Step Position Control by STEP pin
ST
STEP
Operating mode
L
*
Standby mode
H
Figure 25. Example of Direction Reversal
Advancing step position
Position Monitor Output Pin (MO)
H
step position is kept
Table 5: Micro Step Resolution Setting
Bit setting
(D1=0, D0=0)
The active low, open drain pin MO indicates the home
position of the motor. An example of pin MO waveform
is as shown Figure 44 and Figure 45 of page 33 and 34.
Home position
D5
D4
D3
D2
Micro step
resolution:
STEPMODE
0
0
0
0
1/2
100%
0%
0
0
0
1
1/4
100%
0%
0
0
1
0
1/8
100%
0%
0
0
1
1
1/16
100%
0%
0
1
0
0
1/32
100%
0%
0
1
0
1
1/64
100%
0%
0
1
1
0
1/128
100%
0%
0
1
1
1
1/3
100%
0%
1
0
0
0
1/6
100%
0%
1
0
0
1
1/12
100%
0%
1
0
1
0
1/36
100%
0%
1
0
1
1
1/5
100%
0%
1
1
0
0
1/10
100%
0%
1
1
0
1
1/20
100%
0%
1
1
1
0
1/50
100%
0%
1
1
1
1
1/100
100%
0%
1ch
current
2ch
Current
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16
LV8726TA
Current Control Setting (VREF, RF1, RF2)
PWM Constant-Current Control Ratio
The LV8726 implements a current sense mechanism for
each channel using external shunt resistors.
To control a coil current, a RFx pin is provided for each
channel. A resistor connected at this RFx pin defines the
current gain of the coil current.
The resistive voltage generated by the coil current is
sensed by the RFx pin and the output duty cycle is
adjusted so that the RFx voltage level is equal to the
internal reference voltage (Equation 1). The reference
voltage is determined by the input voltage level at
VREF pin and the programmable attenuator. For this
VREF pin, it is required to provide an external constant
voltage source circuit. Refer to RECOMMENDED
OPERATING RANGES of page 10 for VREF range.
The LV8726 implements constant current control drive
by applying a PWM to pins GUx and GBx.
When a coil current reaches the set target value, the
constant current control mechanism gets activated and
performs a repetitive sequence of Charge and Decay
operations as shown Figure 30-32 of page 22 and 23.
The target value is generated based on the step clock
pulse number. The angle of one step θ is
90° ∙ … … … 3 Where,
θ : Angle of micro step [deg]
S : Micro step (1/2, … 1/128)
The n-th current ratio can be represented by
Table 7: VREF Attenuation Ratio Setting
Bit setting
(D1=0, D0=1)
D4
D3
D2
VREF (Reference voltage)
attenuation ratio: VREFATT
%
The n-th current value can be represented by
0
0
0
100%
0
0
1
90%
0
1
0
80%
0
1
1
70%
1
0
0
60%
1
0
1
50%
1
1
0
40%
1
1
1
30%
……… 5
Where,
n : the position number of STEP from 0 to 1/S
The output current calculation method for using of
attenuation function of the VREF input voltage is as
shown in Equation 1.
Equation 2 is utilized to calculate the coil peak current,
IOUT.
∙
5
∙
5∙
∙
………… 1 ……… 2
For example, in case of
1/128
32
The θ32 is
32
Each current ratio is
32
32
For example, in case of
0.1 Ω]
1.5[V]
=1.0 (100%)
1.5 1.0
5 0.1
90° ∙
32
128
22.5°
22.5° ∙ 100
22.5° ∙ 100
92[%]
38[%]
Equation 4 represents the theoretical calculation. The
actual current ratio between the channel 1 and 2 is the
preset value as shown in Table 10-12 of page 28, 30 and
32. In case of 1/128 micro step case, the preset values
are plotted in Figure 41 of page 29. The current
waveforms for some micro step settings are illustrated
in Figure 44-1., Figure 45-1, Figure 46-1.
Where,
IOUT : Coil current [A]
RRFx : Resistor between RFx and GND [Ω]
VREF : Input voltage at the VREF pin [V]
ATTRATIO : Attenuator Ratio for the VREF pin
The coil current is
∙ 100 … … … 4
3.0 A
The LV8726 provides the built-in current vector
generator. The current ratio between channel 1 and 2
are preset based on cosine and sine element
individually.
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17
LV8726TA
Output Pin for STEP Input Monitoring (SDO)
Fault Detection Output (EMO)
The step clock signal at pin STEP is monitored by an
internal counter. When the interval time of the rising
edge is longer than timeout criteria, open drain pin SDO
goes Low. The timeout period is selectable by the
register bits shown in the following table. The example
of detection timing is illustrated in Figure 26.
When a fault event is detected, open drain pin EMO
goes Low. The fault event is selectable by register from
the following four conditions.
Table 9: Fault Detection Output Setting
Bit setting
(D1=0, D0=0)
Table 8: STEP Signal OFF Detection Time Setting
Bit setting
(D1=0, D0=1)
D7
STEP signal OFF detection time:
TSDO
0
0.52sec
1
1.04sec
Fault detection output:
EMOSEL
D7
D6
0
0
Over-current detection
0
1
None
1
0
VM low voltage < 7.6V (typ)
1
1
Thermal Shutdown
The all fault protection functions always work
regardless of the EMO output selection.
Serial Interface (ST, SDATA, SCLK, STB)
The LV8726 has registers to program settings and
parameters which are accessed through the serial
interface. It consists of the following three pins:
1.
Figure 26. Example of SDO Timing
2.
SDO Output for Current Reduction
To avoid to applying high current to a motor coil for
long term at one step position, the SDO output may be
used to reduce the reference current. SDO is asserted
when the step clock interval is longer than TSDO. With
the circuit is shown in Figure 27. VREF voltage can be
reduced in case of an SDO assertion.
V1
R1
VREF
R3
R2
SDO
3.
STB: When STB is Low, SDATA is input at
the rising edge of SCLK. SCLK signal is not
accepted when STB is High. The transmitted
data is latched at the rising edge of STB.
SDATA: LSB first 8-bit word. Its direction is
from external processor to the device. The
written data cannot be read back.
SCLK: Serial clock. The device fetches each
data bit at the rising edge of the clock.
The settings of ‘Micro step resolution’ and ‘Decay
mode’ are taking effect at the first rising edge of STEP
after a register write. Other settings are active
immediately after a register change.
When more than eight bits of data were received, the
latest eight bits are considered effective data. During
standby mode (ST=Low), the registers cannot be
accessed and all logic is reset.
ST
SDATA
D0
D1
D2
D3
D4
D5
D6
D7
SCLK
Figure 27. VREF Voltage Attenuation Circuit
STB
Data latch timing
Figure 28. Serial Interface Timing Chart
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18
LV8726TA
Register Map
The following Figure shows the register map. The two lowest bits are assigned for selecting one of four addresses.
D7
D6
D5
EMOSEL
TSDO
DECAY
TPWM
NA
NA
NA
TOFF
D4
D3
D2
STEPMODE
VREFATT
TBLANK
NA
OCM
OCE
D1
D0
ADDR1
ADDR0
ADDR D[1:0]: 00 (Address 00)
D6
D5
D4
D3
STEPMODE
EMOSEL
D2
STEPMODE D[5:2]
Step mode setting
D5
D4
D3
D2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Micro step resolution
(Step mode)
1/2
1/4
1/8
1/16
1/32
1/64
1/128
1/3
1/6
1/12
1/36
1/5
1/10
1/20
1/50
1/100
EMOSEL D[7:6]
Fault detection output select for EMO output
D7
0
0
1
1
D6
0
1
0
1
Fault detection output
Over-current detection
None
VM low voltage < 7.6V (typ)
Thermal shutdown
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19
01
10
11
Figure 29. Register Map
D7
Address
00
D1
0
D0
0
LV8726TA
ADDR D[1:0] : 01 (Address 01)
D7
TSDO
D6
D5
DECAY
D4
D3
VREFATT
D2
D1
0
D0
1
VREFATT D[4:2]
Attenuator ratio for VREF
D4
0
0
0
0
1
1
1
1
D3
0
0
1
1
0
0
1
1
D2
0
1
0
1
0
1
0
1
VREF attenuation ratio
100%
90%
80%
70%
60%
50%
40%
30%
DECAY D[6:5]
Selection of Decay mode:
In the case of 25%FAST at Mixed decay, 25% of the PWM period operates with Fast decay mode.
In the case of 50%FAST at Mixed decay, 50% of the PWM period operates with Fast decay mode.
D6
0
0
1
1
D5
0
1
0
1
Decay mode: DECAY
Mixed (25% Fast)
Mixed (50% Fast)
Slow
Fast
TSDO D[7]
STEP signal OFF detection time
D7
0
1
Step signal OFF detection time: TSDO
0.52sec
1.04sec
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20
LV8726TA
ADDR D[1:0]: 10 (Address 10)
D7
D6
D5
TPWM
D4
D3
TOFF
D2
TBLANK
D1
1
D0
0
TBLANK D[3:2]
Blanking time: During this period, the mode is not switched from Charge to Decay even if the comparator detects the coil
current higher than the target current.
D3
0
0
1
1
D2
0
1
0
1
Blanking time
0.5µs
1.0µs
2.0µs
4.0µs
TOFF D[5:4]
Time for turning off the MOSFETs to avoid shoot through current
D5
0
0
1
1
D4
0
1
0
1
Through current protector OFF time
0.5µs
1.0µs
2.0µs
4.0µs
TPWM D[7:6]
PWM (Chopping) period
D7
0
0
1
1
D6
0
1
0
1
PWM (Chopping) period
8µs
16µs
24µs
32µs
ADDR D[1:0]: 11 (Address 11)
D7
NA
D6
NA
D5
NA
D4
NA
D3
OCM
D2
OCE
OCE D[2]
Turn on/off the over-current protection function
D2
0
1
Over-current protection
ON
OFF
OCM D[3]
Over-current protection mode
D3
0
1
Over-current protection mode
Latch type
Auto reset type
The output is turned off at the over-current detection. In
case of the latch type, the outputs are turned off until the
standby pin ST is set Low when over-current is detected
with second detection at 256µs after the first detection.
Refer to Figure 47 of page 36 for a timing chart of latch
type. In case of the auto reset type, the output is turned on
with 2ms interval.
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21
D1
1
D0
1
LV8726TA
Current Decay Mode Sequencing
operation is directly changed over to Slow decay
operation (3).
2. Next the device activates Slow decay until 50% (or
75%) of the PWM period depending on register setting.
The slow decay shorts the coil to make the circulation
current decrease slowly as seen in (3) event in Figure
30
3. For the remaining PWM period Fast decay is applied
by reversing the voltage across the.
LV8726 provides four selectable decay modes in one
PWM period:
1. Mixed decay mode
(Ratio is register programmable)
2. Slow decay mode
3. Fast decay mode
The description of the mixed decay sequence covers all
operation modes in detail. For slow and fast decay
operation only, the selected mode (slow, fast) covers the
entire decay period. Figures 30-32 show the sequence of
events in detail.
The operation is changed to Charge again from Fast decay.
During transition from the upper MOSFET to the lower
MOSFET of the same leg a programmable dead time
period avoids turning on both MOSFETs at the same time.
During this dead time, the coil current flows through the
body diode of the MOSFET as seen in (2), (4) and (6)
events in Figure 30. Dead time is determined by the
register bits through the serial interface.
Mixed Decay Sequence
In Mixed Decay operation the following charge-discharge
sequence of three steps is applied assuming a current
direction from “A” to “B”. Refer to Figure 33 and Figure
34 of page 24 for the timing chart of PWM based
constant-current by Mixed decay:
1. During Charge operation the voltage VM is applied to
the “A” side of the coil until the coil current exceeds
the target. In case the current has already exceeded the
target value at the end of blanking time, the Charge
For Slow decay and Fast decay mode, the coil current
flows through the body diode as shown in (2) event in
Figure 31 and Figure 32 same as Mixed decay.
1. CHARGE
VM
2.
3. SLOW
VM
VM
Current pathway
ON
OFF
GU1
GU2
OFF
B
A
OFF
GB2
OFF
B
ON
GB2
ON
GB1
RF
Charge increases
current.
GU2
A
ON
GB1
OFF
GU1
B
OFF
RF
GB2
RF
Transition from Charge to
Slow decay
Current regeneration by
Slow decay
4.
5. FAST
6.
VM
VM
VM
OFF
OFF
GU1
GU2
A
GU2
A
ON
GB1
OFF
GU1
OFF
B
ON
GB2
RF
Transition from Slow
decay to Fast decay
GU2
A
OFF
GB1
ON
GU1
OFF
B
ON
GB2
RF
Current regeneration by
Fast decay
Figure 30. Mixed Decay Sequence
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22
GU2
B
A
OFF
GB1
OFF
GU1
OFF
OFF
GB1
GB2
RF
Transition from Fast decay
to Charge
LV8726TA
Charge increases
current.
Transition from Charge to
Slow decay or from Slow
decay to Charge
Current regeneration by
Slow decay
Figure 31. Slow Decay Sequence
Charge increases
current.
Transition from Charge to
Fast decay or from Fast
decay to Charge
Figure 32. Fast Decay Sequence
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23
Current regeneration by
Fast decay
LV8726TA
Timing Chart of PWM Constant-Current Control
When the current control mode is switched from Decay
mode to Charge mode, a noise in the current sense
resistance occurs by a recovery current, and it may
erroneously detect the voltage of the sense pin. Blanking
time is provided in order to prevent this erroneous
detection. During this period, the mode is not switched
from Charge to Decay even if the comparator detects the
coil current higher than the target current.
Mixed decay current control
STEP
Set current
Set current
Coil current
Blanking Tim e
Fchop
PW M(Chopping) period
CHARGE
Current mode CHARGE
SLOW
SLOW
FAST (50%)
FAST (50%)
Figure 33. Mixed Decay (50%FAST) Rising Slope
STEP
Set current
Blanking Time
Coil current
Set current
PWM(Chopping) period
Fchop
Current mode CHARGE SLOW
FAST (50%)
Blanking Time
FAST
CHARGE
SLOW FAST (50%)
Figure 34. Mixed Decay (50%FAST) Falling Slope
When a coil current reached the set current, external
MOSFETs are repeated Charge mode-> Slow decay
mode-> Fast decay mode according to PWM period. The
coil current is controlled constant-current by repeating
three modes.
As for the Fast period, it is selectable in 50% and 25% of
PWM period by serial interface.
The coil current (ICOIL) and set current (IREF) are
compared in blanking time.
When ICOIL < IREF:
The Charge mode is continued until ICOIL  IREF. If
ICOIL reaches IREF, the mode is switched to Slow decay
mode, and then is changed Fast decay mode.
When ICOIL > IREF:
The Fast decay mode begins. The coil current is
attenuated in the Fast decay mode till one PWM period is
over.
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24
LV8726TA
Slow decay current control
STEP
Set current
Set current
Coil current
Blanking Time
Fchop
PW M(Chopping) period
CHARGE
Current mode
CHARGE
SLOW
SLOW
Figure 35. Slow Decay Rising Slope
S TE P
S e t c u rre n t
C o il cu rre n t
S e t c u rre n t
B la n k in g T im e
P W M (C h o p p in g ) p e rio d
F chop
C u rre n t m o d e
CHARGE
SLOW
B la n k in g T im e
SLOW
B la n k in g T im e
SLOW
Figure 36. Slow Decay Falling Slope
When a coil current reached the set current, external
MOSFETs are repeated Charge mode-> Slow decay mode
according to PWM period. The coil current is controlled
constant-current by repeating two modes.
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25
LV8726TA
Fast decay current control
STEP
Set current
Set current
Coil current
Blanking Time
Fchop
Current mode
PW M(Chopping) period
CHARGE
FAST
CHARGE
FAST
Figure 37. Fast Decay Rising Slope
STEP
S e t c u rre n t
C o il c u rre n t
S e t c u rre n t
B la n k in g T im e
P W M (C h o p p in g ) p e rio d
F chop
C u rre n t m o d e
CHARGE
FA S T
B la n k in g T im e
FA S T
CHARGE
FA S T
Figure 38. Fast Decay Falling Slope
When a coil current reached the set current, external
MOSFETs are repeated Charge mode-> Fast decay mode
according to PWM period. The coil current is controlled
constant-current by repeating two modes.
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26
LV8726TA
Power on/off Sequence
Power-on timing of VM power supply and VCC power
supply and input timing of VREF voltage are not
restricted. It is possible to power on the VCC power
supply after VM and vice versa. It is also possible to
supply VREF voltage first.
At startup, when all of the following conditions are met;
VM ≥ 8.7V, VCC ≥ 2.7V, and PS = High, the internal
regulators and gate voltage regulators start. It takes
100us for the regulators to get a stable output. The
VREF input should not be floating, and the required
input signal should be applied at least 50µs, before ST is
pulled High. The register access by serial interface and
the logic pin control are possible at least 100us after ST
has gone High.
Figure 39 shows an example of timing chart that
supplied the voltage in order of VM, VCC and VREF
including the access timing of the logic pins and the
serial interface.
Power-off timing of VM power supply, VCC power
supply and VREF voltage are not restricted. It is
possible to power off the VM power supply after VCC
and vice versa. It is also possible to supply VREF
voltage last. VM, VCC and VREF voltage should be
turned off at least 10µs, after ST was pulled Low in
reverse with Power-on sequence.
Figure 40 shows an example of Power-off timing chart.
Figure 39. Timing Chart Example of Power-on
Sequence
Figure 40. Timing Chart Example of Power-off
Sequence
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27
LV8726TA
Table 10: Current Ratio [%] for Micro Step 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 and 1/128
STEP
θ0
θ1
θ2
θ3
θ4
θ5
θ6
θ7
θ8
θ9
θ10
θ11
θ12
θ13
θ14
θ15
θ16
θ17
θ18
θ19
θ20
θ21
θ22
θ23
θ24
θ25
θ26
θ27
θ28
θ29
θ30
θ31
θ32
θ33
θ34
θ35
θ36
θ37
θ38
θ39
θ40
θ41
θ42
θ43
θ44
θ45
θ46
θ47
θ48
θ49
θ50
θ51
θ52
θ53
θ54
θ55
θ56
θ57
θ58
θ59
θ60
θ61
θ62
θ63
θ64
1/128 Step
1ch
2ch
100
100
100
100
100
100
100
100
100
99
99
99
99
99
99
98
98
98
98
97
97
97
96
96
96
95
95
95
94
94
93
93
92
92
91
91
90
90
89
89
88
88
87
86
86
85
84
84
83
82
82
81
80
80
79
78
77
77
76
75
74
73
72
72
71
0
1
2
4
5
6
7
9
10
11
12
13
15
16
17
18
20
21
22
23
24
25
27
28
29
30
31
33
34
35
36
37
38
39
41
42
43
44
45
46
47
48
49
50
51
52
53
55
56
57
58
59
60
61
62
62
63
64
65
66
67
68
69
70
71
1/64 Step
1ch
2ch
100
0
100
2
100
5
100
7
100
10
99
12
99
15
99
17
98
20
98
22
97
24
96
27
96
29
95
31
94
34
93
36
92
38
91
41
90
43
89
45
88
47
87
49
86
51
84
53
83
56
82
58
80
60
79
62
77
63
76
65
74
67
72
69
71
71
1/32 Step
1ch
2ch
100
100
100
99
98
97
96
94
92
90
88
86
83
80
77
74
71
0
1/16 Step
1ch
2ch
100
0
1/8 Step
1ch
2ch
100
0
1/4 Step
1ch
2ch
100
1/2 Step
1ch
2ch
0
100
5
10
100
10
15
20
98
20
98
20
24
29
96
29
34
38
92
38
92
38
92
38
43
47
88
47
51
56
83
56
83
56
60
63
77
63
67
71
71
71
71
71
71
71
71
STEP
0 θ65
θ66
θ67
θ68
θ69
θ70
θ71
θ72
θ73
θ74
θ75
θ76
θ77
θ78
θ79
θ80
θ81
θ82
θ83
θ84
θ85
θ86
θ87
θ88
θ89
θ90
θ91
θ92
θ93
θ94
θ95
θ96
θ97
θ98
θ99
θ100
θ101
θ102
θ103
θ104
θ105
θ106
θ107
θ108
θ109
θ110
θ111
θ112
θ113
θ114
θ115
θ116
θ117
θ118
θ119
θ120
θ121
θ122
θ123
θ124
θ125
θ126
θ127
θ128
71
1/128 Step
1ch
2ch
70
69
68
67
66
65
64
63
62
62
61
60
59
58
57
56
55
53
52
51
50
49
48
47
46
45
44
43
42
41
39
38
37
36
35
34
33
31
30
29
28
27
25
24
23
22
21
20
18
17
16
15
13
12
11
10
9
7
6
5
4
2
1
0
72
72
73
74
75
76
77
77
78
79
80
80
81
82
82
83
84
84
85
86
86
87
88
88
89
89
90
90
91
91
92
92
93
93
94
94
95
95
95
96
96
96
97
97
97
98
98
98
98
99
99
99
99
99
99
100
100
100
100
100
100
100
100
100
www.onsemi.com
28
1/64 Step
1ch
2ch
69
72
67
74
65
76
63
77
62
79
60
80
58
82
56
83
53
84
51
86
49
87
47
88
45
89
43
90
41
91
38
92
36
93
34
94
31
95
29
96
27
96
24
97
22
98
20
98
17
99
15
99
12
99
10
100
7
100
5
100
2
100
0
100
1/32 Step
1ch
2ch
67
74
63
77
60
80
56
83
51
86
47
88
43
90
38
92
34
94
29
96
24
97
20
98
15
99
10
100
5
100
0
100
1/16 Step
1ch
2ch
63
77
56
83
47
88
38
92
29
96
20
98
10
100
0
100
1/8 Step
1ch
2ch
56
83
38
92
20
98
0
100
1/4 Step
1ch
2ch
38
92
0
100
1/2 Step
1ch
2ch
0
100
LV8726TA
100.0
θ0
θ8
θ16
θ24
θ32
θ40
θ48
θ56
θ64
1ch current ratio (%)
66.7
θ72
θ80
θ88
θ96
33.3
θ104
θ112
θ120
θ128
0.0
0.0
33.3
66.7
2ch current ratio (%)
Figure 41. Vector Locus Plot for Example of 1/128 Micro Step
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29
100.0
LV8726TA
Table 11: Current Ratio [%] for Micro Step 1/5, 1/10, 1/20, 1/50 and 1/100
STEP
θ0
θ1
θ2
θ3
θ4
θ5
θ6
θ7
θ8
θ9
θ10
θ11
θ12
θ13
θ14
θ15
θ16
θ17
θ18
θ19
θ20
θ21
θ22
θ23
θ24
θ25
θ26
θ27
θ28
θ29
θ30
θ31
θ32
θ33
θ34
θ35
θ36
θ37
θ38
θ39
θ40
θ41
θ42
θ43
θ44
θ45
θ46
θ47
θ48
θ49
θ50
1/100 Step
1ch
2ch
100
100
100
100
100
100
100
99
99
99
99
99
98
98
98
97
97
96
96
96
95
95
94
94
93
92
92
91
90
90
89
88
88
87
86
85
84
84
83
82
81
80
79
78
77
76
75
74
73
72
71
0
2
3
5
6
8
9
11
13
14
16
17
19
20
22
23
25
26
28
29
31
32
34
35
37
38
40
41
43
44
45
47
48
50
51
52
54
55
56
58
59
60
61
63
64
65
66
67
68
70
71
1/50 Step
1ch
2ch
1/20 Step
1ch
2ch
100
0
100
3
100
6
100
100
100
9
99
13
99
16
98
19
98
22
99
97
97
25
96
28
95
31
94
34
93
37
95
92
92
40
90
43
89
45
88
48
86
51
89
85
84
54
83
56
81
59
79
61
77
64
81
76
75
66
73
68
71
71
71
1/10 Step
1ch
2ch
0
100
1/5 Step
1ch
2ch
0
100
8
16
99
16
23
31
95
31
95
38
45
89
45
52
59
81
59
65
71
71
81
STEP
0 θ51
θ52
θ53
θ54
θ55
θ56
θ57
θ58
θ59
θ60
θ61
θ62
θ63
θ64
θ65
θ66
θ67
θ68
θ69
θ70
31 θ71
θ72
θ73
θ74
θ75
θ76
θ77
θ78
θ79
θ80
θ81
θ82
θ83
θ84
θ85
θ86
θ87
θ88
θ89
θ90
59 θ91
θ92
θ93
θ94
θ95
θ96
θ97
θ98
θ99
θ100
1/100 Step
1ch
2ch
71
www.onsemi.com
30
70
68
67
66
65
64
63
61
60
59
58
56
55
54
52
51
50
48
47
45
44
43
41
40
38
37
35
34
32
31
29
28
26
25
23
22
20
19
17
16
14
13
11
9
8
6
5
3
2
0
72
73
74
75
76
77
78
79
80
81
82
83
84
84
85
86
87
88
88
89
90
90
91
92
92
93
94
94
95
95
96
96
96
97
97
98
98
98
99
99
99
99
99
100
100
100
100
100
100
100
1/50 Step
1ch
2ch
68
73
66
75
64
77
61
79
59
81
56
83
54
84
51
86
48
88
45
89
43
90
40
92
37
93
34
94
31
95
28
96
25
97
22
98
19
98
16
99
13
99
9
100
6
100
3
100
0
100
1/20 Step
1ch
2ch
65
76
59
81
52
85
45
89
38
92
31
95
23
97
16
99
8
100
0
100
1/10 Step
1ch
2ch
59
81
45
89
31
95
16
99
0
100
1/5 Step
1ch
2ch
59
81
31
95
0
100
LV8726TA
100.0
θ0
θ5
θ10
θ15
θ20
θ25
θ30
θ35
θ40
θ45
θ50
1ch current ratio (%)
66.7
θ55
θ60
θ65
θ70
θ75
33.3
θ80
θ85
θ90
θ95
θ100
0.0
0.0
33.3
66.7
2ch current ratio (%)
Figure 42. Vector Locus Plot for Example of 1/100 Micro Step
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31
100.0
LV8726TA
Table 12: Current Ratio [%] for Micro Step 1/3, 1/6, 1/12 and 1/36
100
100
100
99
98
98
97
95
94
92
91
89
87
84
82
79
77
74
71
1/12 Step
1ch
2ch
0
4
9
13
17
22
26
30
34
38
42
46
50
54
57
61
64
68
71
100
0
99
13
97
26
92
38
87
50
79
61
71
71
1/6 Step
1ch
2ch
100
0
97
1/3 Step
1ch
2ch
100
26
87
50
71
87
STEP
0 θ19
θ20
θ21
θ22
θ23
θ24
θ25
θ26
θ27
θ28
θ29
θ30
50 θ31
θ32
θ33
θ34
θ35
θ36
1/36 Step
1ch
2ch
68
64
61
57
54
50
46
42
38
34
30
26
22
17
13
9
4
0
74
77
79
82
84
87
89
91
92
94
95
97
98
98
99
100
100
100
1/12 Step
1ch
2ch
61
79
50
87
38
92
26
97
13
99
0
100
1/6 Step
1ch
2ch
50
87
26
97
0
100
71
100.0
θ3
θ0
θ6
θ9
θ12
θ15
θ18
66.7
1ch current ratio (%)
STEP
θ0
θ1
θ2
θ3
θ4
θ5
θ6
θ7
θ8
θ9
θ10
θ11
θ12
θ13
θ14
θ15
θ16
θ17
θ18
1/36 Step
1ch
2ch
θ21
θ24
θ27
33.3
θ30
θ33
θ36
0.0
0.0
33.3
66.7
2ch current ratio (%)
Figure 43. Vector Locus Plot for Example of 1/36 Micro Step
www.onsemi.com
32
100.0
1/3 Step
1ch
2ch
50
87
0
100
LV8726TA
STEP
MO
(%)
100
I1
0
-100
(%)
100
I2
0
-100
Figure 44-1. Current Waveform Example: Case of 1/2 Step CW
1/2 (Half) step
VM=48V, VCC=3.3V, VREF=1.1V (Iout≈2.0A)
RF1/2=0.11kΩ, STEP=2000Hz
Rcoil=0.47Ω
Decay mode: Mixed (25% Fast)
PWM (chopping) period: 8us
MO
5V/div
STEP
5V/div
OUT1
Motor Current
2A/div
OUT3
Motor Current
2A/div
1ms/div
Figure 44-2. Current Waveform Example of the stepper motor: Case of 1/2 Step CW
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33
LV8726TA
STEP
MO
[%]
100
50
I1
0
-50
-100
[%]
100
50
I2
0
-50
-100
Figure 45-1. Current Waveform Example: Case of 1/16 Step CW
1/16 step
VM=48V, VCC=3.3V, VREF=1.1V (Iout≈2.0A)
RF1/2=0.11kΩ, STEP=2000Hz
Rcoil=0.47Ω
Decay mode: Mixed (25% Fast)
PWM (chopping) period: 8us
MO
5V/div
STEP
5V/div
OUT1
Motor Current
2A/div
OUT3
Motor Current
2A/div
Figure 45-2. Current Waveform Example of the stepper motor: Case of 1/16 Step CW
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34
LV8726TA
Figure 46-1. Current Waveform Example: Case of 1/128 Step CW
1/128 step
VM=48V, VCC=3.3V, VREF=1.1V (Iout≈2.0A)
RF1/2=0.11kΩ, STEP=2000Hz
Rcoil=0.47Ω
Decay mode: Mixed (25% Fast)
PWM (chopping) period: 8us
MO
5V/div
STEP
5V/div
OUT1
Motor Current
2A/div
OUT3
Motor Current
2A/div
50ms/div
Figure 46-2. Current Waveform Example of the stepper motor: Case of 1/128 Step CW
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35
LV8726TA
Over-Current Protection (OCP)
The over-current covers the following three circuit short
modes.
1. Output shorted to power rail
2. Output shorted to ground
3. Loads shorted to each other (two outputs of a
channel)
Figure 48, Figure 49. and Figure 50. show these three
circuit short modes.
The over-current is detected when the voltage between
drain and source of the external P-MOSFET exceeds 3V
during turn-on.
For the low side, it is detected when RFx voltage
exceeds three times the RFx voltage defined by
applying setting current (ATTRATIO =1.0:100%). RFx
pin voltage is as shown in Equation 6. Refer to equation
2 to determine Iout.
5
Output ON
Over-current
Detected
Fault
Detection
Release
2µs
Output OFF Timer latch period
(typ:256µs)
Output ON
Output OFF
2µs
Over-current
Detected
Internal
counter
1st counter 1st counter 1st counter 1st counter
start
stop
start
stop
2nd counter
start
2nd counter
stop
Figure 47. Timing Chart of Latched OCP
Auto Reset OCP
When the over-current is detected for 2µs (typ), the
outputs turned off for 2ms (typ), and they are turned on
again after 2ms. If the over-current mode still continues,
over-current protection circuit is continued repetition
operation of on and off until the current gets down.
∙
H-bridge
Output state
……… 6
Where,
IOUT(max) : Coil current [A] (ATTRATIO=1.0: 100%)
RRFx : Resistor between RFx and GND [Ω]
VRFx(max) : RFx voltage [V] (ATTRATIO=1.0: 100%)
For example, in case of
1.5 V]
1.5
[V] 0.3 V
5
The over-current protection voltage of low side is
3∙
3 0.3[V] 0.9 V
Under Voltage Lockout (UVLO)
The integrated UVLO protection enables safe shutdown
of the system if the voltage on either VM or VCC drops.
When the VM voltage is less than 7.6V (typ), the
outputs are turned off and EMO output is asserted.
When the VCC voltage is less than 2.3V (typ), logic
circuits are put into the reset state and the outputs are
turned off.
Thermal Shutdown (TSD)
It depends on VREF input voltage.
Latched OCP
If a coil current exceeds the detection current level for
2µs, the outputs are turned off. Subsequently, the
outputs are turned on again after the timer latch period
(typ: 256μs). If the output remains in over-current
condition, it will be turned off again and remain latched
off. In this case the programmed EMO output is asserted.
The over-current protection latch (the outputs are turned
off), is released by setting ST = "L".
The built-in TSD protection prevents damage to the
LV8726 from excessive heat. If the junction
temperature Tj exceeds 180°C (typ), the outputs are
turned off. If Tj goes down under 140°C (40°C of
hysteresis), the outputs are automatically restored. This
thermal shutdown function doesn’t guarantee protection
of the set and the destruction prevention.
www.onsemi.com
36
LV8726TA
Short to Power
Figure 48. Short Output to Power Rail
Short to GND
Figure 49. Short Output to GND
Load short
Figure 50. Short Load
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37
LV8726TA
PCB LAYOUT GUIDELINES
VM and Ground routing
Make sure to connect VM and the power rail of the
external P channel MOSFETs by a low impedance route.
As high current flows into the source of the N channel
MOSFETs, these sources must also be connected by a
low impedance route to power ground (PGND). PGND
and GND (pin 30) of LV8726 must also be connected by
low impedance traces.
(pin 30) and PGND of the N channel MOSFETs are in
the same plane, connect the exposed pad to same GND.
Do not connect the exposed pad to the PGND only. If
GND (30pin) and PGND are divided, connect it to GND
(30pin).
Thermal Test conditions
Size: 90mm × 90mm × 1.6mm (two layers PCB)
Material: Glass epoxy
Copper wiring density: L1 = 55% / L2 = 70%
Exposed Pad
The exposed pad is connected to the frame of the
LV8726 and must be connected to GND. When GND
L1 : Copper wiring pattern diagram (top)
L2 : Copper wiring pattern diagram (bottom)
Figure 51. Pattern Diagram of Top and Bottom Layer
Recommendation
The thermal data provided is for the thermal test
condition where 90% or more of the exposed die pad is
soldered.
It is recommended to derate critical parameters for a
safe design. Electrical parameters that are recommended
to be derated are: operating voltage, operating current,
junction temperature, and device power dissipation. The
recommended derating for a safe design is as shown
below:



Check solder joints and verify reliability of solder joints
for critical areas such as exposed die pad, power pins
and grounds.
Any void or deterioration in solder joint of these critical
areas may cause deterioration in thermal conduction and
lead to thermal destruction of the device.
Maximum 80% for operating voltage
Maximum 80% for operating current
Maximum 80% for junction temperature
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38
LV8726TA
PACKAGE DIMENSIONS
unit : mm
TQFP48 EP 7x7, 0.5P
CASE 932F
ISSUE C
4X 12 TIPS
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL BE 0.08 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07.
0.20 C A-B D
NOTE 9
D
NOTE 7
D
NOTE 7
25
37
A
NOTES
4&6
SIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.25 PER SIDE. DIMENSIONS D1 AND E1
ARE MAXIMUM PLASTIC BODY SIZE INCLUDING MOLD MISMATCH.
5. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM
PACKAGE SIZE BY AS MUCH AS 0.15.
6. DATUMS A-B AND D ARE DETERMINED AT DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
NOTE 7
B
NOTE 9
E1
E
8. DIMENSIONS D AND E TO BE DETERMINED AT DATUM PLANE C.
13
48
1
D1
4X
NOTES 4 & 6
0.20 H A-B D
TOP VIEW
DETAIL A
0.08 C
A
H
0.05
L2
A2
A1
e
48X
SIDE VIEW
C
SEATING
PLANE
b
0.20 C A-B D
DETAIL A
L
M
DIM
A
A1
A2
b
D
D1
D2
E
E1
E2
e
L
L2
M
MILLIMETERS
MIN
MAX
0.95
1.25
0.05
0.15
0.90
1.20
0.17
0.27
9.00 BSC
7.00 BSC
4.90
5.10
9.00 BSC
7.00 BSC
4.90
5.10
0.50 BSC
0.45
0.75
0.25 BSC
0
7
RECOMMENDED
SOLDERING FOOTPRINT*
NOTE 3
D2
E2
9.36
48X
1.13
5.30
9.36
5.30
1
BOTTOM VIEW
0.50
PITCH
www.onsemi.com
39
48X
0.29
DIMENSIONS: MILLIMETERS
LV8726TA
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
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nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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