EN6197 D

Ordering number : EN6197C
LB1927
Monolithic Digital IC
For Office Automation Equipment
http://onsemi.com
3-phase Brushless Motor Driver
Overview
The LB1927 is a 3-phase brushless motor driver well suited for drum and paper feed motors in laser printers, plain-paper
copiers and other office automation equipment. Direct PWM drive allows control with low power losses. Peripheral
circuitry including speed control circuit and FG amplifier is integrated, thus allows drive circuit to be constructed with a
single chip.
Features
• 3-phase bipolar drive (30V, 2.5A)
• Direct PWM drive technique
• Built-in diode for absorbing output lower-side kickback
• Speed discriminator and PLL speed control
• Speed lock detection output
• Built-in forward/reverse switching circuit
• Built-in protection circuitry includes current limiter, overheat protection, motor restraint protection, etc.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
VCC max
Ratings
Unit
30
Maximum output current
IO max
T ≤ 500ms
Allowable power dissipation 1
Pd max 1
Independent IC
Allowable power dissipation 2
Pd max 2
With an arbitrary large heat sink
Operating temperature
Storage temperature
V
2.5
A
3
W
20
W
Topr
-20 to +80
°C
Tstg
-55 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
N1908 MS JM/O0702AS(OT)/D1099TH(KI)/62599RM(KI) No.6197-1/11
LB1927
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Power supply voltage range 1
VCC
9.5 to 28
V
Regulator voltage output current
IREG
-30 to 0
mA
LD output current
ILD
0 to 15
mA
Electrical Characteristics at Ta = 25°C, VCC = VM = 24V
Ratings
Parameter
Symbol
Conditions
min
typ
Unit
max
Power supply current 1
ICC1
23
30
mA
Power supply current 2
ICC2
In STOP mode
3.5
5.0
mA
Output saturation voltage 1
VOsat1
IO = 1.0A, VO (SINK) +VO (SOURCE)
2.0
2.5
V
Output saturation voltage 2
VOsat2
IO = 2.0A, VO (SINK) +VO (SOURCE)
2.6
3.2
V
Output leak current
IOleak
100
μA
Lower-side diode forward voltage 1
VD1
ID = -1.0A
1.2
1.5
V
Lower-side diode forward voltage 2
VD2
ID = -2.0A
1.5
2.0
V
Output
5V regulator voltage output
Output voltage
VREG
IO = -5mA
5.00
5.35
V
Voltage fluctuation
ΔVREG1
VCC = 9.5 to 28V
4.65
30
100
mV
Load fluctuation
ΔVREG2
IO = -5 to -20mA
20
100
mV
Hall amplifier
Input bias current
IHB
Common mode input voltage range
VICM
-2
Hall input sensitivity
μA
-0.5
1.5
VREG-1.5
80
V
mVp-p
Hysteresis width
ΔVIN
Input voltage L→H
VSLH
12
mV
Input voltage H→L
VSHL
-12
mV
15
24
42
mV
PWM oscillator
Output High level voltage
VOH (PWM)
2.5
2.8
3.1
V
Output Low level voltage
VOL (PWM)
1.2
1.5
1.8
V
Oscillator frequency
F (PWM)
Amplitude
V (PWM)
1.05
1.30
1.55
Vp-p
C = 3900pF
18
kHz
CSD circuit
Operating voltage
VOH (CSD)
3.6
3.9
4.2
V
External capacitance charge
ICHG
-17
-12
-9
μA
current
Operating time
T (CSD)
C = 10μF Design target value
3.3
s
VRF
VCC-VM
0.45
0.5
TSD
Design target value (junction temperature)
150
180
°C
ΔTSD
Design target value (junction temperature)
50
°C
Current limiter operation
Limiter
0.55
V
Thermal shutdown operation
Thermal shutdown operating
temperature
Hysteresis width
FG amplifier
Input offset voltage
VIO (FG)
Input bias current
IB (FG)
Output High level voltage
VOH (FG)
IFGO = -0.2mA
Output Low level voltage
VOL (FG)
IFGO = 0.2mA
FG input sensitivity
GAIN 100 times
Next-stage Schmitt comparator
Design target value
-10
+10
mV
-1
+1
μA
0.8
1.2
V
100
180
250
mV
2
kHz
45
51
VREG-1.2
VREG-0.8
V
3
mV
width
Operation frequency range
Open-loop gain
f (FG) = 2kHz
dB
Continued on next page.
No.6197-2/11
LB1927
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
min
typ
VREG-1.0
VREG-0.7
Unit
max
Speed discriminator
Output High level voltage
VOH (D)
IDO = -0.1mA
Output Low level voltage
VOL (D)
IDO = 0.1mA
0.8
Count number
V
1.1
V
512
PLL output
Output High level voltage
VOH (P)
IPO = -0.1mA
Output Low level voltage
VOL (P)
IPO = 0.1mA
VOL (LD)
ILD = 10mA
VREG-1.8
VREG-1.5
VREG-1.2
V
1.2
1.5
1.8
V
0.15
0.5
Lock detection
Output Low level voltage
Lock range
6.25
V
%
Integrator
Input bias current
IB (INT)
Output High level voltage
VOH (INT)
IINTO = -0.2mA
-0.4
Output Low level voltage
VOL (INT)
IINTO = 0.2mA
Open-loop gain
f (INT) = 1kHZ
Gain bandwidth product
Design target value
Reference voltage
Design target value
VREG-1.2
0.8
45
-5%
+0.4
μA
1.2
V
VREG-0.8
V
51
dB
450
kHz
VREG/2
5%
V
10
MHz
Crystal oscillator
Operating frequency range
fOSC
Low level pin voltage
VOSCL
IOSC = -0.5mA
3
High level pin current
IOSCH
VOSC = VOSCL+0.3V
1.65
V
0.4
mA
Start/stop pin
High level input voltage range
VIH (S/S)
3.5
VREG
V
Low level input voltage range
VIL (S/S)
0
1.5
V
Input open voltage
VIO (S/S)
VREG-0.5
Hysteresis width
ΔVIN
High level input current
IIH (S/S)
V (S/S) = VREG
Low level input current
IIL (S/S)
V (S/S) = 0V
VREG
V
0.35
0.50
0.65
V
-10
0
10
μA
-280
-210
μA
Forward/reverse pin
High level input voltage range
VIH (F/R)
Low level input voltage range
VIL (F/R)
Input open voltage
VIO (F/R)
Hysteresis width
ΔVIN
3.5
VREG
V
0
1.5
V
VREG-0.5
VREG
V
0.50
0.65
V
-10
0
+10
μA
-280
-210
0.35
High level input current
IIH (F/R)
V (F/R) = VREG
Low level input current
IIL (F/R)
V (F/R) = 0V
μA
No.6197-3/11
LB1927
Package Dimensions
unit : mm (typ)
3147C
Pd max -- Ta
Allowable power dissipation, Pd max -- W
24
With an arbitrary large heat sink
20
16
12
8
4
3
Without heat sink
0
-20
0
20
40
60
80
100
Ambient temperature, Ta -- °C
Pin Assignment
OUT1
F/R
IN3+
IN3-
IN2+
IN2-
IN1+
IN1-
GND1
S/S
28
27
26
25
24
23
22
21
20
19
FGIN+ FGIN- FGOUT
18
17
16
LD
15
LB1927
1
2
3
OUT2 OUT3 GND2
4
5
VCC
VM
6
7
VREG PWM
8
9
10
CSD
XI
XO INTOUT INTIN POUT DOUT
11
12
13
14
Top view
Relationship between crystal oscillator frequency fOSC and FG frequency fFG is as follows.
fFG (servo) = fOSC/ (ECL divide-by-16×count number)
= fOSC/8192
Truth Table
Source
F/R = “L”
Sink
F/R = “H”
IN1
IN2
IN3
IN1
IN2
IN3
1
OUT2→OUT1
H
L
H
L
H
L
2
OUT3→OUT1
H
L
L
L
H
H
3
OUT3→OUT2
H
H
L
L
L
H
4
OUT1→OUT2
L
H
L
H
L
H
5
OUT1→OUT3
L
H
H
H
L
L
6
OUT2→OUT3
L
L
H
H
H
L
No.6197-4/11
LB1927
Block Diagram and Sample Application Circuit
FGIN-
FGOUT
+
LD
POUT
LD
DOUT INTIN
FG AMP
–
FGIN+
–
LOCK
DET
+
VREG/2
INTOUT CSD
INT AMP
CSD
CIRCUIT
+
PWM
OSC
TSD
–
SPEED
DISCRI
+
VCC
VCC
+
CURR
LIM
PWM
Rf
VREG
VM
COMP
FG
RST
PLL
VREF
OUT1
GND1
ECL
1/16
LOGIC
VREF
1/512
DRIVER
BGP
OUT2
HALL HYS AMP
Xtal
OSC
XI
S/S
XO
S/S
F/R
F/R
5VREG
VREG
OUT3
IN1
IN2
IN3
GND2
No.6197-5/11
LB1927
Pin Description
Pin No.
Pin name
Pin function
28
OUT1
Motor drive output pins.
1
OUT2
Connect a Schottky diode between these outputs and VCC.
2
OUT3
3
GND2
5
VM
Equivalent circuit
Output ground pin.
Output block power supply and output current detection pin.
Connect a resistor (Rf) between this pin and VCC to detect the
output current as a voltage.
The output current is limited according to the equation IOUT =
VRF/Rf.
4
VCC
6
VREG
Power supply pin (except for output block).
Regulated power supply output pin (5V output).
Connect a capacitor (approx. 0.1μF) between this pin and
ground to stabilize the output.
7
PWM
PWM frequency setting pin.
Connect a capacitor between this pin and ground.
C = 3900pF results in a frequency of about 18kHz.
8
CSD
Lock protection circuit operation time setting pin.
Connecting a capacitor of about 10μF between this pin and
ground results in a protection circuit operation time of about
3.3 seconds.
9
XI
Crystal oscillator pins.
10
XO
Connect to quartz oscillator to generate the reference clock.
When an external clock (of several MHz) is used, the clock
signal should be input via a resistor of about 5.1kΩ connected
in series with the XI pin. In this case, the XO pin must be left
open.
Continued on next page.
No.6197-6/11
LB1927
Continued from preceding page.
Pin No.
Pin name
Pin function
11
INTOUT
Integrator output pin (speed control pin).
12
INTIN
Integrator input pin.
13
POUT
PLL output pin.
14
DOUT
Equivalent circuit
Speed discriminator output pin.
Acceleration : High, Deceleration : Low
15
LD
Speed lock detection pin.
When motor rotation is within lock range (±6.25%) : Low
Withstand voltage : 30V max.
Continued on next page.
No.6197-7/11
LB1927
Continued from preceding page.
Pin No.
Pin name
Pin function
16
FGOUT
FG amplifier output pin.
17
FGINFGIN+
FG amplifier input pin.
18
19
S/S
Start/stop control pin.
Equivalent circuit
By connecting a capacitor (approx. 0.1μF)
between FGIN+ and ground, the logic circuitry is
reset.
Start (Low) : 0V to 1.5V
Stop (High) : 3.5V to VREG
High when open.
Hysteresis width : approx. 0.5V.
20
GND1
Ground pin (except for output block).
22
IN1+
IN1-
Hall input pins.
High when IN+ > IN-, Low when IN+ < IN-.
IN2+
IN2-
Hall signal should have an amplitude of at least
25
IN3+
IN3-
signal noise is a problem, connect a capacitor
between IN+ and IN-.
27
F/R
21
24
23
26
100mVp-p (differential operation). When Hall
Forward/reverse control pin.
Forward (Low) : 0V to 1.5V
Reverse (High) : 3.5V to VREG
High when open.
Hysteresis width : approx. 0.5V.
No.6197-8/11
LB1927
Description of the LB1927
1. Speed control circuit
The IC performs speed control through combined use of a speed discrimination circuit and PLL circuit. The speed
control circuit counts FG cycles and outputs a deviation signal every 2FG cycles. The PLL circuit outputs a phase
deviation signal every FG cycle.
The FG servo frequency is determined by the following equation. The motor rotation speed is set by the number of
FG pulses and the crystal oscillator frequency.
fFG (servo) = fOSC/8192
fOSC : Crystal oscillator frequency
2. Output drive circuit
In order to reduce power loss at the output, the LB1927 uses the PWM drive technique. While ON, the output
transistors are always saturated, and motor drive power is adjusted by varying the output ON duty ratio. Because
output PWM switching is performed by the lower-side output transistor, a Schottky diode must be connected
between OUT and VCC. (If the reverse recovery time of the diode is too long, a feedthrough current will flow at the
instant when the lower-side transistor goes ON.) An internal diode is provided between OUT and GND. If large
output current causes a problem (waveform distortion during lower-side kickback, etc.), an external rectifying diode
or Schottky diode should be connected.
The output diode is integrated only on the lower side.
3. Current limiting circuit
The current limiting circuit limits the peak current to the value I = VRF/Rf (VRF = 0.5V typ., Rf : current detector
resistance). Current limiting is achieved by reducing the ON duty ratio of the output, which reduces the current.
4. Power save circuit
In order to reduce current drain in the STOP condition, the IC goes into power save mode. In this condition, bias
current to most circuits is cut off, but the 5V regulator output remains active.
5. Reference clock
The reference clock for speed control can be input using one of the following two methods.
(1) Using a crystal oscillator
When a crystal is used for oscillation, connect the crystal, capacitors, and a resistor as shown in the figure below.
XI
XO
C3
C4
C1
C2
R1
C1, R1 : For stable oscillation
C3 : For oscillator coupling
C2 : For stabilization and to prevent oscillation at upper harmonic frequencies
C4 : Prevents oscillation at upper harmonic frequencies
VREG
(Reference values)
Oscillator frequency (MHz)
C1 (μF)
C2 (pF)
C3 (pF)
C4 (pF)
R1 (Ω)
3 to 5
0.1
15
47
10
330k
5 to 8
0.1
10
47
None
330k
8 to 10
0.1
10
22
None
330k
The circuit configuration and values are for reference only. The crystal oscillator’s characteristics as well as the
possibility of floating capacitance and noise due to layout factors must be taken into consideration when
designing an actual application.
No.6197-9/11
LB1927
[Precautions for wiring layout design]
Since the crystal oscillator circuit operates at high frequencies, it is susceptible to the influence of floating
capacitance from the circuit board. Wiring should be kept as short as possible and traces should be kept narrow.
When designing the external circuitry, pay special attention to the wiring layout between the oscillator and C3
(C2), to minimize the influence of floating capacitance. The capacitor C4 is quite effective at reducing the
negative resistance (gain) at high frequencies. However, care is required to avoid excessive reduction in the
negative resistance at the fundamental frequency.
(2) External clock input (equivalent to crystal oscillator, several MHz)
When using an external signal source instead of a crystal oscillator, the clock signal should be input from the XI pin
through a resistor of about 5.1kΩ connected to the pin in series. The XO pin should be left open. Signal input level
Low : 0 to 0.8V
High : 2.5 to 5.0V
6. Speed lock range
The speed clock range is ±6.25% of the rated speed. When the motor rotation is within the lock range, the LD pin
becomes Low (open collector output). When the motor rotation goes out of the lock range, the ON duty ratio of the
motor drive output is varied according to the amount of deviation to bring the rotation back into the lock range.
7. PWM frequency
The PWM frequency is determined by the capacitance connected to the PWM pin.
f PWM ≈ 1/ (14400×C)
PWM frequency in the range 15 to 25kHz is desirable. The ground side of the connected capacitor must be
connected to the GND1 pin with a lead that is as short as possible.
8. Hall input signal
The Hall input requires a signal with an amplitude of at least the hysteresis width (42mV max.). Taking possible
noise influences into consideration, an amplitude of at least 100mV is desirable. If noise during output phase
switching disrupts the output waveform, insert capacitors across the Hall signal inputs (between the + and - inputs),
and position those capacitors as close as possible to the pins.
9. Forward/reverse switching
Forward/reverse switching of motor rotation is carried out with the F/R pin. If this is performed while the motor is
running, the following points must be observed :
• Feedthrough current during switching is handled by proper circuit design. However, the VCC voltage rise during
switching (caused by momentary return of motor current to power supply) must not exceed the rated voltage
(30V). If problems occur, the capacitance between VCC and GND must be increased.
• If the motor current after switching exceeds the current limiter value, the lower-side transistors go OFF but the
upper-side transistors go into the short brake state, which causes a current flow. The magnitude of the current is
determined by the motor counterelectromotive voltage and the coil resistance. This current may not exceed the
rated current (2.5A). (Forward/reverse switching at high speed therefore is not safe.)
10. Motor restraint protection circuit
To protect the IC and the motor itself when rotation is inhibited, a restraint protection circuit is provided. If the LD
output is High (unlocked) for a certain interval in the start condition, the lower-side transistors are turned off. The
length of the interval is determined by the capacitance at the CSD pin. A capacitance of 10μF results in a set
interval of about 3.3 seconds. (Tolerance approx. ±30%)
Set interval (s) ≈ 0.33×C (μF)
If the capacitor arrangement is subject to leak current, possible adverse effects such as setting time tolerances must
be taken into consideration.
When the restraint protection circuit has been activated, the condition can only be canceled by setting the system to
the stop condition or by turning the power off and on again (in the stop condition). When wishing not to use the
restraint protection circuit, connect the CSD pin to ground.
If the stop time when releasing the restraint protection is short, the capacitor charge will not be fully dissipated.
This in turn will cause a shorter restraint protection activation time after the motor has been restarted. The stop time
should therefore be designed to be sufficiently long, using the equation shown below (also when restarting in the
motor start transient state).
Stop time (ms) ≥ 15×C (μF)
No.6197-10/11
LB1927
11. Power supply stabilization
Because this IC provides a high output current and uses a switching drive technique, power supply line fluctuations
can occur easily. Therefore, a capacitor of sufficient capacitance (several ten μF or higher) must be connected
between the VCC pin and ground to assure stable operation. The ground connection of this capacitor must be
connected to the GND2 pin, which is the power block ground, at a point as close as possible to the IC. If, due to
problems associated with the heat sink, the (electrolytic) capacitor cannot be connected near the this pin, a ceramic
capacitor of about 0.1μF must be connected near the pin.
Since the likelihood of power line fluctuation increases if diodes are inserted in the power supply lines to prevent
destruction of the IC if power is connected with reverse polarity, a larger capacitance will be required.
12. VREG stabilization
A capacitor (about 0.1μF) must be connected to the VREG pin (the 5V regulator output), which functions as the
control circuit power supply, for stabilization. The ground side of this capacitor must be connected to the GND1 pin
with a lead that is as short as possible.
13. Integrating amplifier related component values
The external components used in the integrating amplifier must be located as close as possible to the IC to
minimize the circuit’s susceptibility to noise. These components must be located as far as possible from the motor.
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PS No.6197-11/11
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