ENA2143 D

Ordering number : ENA2143
LV8068V
Bi-CMOS IC
Fan Motor Driver
http://onsemi.com
Single-Phase Full-Wave Driver
Overview
The LV8068V is single-phase bipolar fan motor is driven, through BTL output linear driver, at high efficiency, low
power, and low noise by suppressing the reactive power. The BTL output can put PWM control by an outside signal
together, which is optimum for the CPU cooler, etc.
Functions
• Single-phase full-wave operating by BTL output (BTL amplifier gain : +49dB)
• Speed control available by PWM input
• The characteristic of the motor rotational speed adjust by “VCONT” voltage
• The characteristic of the motor rotational minimum speed adjust by “RMI” voltage
• Hall bias output terminal (VHB = 1.32V (typ))
• Built-in Quick Start circuit
• Startup support function (50% Duty Start)
• FG (rotate detection) output terminal (Open drain output)
• RD (Lock detection) output terminal (Open drain output)
• Built-in Current Limiter circuit (limit at IO = 250mA with Rf = 1 connection, the limiter value determined with Rf.)
• Built-in lock protection and automatic return circuit
• Built-in thermal shut-down (TSD) circuit
Semiconductor Components Industries, LLC, 2013
May, 2013
O2412NKPC 20120824-S00001 No.A2143-1/11
LV8068V
Specitications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Maximum supply voltage
VCC max
OUT pin output current
IOUT max
OUT pin output voltage handling
Conditions
Ratings
Unit
18
V
1.2
A
VOUT max
18
V
RD output voltage handling
VRD max
18
V
RD output current
IRD max
5
mA
FG output voltage handling
VFG max
IFG max
18
V
5
mA
IHB max
VPWM max
10
mA
PWM input voltage handling
Allowable power dissipation
Pd max
Operating temperature
Topr
FG output current
HB output current
In regular mode
7
V
0.8
W
-40 to +90
°C
IC On board*
Storage temperature
Tstg
-55 to +150
°C
* Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board
Caution 1) Absolute maximum ratings represent the values which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Operating supply voltage1
VCC op1
Active at all circuit
Conditions
Operating supply voltage2
VCC op2
Start-up with PWM=H and RMI=VCONT=L
Hall input common-mode input voltage
VICM
Ratings
Unit
6.0 to 16.0
V
4.0 to 6.0
V
0.3 to 5VREG-1.5
V
V
range
VCONT input voltage range
VCONTIN
0.3 to 5VREG
RMI input voltage range
VRMIIN
0.3 to 5VREG
PWM input frequency range
FPWMIN
20 to 50
V
kHz
Electrical Characteristics at Ta = 25°C, VCC = 12.0V
Parameter
Symbol
Circuit current
ICC
5VREG output voltage
VRGL
I5VREG = 5mA
REGH output voltage
VRGH
IREGH = 5mA
HB bias voltage
VHB
IHB = 5mA
Hall Input bias current
IHIN
Output ON voltage
VO
VRF
Current limiter
Hall amplifier output offset voltage
Hall amplifier voltage gain
VINOFS
GH
PWM pin bias current
IPWM
PWM pin input Low level
VPWML
VPWMH
PWM pin input High level
PWM input smallest pulse width
TPWM
CPWM charge current
ICPC
CPWM discharge current
ICPD
CPWM charge/ discharge current ratio
ICPRTO
CPWM oscillation High level
CPWM oscillation Low level
Ratings
Conditions
min
typ
Unit
max
6
8
4.7
5.0
5.3
V
VCC-4.6
VCC-4.2
1.32
VCC-3.9
1.42
V
1
μA
1.22
IO = 250mA, source + sink
200
V
0.35
0.5
V
250
300
mV
10
mV
-10
PWM = GND
mA
44
49
-20
-10
dB
-3
μA
0
0.7
V
2.5
5VREG
V
23
μA
μA
Design guarantee*
μs
5
13
18
13
18
23
0.7
1
1.2
VCPH
3.3
3.5
3.8
V
VCPL
0.7
1.0
1.3
V
CPWM oscillation amplitude width
VCPA
2.3
2.5
2.7
V
VCONT pin input bias current
ICONT
1
μA
1
μA
0.3
V
RMI pin input bias current
IRMI
RD output Low-level voltage
VRD
ICPRTO = ICPC/ICPD
IRD = 3mA
*: Design guarantee: Indicates a design target value. These parameters are not tested in the independent IC.
Continued on next page.
No.A2143-2/11
LV8068V
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
μA
RD output leakage current
IRDL
VRD = 18V
10
FG output Low-level voltage
VFG
IFG = 3mA
0.3
V
FG output leakage current
IFGL
VFG = 18V
10
μA
FG comparator hysteresis width
ΔVFG
±2
±4
±10
mV
Output ON time in Lock-detection
TACT
CPWM = 100pF
0.35
0.5
0.65
sec
Output OFF time in Lock-detection
TDET
CPWM = 100pF
3.0
4.5
6.0
sec
Output ON/OFF ratio in Lock-detection
TRTO
TRTO = TDET/TACT
9
11
Thermal shutdown oprating temperature
TSD
Design guarantee*
180
°C
Thermal shutdown hysteresis width
ΔTSD
Design guarantee*
40
°C
7
* Design guarantee: Indicates a design target value. These parameters are not tested in the independent IC.
Package Dimensions
unit : mm (typ)
3178B
Pd max -- Ta
Allowable power dissipation, Pd max -- W
1.2
5.2
0.5
6.4
9
4.4
16
1
8
0.65
0.15
0.22
0.80
0.8
0.6
0.4
0.38
0.2
0
--40
1.5max
(0.33)
1.0
0
--20
20
40
60
80
100
0.1
(1.3)
Ambient temperature, Ta -- °C
SANYO : SSOP16(225mil)
Pin Assignment
SSOP16 (225mil)
OUT1 1
16 OUT2
VCC 2
15 RF
REGH 3
14 GND
5VREG 4
13 PWM
LV8068V
VCONT 5
12 CPWM
RMI 6
11 IN2
FG 7
10 HB
RD 8
9
IN1
Top view
No.A2143-3/11
LV8068V
Block Diagram
16 OUT2
VCC
2
REGH
3
High Side
Regulator
5VREG
4
Low Side
Regulator
VCONT
5
+
-
1
+
OUT1
15 RF
14 GND
LEVEL SHIFT
13 PWM
OSC &
CLOCK
+
-
12 CPWM
CONTROL
RMI
6
FG
7
RD
8
11 IN2
HB
10 HB
ENABLE
9
TSD
IN1
Lock Detection
No.A2143-4/11
LV8068V
Pin Function
Pin No.
Pin name
Function
1
OUT1
Motor driver output pin
16
OUT2
Motor driver output pin
Equivalent circuit
1
16
15
2
VCC
Voltage supply pin
3
REGH
Regulator voltage output pin for internal circuit
(Upper side)
3
4
5VREG
Regulator voltage output pin for internal circuit
(Lower side)
4
5
VCONT
Output duty control pin for CPWM
6
RMI
Output minimum duty control pin for CPWM
5
6
7
FG
FG pulse output pin
8
RD
RD pulse output pin
9
IN1
Hall input - pin
11
IN2
Hall input + pin
7
8
9
11
10
HB
Hall bias output pin
10
Continued on next page.
No.A2143-5/11
LV8068V
Continued from preceding page.
Pin No.
12
Pin name
CPWM
Function
Equivalent circuit
Capacitor connection pin for PWM oscillator and
Main clock
12
13
PWM
PWM control input pin
13
14
GND
15
RF
Reference voltage pin for current limiter
15
No.A2143-6/11
LV8068V
Sample Application Circuit
1. Speed control by PWM pin
1 OUT1
OUT2 16
Di
2 VCC
+
Cr
RF 15
*6 Rf
*8
ZDi
3 REGH
GND 14
4 5VREG
PWM 13
*1
PWM-IN
*7
H:Active
L:Stop
5 VCONT
CPWM 12
*5
6 RMI
IN2 11
7 FG
HB 10
C1
H
R1
*4
8 RD
IN1 9
*2,*3
*1 When the diode Di is used to prevent device destruction from reverse connection, the capacitor Cr must be inserted to
assure a path for regenerative currents.
Similarly, if there no nearby capacitors on the fan power supply line, the capacitor Cr is also required to increase
reliability. When a protection diode against reverse connection is used, if supply voltage increases due to coil
kickback, connect zener diode between power supply and GND.
*2 The Hall element is biased at a constant voltage of approximately 1.3V from the HB pin. Thus the LV8068V provides
a stable Hall output with excellent temperature characteristics. If the Hall output is needed to adjust the amplitude, use
the resistor R1 as shown in the figure.
*3 When the wiring from the Hall output to IC Hall input is long, noise may be carried through the wiring. In this case,
insert the capacitor C1 as shown in the figure.
*4 FG/RD pin is open collector (drain) output. This pin must be left open if unused.
*5 It is a capacitor for PWM oscillations. (Cpwm = 100pF, fpwm = about 33kHz (typ))
*6 The current limiter is activated when the voltage between current detection resistor exceeds 0.25V between GND and
RF. The current limiter is activated at IO = 250mA when RL = 1Ω. Setting is made with the Rf resistance.
Short-circuit GND and RF when the current-limiter PWM is not to be used.
*7 Please insert enough capacitor value between GND and RGL for stabilization on a terminal.
*8 Please insert enough capacitor value between Vcc and RGH for stabilization on a terminal.
No.A2143-7/11
LV8068V
2. Speed control by VCONT/RMI pin
1 OUT1
OUT2 16
Di
2 VCC
+
Cr
RF 15
*6 Rf
*8
ZDi
3 REGH
GND 14
4 5VREG
PWM 13
5 VCONT
CPWM 12
*1
*7
*9
*5
*10
6 RMI
IN2 11
PWM-IN
C1
7 FG
HB 10
H
R1
*4
8 RD
IN1 9
*2,*3
*1 When the diode Di is used to prevent device destruction from reverse connection, the capacitor Cr must be inserted to
assure a path for regenerative currents.
Similarly, if there no nearby capacitors on the fan power supply line, the capacitor Cr is also required to increase
reliability. When a protection diode against reverse connection is used, if supply voltage increases due to coil
kickback, connect zener diode between power supply and GND.
*2 The Hall element is biased at a constant voltage of approximately 1.3V from the HB pin. Thus the LV8068V provides
a stable Hall output with excellent temperature characteristics. If the Hall output is needed to adjust the amplitude, use
theresistor R1 as shown in the figure.
*3 When the wiring from the Hall output to IC Hall input is long, noise may be carried through the wiring. In this case,
insert the capacitor C1 as shown in the figure.
*4 FG/RD pin is open collector (drain) output. This pin must be left open if unused.
*5 It is a capacitor for PWM oscillations. (Cpwm = 100pF, fpwm = about 33kHz (typ))
*6 The current limiter is activated when the voltage between current detection resistor exceeds 0.25V between GND and
RF. The current limiter is activated at IO = 250mA when RL = 1Ω. Setting is made with the Rf resistance.
Short-circuit GND and RF when the current limiter PWM is not to be used.
*7 Please insert enough capacitor value between GND and RGL for stabilization on a terminal.
*8 Please insert enough capacitor value between Vcc and RGH for stabilization on a terminal.
*9 VCONT is speed control pin. For the control method ,refer to the timing chart.
*10 RMI is minimum speed setting pin. When you do not use RMI, please make pull-up to 5VREG
No.A2143-8/11
LV8068V
Timing Chart
1. Stand-by/Start-up
VCC
TSLP
TSLP
PWM1/2
50% Duty
HB
OUT1/OUT2
Active
Stsnd-by
Active
Stsnd-by
Active
*TSLP = 400μs (typ)
*When PWM signal is input “L” level for continuousness TSLP, it becones the Stand-by mode
by detecting above situation.
*When “H” level is input, it becomes the Active mode at once.
2. In Regular-Rotation
• PWM pin control
HYS
HYS
IN1-IN2
PWM1
OUT1
OUT2
FG
RD
• Truth table of mode in Regular-Rotation at PWM pin
IN1
IN2
H
L
L
H
PWM
OUT1
OUT2
H
H
L
L
L
L
H
L
H
L
L
L
FG
Mode
Drive
L
Regenerate
Drive
OFF
Regenerate
No.A2143-9/11
LV8068V
• VCONT/RMI pin control
RMI
CPWM
VCONT
PWM2
PWM Duty=100%
VCONT Control
HYS
IN1-IN2
RMI Control
PWM Duty=0%
HYS
OUT1
OUT2
FG
FD
• Truth table of mode in Regular-Rotation at VCONT/RMI pin
IN1
H
L
IN2
*PWM2
OUT1
OUT2
H
H
L
L
L
L
H
L
H
L
L
L
L
H
FG
Mode
Drive
L
Regenerate
Drive
OFF
Regenerate
*: IC's internal signal
No.A2143-10/11
LV8068V
3. In Motor-Lock
Motor Lock
Motor re-rotation
IN1-IN2
OUT1
OUT2
FG
RD
FG detection
TACT (=0.5 S (typ))
TDET (4.5 S (typ))
Startup support 50% Duty
Waiting FG pulse
Motor protection
Release
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PS No.A2143-11/11
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