CAT4016 D

CAT4016, CAV4016
16-Channel Constant
Current LED Driver
Description
The CAT4016 is a 16 channel constant current driver for LED
billboard and other general display applications. LED channel
currents are programmed together via an external RSET resistor. Low
output voltage operation on the LED channels as low as 0.4 V (for 2 to
100 mA LED current) allows for more power efficient designs.
A high−speed 4−wire serial interface of up to 25 MHz clock
frequency controls each individual channel using a shift register and
latch configuration. A serial output data pin (SOUT) allows multiple
devices to be cascaded and programmed via one serial interface. The
device also includes a blanking control pin (BLANK) that can be used
to disable all channels independently of the interface.
Thermal shutdown protection is incorporated in the device to
disable the LED outputs if the die temperature exceeds a set limit.
The device is available in the 24−lead SOIC, TSSOP and the
compact TQFN 4 x 4 mm packages.
•
16 Constant Current−sink Channels
Serial Interface up to 25 MHz Clock Frequency
3 V to 5.5 V Logic Supply
LED Current Range from 2 mA to 100 mA
LED Current set by External RSET Resistor
300 mV LED Dropout at 30 mA
Thermal Shutdown Protection
Available in 24−lead SOIC, TSSOP and 4 x 4 mm TQFN Packages
CAV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•
•
•
•
SOIC−24
W SUFFIX
CASE 751BK
TSSOP−24
Y SUFFIX
CASE 948AR
TQFN−24
HV6 SUFFIX
CASE 510AM
MARKING DIAGRAMS (Top Views)
Features
•
•
•
•
•
•
•
•
•
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Billboard Display
Marquee Display
Instrument Display
General Purpose Display
SOIC−24
TSSOP−24
A3B
CAT4016WO
FYMXXXX
OAB
CAT4016YO
3YMXXX
CAT4016W =
CAT4016W−T1
CAT4016Y =
CAT4016Y−T2
TQFN−24
LAAA
AXXX
YMCC
LAAD
AXXX
YMCC
LAAA =
CAT4016HV6−T2
LAAD =
CAT4016HV6−GT2
VAAA
AXXX
YMCC
VAAA =
CAV4016HV6−T2*
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
*Product under development.
A = Assembly Location
3 = Lead Finish − Matte−Tin
B = Product Revision (Fixed as “B”)
O = Leave Blank
F = Fab Code
Y or YY = Production Year (Last 1 or 2 Digits)
M = Production Month (1−9, A, B, C)
WW = Production Week (01 − 52)
CC = Country Code (Last Two Digits)
XXX or XXXX = Last 3 or 4 Digits
XXX or XXXX = of Assembly Lot Number
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of
this data sheet.
© Semiconductor Components Industries, LLC, 2010
July, 2015 − Rev. 5
1
Publication Order Number:
CAT4016/D
CAT4016, CAV4016
VDD
RSET
SOUT
BLANK
LED16
LED15
PIN CONNECTIONS
1
GND
SIN
CLK
LATCH
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
VDD
RSET
SOUT
BLANK
LED16
LED15
LED14
LED13
LED12
LED11
LED10
LED9
1
GND
SIN
CLK
LATCH
LED1
LED2
LED14
LED3
LED4
LED5
LED6
LED7
LED8
LED13
LED12
LED11
LED10
LED9
24−Lead SOIC (W), TSSOP (Y)
24−Lead TQFN (HV6)
VIN
3 V to
5.5 V
1 mF
20 mA
CONTROLLER
VDD LED1 LED2
LED16
BLANK
LATCH
CAT4016
SOUT
to next
device
SIN
RSET
CLK
GND
3 kW
Figure 1. Typical Application Circuit
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
6
V
−0.3 V to VDD+0.3 V
V
6
V
150
mA
Storage Temperature Range
−55 to +160
_C
Junction Temperature Range
−40 to +150
_C
300
_C
VDD Supply Voltage
Logic input/output voltage (SIN, SOUT, CLK, BLANK, LATCH)
LEDn voltage
DC output current on LED1 to LED16
Lead Soldering Temperature (10 sec.)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 2. RECOMMENDED OPERATING CONDITIONS
Parameter
Range
Unit
VDD
3.0 to 5.5
V
Voltage applied to LED1 to LED16
0.4 to 5.5
V
up to 100
mA
−40 to +85
−40 to +125
_C
LED current RSET control range
Ambient Temperature Range
CAT4016
CAV4016*
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*Product under development.
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2
CAT4016, CAV4016
Table 3. ELECTRICAL OPERATING CHARACTERISTICS
(VDD = 5.0 V, TAMB = 25°C, over recommended operating conditions unless specified otherwise.)
Name
Conditions
Min
Typ
Max
Units
LED Current (any channel)
VLED = 1 V, RSET = 3 kW
18
20
22
mA
VLED = 1 V, RSET = 1.5 kW
36
40
44
Symbol
DC CHARACTERISTICS
ILED−ACC
ILED−MAT
LED Current Matching
(ILED − ILEDAVR) / ILEDAVR
VLED = 1 V, RSET = 750 W
80
VLED = 1 V, RSET = 3 kW
±1.5
VLED = 1 V, RSET = 1.5 kW
−6.0
±1.5
VLED = 1 V, RSET = 750 W
±2.0
%
+6.0
ΔIVDD
LED current regulation vs. VDD
VDD within 4.5 V and 5.5 V
LED current 30 mA
±0.1
%/V
ΔIVLED
LED current regulation vs. VLED
VLED within 1 V and 3 V
LED current 30 mA
±0.05
%/V
IDDOFF
Supply Current (all outputs off)
RSET = 3 kW
3
RSET = 750 W
8.5
RSET = 3 kW
4
RSET = 750 W
10
IDDON
Supply Current (all outputs on)
ILKG
LEDn output Leakage
VLED = 5 V, outputs off
−1
8
mA
9
mA
1
mA
RLATCH
LATCH Pull−down Resistance
100
180
300
kW
RBLANK
BLANK Pull−up Resistance
100
180
300
kW
VIH
VIL
Logic high input voltage
Logic low input voltage
0.7xVDD
VHYS
Logic input hysteresis voltage
IIL
Logic Input leakage current
(CLK, SIN)
VI = VDD or GND
−5
VOH
VOL
SOUT logic high output voltage
SOUT logic low output voltage
IOH = −1 mA
IOL = 1 mA
VCC−0.3 V
VRSET
RSET Regulated Voltage
V
0.3xVDD
0.1xVDD
0
V
5
mA
V
0.3
1.17
1.20
1.23
V
TSD
Thermal Shutdown
160
°C
THYST
Thermal Hysteresis
20
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
CAT4016, CAV4016
Table 4. TIMING CHARACTERISTICS
(For 3.0 V ≤ VDD ≤ 5.5 V, TAMB = 25°C, unless specified otherwise.)
Name
Symbol
Min
(Note 1)
Conditions
Typ
(Note 2)
Max
(Note 1)
Units
25
MHz
CLK
fclk
CLK Clock Frequency
tcwh
CLK Pulse Width High
20
ns
tcwl
CLK Pulse Width Low
20
ns
tssu
Setup time SIN to CLK
4
ns
tsh
Hold time SIN to CLK
4
ns
tlwh
LATCH Pulse width
20
ns
Tlh
Hold time LATCH to CLK
4
ns
Tlsu
Setup time LATCH to CLK
Channel Stagger Delay
800
ns
tld
LED1 Propagation delay
LATCH to LED1 off/on
SIN
LATCH
LEDn
40
300
ns
40
ns
tls
LED Propagation delay stagger
LED(n) to LED(n+1)
17
tlst
LED Propagation delay stagger total
LED1 to LED16
250
tbd
BLANK Propagation delay
BLANK to LED(n) off/on
60
300
ns
tlr
LED rise time (10% to 90%)
Pull−up resistor = 50 W to 3.0 V
40
200
ns
tlf
LED fall time (90% to 10%)
Pull−up resistor = 50 W to 3.0 V
30
250
ns
tor
SOUT rise time (10% to 90%)
CL = 15 pF
5
tof
SOUT fall time (90% to 10%)
CL = 15 pF
tod
Propagation delay time SOUT
CLK to SOUT
ns
SOUT
5
8
15
1. All min and max values are guaranteed by design.
2. VDD = 5 V, LED current 30 mA.
1 mF
VDD
VDD
Rp
50 W
Rp
50 W
CONTROLLER
LED1
BLANK
LATCH
CAT4016
LED16
SIN
V1
CLK
SOUT
RSET
ns
GND
Cl
15 pF
RSET
Figure 2. Test Circuit for AC Characteristics
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4
3V
ns
25
ns
CAT4016, CAV4016
1/fclk
CLK
tssu
tsh
tcwl
tcwh
SIN
tod
SOUT
tlh
tlsu
LATCH
tlwh
Figure 3. Serial Input Timing Diagram
tld
LATCH
tbd
BLANK
tls
LED1
LED2
tlst = 15 tls
LED16
Figure 4. LED Output Timing Diagram
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5
CAT4016, CAV4016
TYPICAL PERFORMANCE CHARACTERISTICS
70
6.0
60
5.5
SUPPLY CURRENT (mA)
LED CURRENT (mA)
(VDD = 5.0 V, LED current 30 mA, all LEDs On, TAMB = 25°C unless otherwise specified.)
50
40
30
20
10
0
0.3
0.6
0.9
1.2
ALL LED’s OFF
4.0
3.5
1.5
3.0
3.5
4.0
4.5
5.0
5.5
LED PIN (V)
VDD (V)
Figure 5. LED Current vs. LED Pin Voltage
Figure 6. Supply Current vs. VDD Pin Voltage
31.5
12
31.0
10
SUPPLY CURRENT (mA)
LED CURRENT (mA)
4.5
3.0
0
30.5
30.0
29.5
29.0
8
ALL LED’s ON
6
ALL LED’s OFF
4
2
0
28.5
3.0
3.5
4.0
4.5
5.0
0
5.5
0.5
1.0
1.5
VDD (V)
RSET CURRENT (mA)
Figure 7. LED Current vs. VDD Pin Voltage
Figure 8. Supply Current vs. RSET Current
2.0
100
1.30
80
LED CURRENT (mA)
1.25
RSET PIN (V)
ALL LED’s ON
5.0
1.20
1.15
60
40
20
1.10
0
3.0
3.5
4.0
4.5
5.0
5.5
0.1
1
10
VDD (V)
RSET (kW)
Figure 9. RSET Voltage vs. VDD Pin Voltage
Figure 10. LED Current vs. RSET Resistor
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6
100
CAT4016, CAV4016
TYPICAL PERFORMANCE CHARACTERISTICS
(VDD = 5.0 V, LED current 30 mA, all LEDs On, TAMB = 25°C unless otherwise specified.)
1.30
31.5
31.0
LED CURRENT (mA)
RSET PIN (V)
1.25
1.20
1.15
30.5
30.0
29.5
29.0
0
50
100
28.5
−50
150
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. RSET Voltage vs. Temperature
Figure 12. LED Current vs. Temperature
30
30
25
25
PULL−UP CURRENT (mA)
PULL−DOWN CURRENT (mA)
1.10
−50
20
15
10
5
0
20
15
10
5
0
0
1
2
3
4
5
0
1
2
3
4
LATCH VOLTAGE (V)
BLANK VOLTAGE (V)
Figure 13. Internal Pull−Down Current
(LATCH Pin)
Figure 14. Internal Pull−Up Current
(BLANK Pin)
100
DUTY CYCLE (%)
80
60
40
20
0
0
5
10
15
20
25
30
LED CURRENT (mA)
Figure 15. PWM Dimming on BLANK Pin
(f = 10 kHz)
Figure 16. BLANK Transient Response
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5
CAT4016, CAV4016
Table 5. PIN DESCRIPTION
Name
Function
GND
Ground
SIN
Serial data input pin
CLK
Serial clock input pin
LATCH
LED1−LED16
Latch serial data to output registers
LED channel 1 to 16 cathode terminals
BLANK
Enable / disable all channels
SOUT
Serial data output pin.
RSET
LED current set pin
VDD
Positive supply Voltage
TAB (TQFN package only)
Connect to GND on the PCB
Pin Function
GND is the ground reference pin for the device. This pin
must be connected to the ground plane on the PCB.
SIN is the serial data input. Data is loaded into the internal
register on each rising edge of CLK.
CLK is the serial clock input. On each rising CLK edge, data
is transferred from SIN to the internal 16−bit serial shift
register.
LATCH is the latch data input. On the rising edge of
LATCH, data is loaded from the 16−bit serial shift register
into the output register latch. On the falling edge, this data
is latched in the output register and isolated from the state of
the serial shift register.
LED1 – LED16 are the LED current sink channels. These
pins are connected to the LED cathodes. The current sinks
drive the LEDs with a current equal to 50 times RSET pin
current. For the LED sink to operate correctly, the voltage on
the LED pin must be above 0.4 V.
BLANK is the LED channel enable and disable input pin.
When low, LEDs are enabled according to the output latch
register content. When high, all LEDs are off, while
preserving the data in the output latch register.
SOUT is the serial data output of the 16−bit serial shift
register. This pin is used to cascade several devices on the
serial bus. The SOUT pin is then connected to the SIN input
of the next device on the serial bus to cascade.
RSET is the LED current setting pin. A resistor is connected
between this pin and ground. Each LED channel current is
set to 50 times the current pulled out of the pin. The RSET
pin voltage is regulated to 1.2 V.
VDD is the positive supply pin voltage for the entire device.
A small 1 mF ceramic is recommended close to pin.
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CAT4016, CAV4016
Block Diagram
LED1 LED2 LED3
LED16
VDD
+
VIN
+
CURRENT
SINKS
Current
Setting
BLANK
RSET
1.2 V Ref
GND
LATCH
SIN
LATCHES
L1
L2
L3
L16
SHIFT
REGISTER
S1
S2
S3
S16
SOUT
CLK
Figure 17. CAT4016 Functional Block Diagram
Basic Operation
The CAT4016 uses 16 tightly matched current sinks to
accurately regulate the LED current in each channel. The
external resistor, RSET, is used to set the LED channel
current to 50 times the current in RSET.
LED current + 50
Pull−up and pull−down resistors are internally provided to
set the state of the BLANK and LATCH pins to the off−state
when not externally driven.
Serial Interface
1.2
R SET
A high−speed serial 4−wire interface is provided to
program the state of each LED on or off. The interface
contains a 16−bit serial to parallel shift register (S1−S16)
and a 16−bit latch (L1−L16). Programming the serial to
parallel register is accomplished via SIN and CLK input
pins. On each rising edge of the CLK signal, the data from
SIN is moved through the shift register serially. Data is also
moved out of SOUT which can be connected to a next device
if programming more than one device on the same interface.
On the rising edge of LATCH, the data contents of the
serial to parallel shift register is reflected in the latches. On
the falling edge of LATCH, the state of the serial to parallel
register at that particular time is saved in the latches and does
not change irrespective of the contents of the serial to
parallel register.
BLANK is used to disable all LEDs (turn off)
simultaneously while maintaining the same data in the latch
register. When low, the LED outputs reflect the data in the
latches. When high, all outputs are high impedance (zero
current).
Tight current regulation for all channels is possible over
a wide range of input and LED voltages due to independent
current sensing circuitry on each channel. The LED
channels have a maximum dropout of 0.4 V for most current
and supply voltage conditions. This helps improve the heat
dissipation and efficiency of the LED driver.
Upon power−up, an under−voltage lockout circuit clears
all latches and shift registers and sets all outputs to off. Once
the under−voltage lockout threshold has been reached the
device can be programmed.
The driver delays the activation of each consecutive LED
output channel by 17 ns (typical). Relative to LED1, LED2
is delayed by 17 ns, LED3 by 34 ns and LED16 by 250 ns
typical. The delay is introduced when LATCH is activated.
The delay minimizes the inrush current on the LED supply
by staggering the turn on and off current spikes over a period
of time and therefore allowing usage of smaller bypass
capacitors.
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9
CAT4016, CAV4016
PACKAGE DIMENSIONS
SOIC−24, 300 mils
CASE 751BK
ISSUE O
E1
SYMBOL
MIN
A
2.35
2.65
A1
0.10
0.30
E
e
PIN#1 IDENTIFICATION
MAX
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
15.20
15.40
E
10.11
10.51
E1
7.34
7.60
1.27 BSC
e
b
NOM
h
0.25
0.75
L
0.40
1.27
θ
0º
8º
θ1
5º
15º
TOP VIEW
h
D
A2
A
A1
SIDE VIEW
h
q1
q
q1
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
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10
c
CAT4016, CAV4016
PACKAGE DIMENSIONS
TSSOP24, 4.4x7.8
CASE 948AR
ISSUE A
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.80
7.90
E
6.25
6.40
6.55
E1
4.30
4.40
4.50
e
L
0.65 BSC
0.50
L1
θ
0.60
0.70
1.00 REF
0º
8º
e
TOP VIEW
D
c
A2
A θ1
L
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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11
L1
CAT4016, CAV4016
PACKAGE DIMENSIONS
QSOP−24, 150 mils
CASE 492AB
ISSUE O
D
SYMBOL
MIN
A
1.37
1.73
A1
0.10
0.25
b
0.20
0.30
E1 E
MAX
c
0.19
0.25
D
8.56
8.74
E
5.82
6.19
E1
3.81
3.98
e
0.635 BSC
h
0.28
0.48
L
0.41
0.86
L2
θ1
θ2
e
NOM
b
0.254 BSC
0º
8º
7º BSC
TOP VIEW
q2
h
A
A1
q1
c
L
L2
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-137.
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12
CAT4016, CAV4016
PACKAGE DIMENSIONS
TQFN24, 4x4 AR
CASE 510AM
ISSUE O
A
D
DETAIL A
E
E2
PIN#1 ID
PIN#1 INDEX AREA
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
−
0.05
A3
b
0.20
2.40
0.25
e
L
0.30
−
DETAIL A
2.90
4.00 BSC
2.40
e
L
b
4.00 BSC
E
E2
BOTTOM VIEW
0.20 REF
D
D2
D2
A1
−
2.90
0.50 BSC
0.30
−
0.50
A
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-220.
(3) Minimum space between leads and flag cannot be smaller than 0.15 mm.
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13
FRONT VIEW
A3
CAT4016, CAV4016
Table 6. ORDERING INFORMATION
Package Marking
Package
Shipping†
CAT4016W-T1
CAT4016W
SOIC24 (Note 7)
(Pb−Free)
1000 / Tape & Reel
CAT4016Y-T2
CAT4016Y
TSSOP24 (Note 7)
(Pb−Free)
2000 / Tape & Reel
CAT4016HV6-T2
LAAA
TQFN24 (Note 7)
(Pb−Free)
2000 / Tape & Reel
CAT4016HV6-GT2
LAAD
TQFN24 (Note 8)
(Pb−Free)
2000 / Tape & Reel
CAV4016HV6−T2* (Note 3)
VAAA
TQFN24 (Note 7)
(Pb−Free)
2000 / Tape & Reel
Part Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Product under development.
3. CAV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
4. All packages are RoHS−compliant (Pb−Free, Halogen−free).
5. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
6. SOIC package availability in 1000 / Tape & Reel. All other packages are 2000 / Tape & Reel.
7. Matte−Tin Plated Finish (RoHS−compliant).
8. NiPdAu Plated Finish (RoHS−compliant).
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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